自学教程：C++ AH5212函数代码示例

/* * Reads the Interrupt Status Register value from the NIC, thus deasserting * the interrupt line, and returns both the masked and unmasked mapped ISR * values.  The value returned is mapped to abstract the hw-specific bit * locations in the Interrupt Status Register. * * (*masked) is cleared on initial call. * * Returns: A hardware-abstracted bitmap of all non-masked-out *          interrupts pending, as well as an unmasked value */HAL_BOOLar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked){	uint32_t isr, isr0, isr1, sync_cause = 0, o_sync_cause = 0;	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;#ifdef	AH_INTERRUPT_DEBUGGING	/*	 * Blank the interrupt debugging area regardless.	 */	bzero(&ah->ah_intrstate, sizeof(ah->ah_intrstate));	ah->ah_syncstate = 0;#endif	/*	 * Verify there's a mac interrupt and the RTC is on.	 */	if (AR_SREV_HOWL(ah)) {		*masked = 0;		isr = OS_REG_READ(ah, AR_ISR);	} else {		if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&		    (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)			isr = OS_REG_READ(ah, AR_ISR);		else			isr = 0;#ifdef	AH_INTERRUPT_DEBUGGING		ah->ah_syncstate =#endif		o_sync_cause = sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);		sync_cause &= AR_INTR_SYNC_DEFAULT;		*masked = 0;		if (isr == 0 && sync_cause == 0)			return AH_FALSE;	}#ifdef	AH_INTERRUPT_DEBUGGING	ah->ah_intrstate[0] = isr;	ah->ah_intrstate[1] = OS_REG_READ(ah, AR_ISR_S0);	ah->ah_intrstate[2] = OS_REG_READ(ah, AR_ISR_S1);	ah->ah_intrstate[3] = OS_REG_READ(ah, AR_ISR_S2);	ah->ah_intrstate[4] = OS_REG_READ(ah, AR_ISR_S3);	ah->ah_intrstate[5] = OS_REG_READ(ah, AR_ISR_S4);	ah->ah_intrstate[6] = OS_REG_READ(ah, AR_ISR_S5);#endif	if (isr != 0) {		struct ath_hal_5212 *ahp = AH5212(ah);		uint32_t mask2;		mask2 = 0;		if (isr & AR_ISR_BCNMISC) {			uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);			if (isr2 & AR_ISR_S2_TIM)				mask2 |= HAL_INT_TIM;			if (isr2 & AR_ISR_S2_DTIM)				mask2 |= HAL_INT_DTIM;			if (isr2 & AR_ISR_S2_DTIMSYNC)				mask2 |= HAL_INT_DTIMSYNC;			if (isr2 & (AR_ISR_S2_CABEND ))				mask2 |= HAL_INT_CABEND;			if (isr2 & AR_ISR_S2_GTT)				mask2 |= HAL_INT_GTT;			if (isr2 & AR_ISR_S2_CST)				mask2 |= HAL_INT_CST;				if (isr2 & AR_ISR_S2_TSFOOR)				mask2 |= HAL_INT_TSFOOR;			/*			 * Don't mask out AR_BCNMISC; instead mask			 * out what causes it.			 */			OS_REG_WRITE(ah, AR_ISR_S2, isr2);			isr &= ~AR_ISR_BCNMISC;		}		if (isr == 0xffffffff) {			*masked = 0;			return AH_FALSE;		}		*masked = isr & HAL_INT_COMMON;		if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))			*masked |= HAL_INT_RX;		if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))			*masked |= HAL_INT_TX;//.........这里部分代码省略.........

/* * Restore/reset the ANI parameters and reset the statistics. * This routine must be called for every channel change. */voidar5212AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,	HAL_OPMODE opmode, int restore){	struct ath_hal_5212 *ahp = AH5212(ah);	HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);	/* XXX bounds check ic_devdata */	struct ar5212AniState *aniState = &ahp->ah_ani[chan->ic_devdata];	uint32_t rxfilter;	if ((ichan->privFlags & CHANNEL_ANI_INIT) == 0) {		OS_MEMZERO(aniState, sizeof(*aniState));		if (IEEE80211_IS_CHAN_2GHZ(chan))			aniState->params = &ahp->ah_aniParams24;		else			aniState->params = &ahp->ah_aniParams5;		ichan->privFlags |= CHANNEL_ANI_INIT;		HALASSERT((ichan->privFlags & CHANNEL_ANI_SETUP) == 0);	}	ahp->ah_curani = aniState;#if 0	ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s/n",	    __func__, chan->ic_freq, chan->ic_flags, restore, opmode,	    ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");#else	HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s/n",	    __func__, chan->ic_freq, chan->ic_flags, restore, opmode,	    ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");#endif	OS_MARK(ah, AH_MARK_ANI_RESET, opmode);	/*	 * Turn off PHY error frame delivery while we futz with settings.	 */	rxfilter = ah->ah_getRxFilter(ah);	ah->ah_setRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);	/*	 * If ANI is disabled at this point, don't set the default	 * ANI parameter settings - leave the HAL settings there.	 * This is (currently) needed for reliable radar detection.	 */	if (! ANI_ENA(ah)) {		HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ANI disabled/n",		    __func__);		goto finish;	}	/*	 * Automatic processing is done only in station mode right now.	 */	if (opmode == HAL_M_STA)		ahp->ah_procPhyErr |= HAL_RSSI_ANI_ENA;	else		ahp->ah_procPhyErr &= ~HAL_RSSI_ANI_ENA;	/*	 * Set all ani parameters.  We either set them to initial	 * values or restore the previous ones for the channel.	 * XXX if ANI follows hardware, we don't care what mode we're	 * XXX in, we should keep the ani parameters	 */	if (restore && (ichan->privFlags & CHANNEL_ANI_SETUP)) {		ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,				 aniState->noiseImmunityLevel);		ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,				 aniState->spurImmunityLevel);		ar5212AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,				 !aniState->ofdmWeakSigDetectOff);		ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,				 aniState->cckWeakSigThreshold);		ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,				 aniState->firstepLevel);	} else {		ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);		ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);		ar5212AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,			AH_TRUE);		ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);		ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);		ichan->privFlags |= CHANNEL_ANI_SETUP;	}	/*	 * In case the counters haven't yet been setup; set them up.	 */	enableAniMIBCounters(ah, ahp->ah_curani->params);	ar5212AniRestart(ah, aniState);finish:	/* restore RX filter mask */	ah->ah_setRxFilter(ah, rxfilter);}

static voidar5212AniLowerImmunity(struct ath_hal *ah){	struct ath_hal_5212 *ahp = AH5212(ah);	struct ar5212AniState *aniState;	const struct ar5212AniParams *params;		HALASSERT(ANI_ENA(ah));	aniState = ahp->ah_curani;	params = aniState->params;	if (ANI_ENA_RSSI(ah)) {		int32_t rssi = BEACON_RSSI(ahp);		if (rssi > params->rssiThrHigh) {			/* 			 * Beacon signal is high, leave ofdm weak signal			 * detection off or it may oscillate.  Let it fall			 * through.			 */		} else if (rssi > params->rssiThrLow) {			/*			 * Beacon rssi in mid range, turn on ofdm weak signal			 * detection or lower firstep level.			 */			if (aniState->ofdmWeakSigDetectOff) {				HALDEBUG(ah, HAL_DEBUG_ANI,				    "%s: rssi %d OWSD on/n", __func__, rssi);				ar5212AniControl(ah,				    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,				    AH_TRUE);				return;			}			if (aniState->firstepLevel > 0) {				HALDEBUG(ah, HAL_DEBUG_ANI,				    "%s: rssi %d lower ST %u/n", __func__, rssi,				    aniState->firstepLevel-1);				ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,						 aniState->firstepLevel - 1);				return;			}		} else {			/*			 * Beacon rssi is low, reduce firstep level.			 */			if (aniState->firstepLevel > 0) {				HALDEBUG(ah, HAL_DEBUG_ANI,				    "%s: rssi %d lower ST %u/n", __func__, rssi,				    aniState->firstepLevel-1);				ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,						 aniState->firstepLevel - 1);				return;			}		}	}	/* then lower spur immunity level, down to zero */	if (aniState->spurImmunityLevel > 0) {		HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower SI %u/n",		    __func__, aniState->spurImmunityLevel-1);		ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,				 aniState->spurImmunityLevel - 1);		return;	}	/* 	 * if all else fails, lower noise immunity level down to a min value	 * zero for now	 */	if (aniState->noiseImmunityLevel > 0) {		HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower NI %u/n",		    __func__, aniState->noiseImmunityLevel-1);		ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,				 aniState->noiseImmunityLevel - 1);		return;	}}

static HAL_BOOLar2316SetPowerTable(struct ath_hal *ah,	int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan, 	uint16_t *rfXpdGain){	struct ath_hal_5212 *ahp = AH5212(ah);	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;	const RAW_DATA_STRUCT_2316 *pRawDataset = AH_NULL;	uint16_t pdGainOverlap_t2;	int16_t minCalPower2316_t2;	uint16_t *pdadcValues = ahp->ah_pcdacTable;	uint16_t gainBoundaries[4];	uint32_t reg32, regoffset;	int i, numPdGainsUsed;#ifndef AH_USE_INIPDGAIN	uint32_t tpcrg1;#endif	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x/n",	    __func__, chan->channel,chan->channelFlags);	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];	else if (IS_CHAN_B(chan))		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];	else {		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode/n", __func__);		return AH_FALSE;	}	pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),					  AR_PHY_TPCRG5_PD_GAIN_OVERLAP);    	numPdGainsUsed = ar2316getGainBoundariesAndPdadcsForPowers(ah,		chan->channel, pRawDataset, pdGainOverlap_t2,		&minCalPower2316_t2,gainBoundaries, rfXpdGain, pdadcValues);	HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);#ifdef AH_USE_INIPDGAIN	/*	 * Use pd_gains curve from eeprom; Atheros always uses	 * the default curve from the ini file but some vendors	 * (e.g. Zcomax) want to override this curve and not	 * honoring their settings results in tx power 5dBm low.	 */	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 			 (pRawDataset->pDataPerChannel[0].numPdGains - 1));#else	tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);	tpcrg1 = (tpcrg1 &~ AR_PHY_TPCRG1_NUM_PD_GAIN)		  | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);	switch (numPdGainsUsed) {	case 3:		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING3;		tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);		/* fall thru... */	case 2:		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING2;		tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);		/* fall thru... */	case 1:		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING1;		tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);		break;	}#ifdef AH_DEBUG	if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "		    "pd_gains (default 0x%x, calculated 0x%x)/n",		    __func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);#endif	OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);#endif	/*	 * Note the pdadc table may not start at 0 dBm power, could be	 * negative or greater than 0.  Need to offset the power	 * values by the amount of minPower for griffin	 */	if (minCalPower2316_t2 != 0)		ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2316_t2);	else		ahp->ah_txPowerIndexOffset = 0;	/* Finally, write the power values into the baseband power table */	regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */	for (i = 0; i < 32; i++) {		reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0)  | 			((pdadcValues[4*i + 1] & 0xFF) << 8)  |			((pdadcValues[4*i + 2] & 0xFF) << 16) |			((pdadcValues[4*i + 3] & 0xFF) << 24) ;        		OS_REG_WRITE(ah, regoffset, reg32);		regoffset += 4;	}	OS_REG_WRITE(ah, AR_PHY_TPCRG5, 		     SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 		     SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |		     SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |		     SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |//.........这里部分代码省略.........

/* * Control Adaptive Noise Immunity Parameters */HAL_BOOLar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param){	typedef int TABLE[];	struct ath_hal_5212 *ahp = AH5212(ah);	struct ar5212AniState *aniState = ahp->ah_curani;	const struct ar5212AniParams *params = AH_NULL;		/*	 * This function may be called before there's a current	 * channel (eg to disable ANI.)	 */	if (aniState != AH_NULL)		params = aniState->params;	OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);	switch (cmd) {	case HAL_ANI_NOISE_IMMUNITY_LEVEL: {		u_int level = param;		if (level > params->maxNoiseImmunityLevel) {			HALDEBUG(ah, HAL_DEBUG_ANY,			    "%s: level out of range (%u > %u)/n",			    __func__, level, params->maxNoiseImmunityLevel);			return AH_FALSE;		}		OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,		    AR_PHY_DESIRED_SZ_TOT_DES, params->totalSizeDesired[level]);		OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,		    AR_PHY_AGC_CTL1_COARSE_LOW, params->coarseLow[level]);		OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,		    AR_PHY_AGC_CTL1_COARSE_HIGH, params->coarseHigh[level]);		OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,		    AR_PHY_FIND_SIG_FIRPWR, params->firpwr[level]);		if (level > aniState->noiseImmunityLevel)			ahp->ah_stats.ast_ani_niup++;		else if (level < aniState->noiseImmunityLevel)			ahp->ah_stats.ast_ani_nidown++;		aniState->noiseImmunityLevel = level;		break;	}	case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: {		static const TABLE m1ThreshLow   = { 127,   50 };		static const TABLE m2ThreshLow   = { 127,   40 };		static const TABLE m1Thresh      = { 127, 0x4d };		static const TABLE m2Thresh      = { 127, 0x40 };		static const TABLE m2CountThr    = {  31,   16 };		static const TABLE m2CountThrLow = {  63,   48 };		u_int on = param ? 1 : 0;		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,			AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1ThreshLow[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,			AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2ThreshLow[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,			AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,			AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,			AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,			AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);		if (on) {			OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,				AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);			ahp->ah_stats.ast_ani_ofdmon++;		} else {			OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,				AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);			ahp->ah_stats.ast_ani_ofdmoff++;		}		aniState->ofdmWeakSigDetectOff = !on;		break;	}	case HAL_ANI_CCK_WEAK_SIGNAL_THR: {		static const TABLE weakSigThrCck = { 8, 6 };		u_int high = param ? 1 : 0;		OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,		    AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, weakSigThrCck[high]);		if (high)			ahp->ah_stats.ast_ani_cckhigh++;		else			ahp->ah_stats.ast_ani_ccklow++;		aniState->cckWeakSigThreshold = high;		break;	}	case HAL_ANI_FIRSTEP_LEVEL: {		u_int level = param;		if (level > params->maxFirstepLevel) {			HALDEBUG(ah, HAL_DEBUG_ANY,			    "%s: level out of range (%u > %u)/n",//.........这里部分代码省略.........

/* * Attach for an AR9280 part. */static struct ath_hal *ar9280Attach(uint16_t devid, HAL_SOFTC sc,	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,	HAL_STATUS *status){	struct ath_hal_9280 *ahp9280;	struct ath_hal_5212 *ahp;	struct ath_hal *ah;	uint32_t val;	HAL_STATUS ecode;	HAL_BOOL rfStatus;	int8_t pwr_table_offset;	uint8_t pwr;	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p/n",	    __func__, sc, (void*) st, (void*) sh);	/* NB: memory is returned zero'd */	ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280));	if (ahp9280 == AH_NULL) {		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,		    "%s: cannot allocate memory for state block/n", __func__);		*status = HAL_ENOMEM;		return AH_NULL;	}	ahp = AH5212(ahp9280);	ah = &ahp->ah_priv.h;	ar5416InitState(AH5416(ah), devid, sc, st, sh, status);	/*	 * Use the "local" EEPROM data given to us by the higher layers.	 * This is a private copy out of system flash. The Linux ath9k	 * commit for the initial AR9130 support mentions MMIO flash	 * access is "unreliable." -adrian	 */	if (eepromdata != AH_NULL) {		AH_PRIVATE((ah))->ah_eepromRead = ath_hal_EepromDataRead;		AH_PRIVATE((ah))->ah_eepromWrite = NULL;		ah->ah_eepromdata = eepromdata;	}	/* XXX override with 9280 specific state */	/* override 5416 methods for our needs */	AH5416(ah)->ah_initPLL = ar9280InitPLL;	ah->ah_setAntennaSwitch		= ar9280SetAntennaSwitch;	ah->ah_configPCIE		= ar9280ConfigPCIE;	ah->ah_disablePCIE		= ar9280DisablePCIE;	AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;	AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;	AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;	AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;	AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;	AH5416(ah)->ah_spurMitigate	= ar9280SpurMitigate;	AH5416(ah)->ah_writeIni		= ar9280WriteIni;	AH5416(ah)->ah_olcInit		= ar9280olcInit;	AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation;	AH5416(ah)->ah_setPowerCalTable	= ar9280SetPowerCalTable;	AH5416(ah)->ah_rx_chainmask	= AR9280_DEFAULT_RXCHAINMASK;	AH5416(ah)->ah_tx_chainmask	= AR9280_DEFAULT_TXCHAINMASK;	if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {		/* reset chip */		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip/n",		    __func__);		ecode = HAL_EIO;		goto bad;	}	if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip/n",		    __func__);		ecode = HAL_EIO;		goto bad;	}	/* Read Revisions from Chips before taking out of reset */	val = OS_REG_READ(ah, AR_SREV);	HALDEBUG(ah, HAL_DEBUG_ATTACH,	    "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x/n",	    __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),	    MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));	/* NB: include chip type to differentiate from pre-Sowl versions */	AH_PRIVATE(ah)->ah_macVersion =	    (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;	AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);	AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;	/* setup common ini data; rf backends handle remainder */	if (AR_SREV_MERLIN_20_OR_LATER(ah)) {		HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);		HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);		HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,		    ar9280PciePhy_clkreq_always_on_L1_v2, 2);//.........这里部分代码省略.........

/* * Read the transmit power levels from the structures taken from EEPROM * Interpolate read transmit power values for this channel * Organize the transmit power values into a table for writing into the hardware */static HAL_BOOLar5111SetPowerTable(struct ath_hal *ah,	int16_t *pMinPower, int16_t *pMaxPower,	const struct ieee80211_channel *chan,	uint16_t *rfXpdGain){	uint16_t freq = ath_hal_gethwchannel(ah, chan);	struct ath_hal_5212 *ahp = AH5212(ah);	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;	FULL_PCDAC_STRUCT pcdacStruct;	int i, j;	uint16_t     *pPcdacValues;	int16_t      *pScaledUpDbm;	int16_t      minScaledPwr;	int16_t      maxScaledPwr;	int16_t      pwr;	uint16_t     pcdacMin = 0;	uint16_t     pcdacMax = PCDAC_STOP;	uint16_t     pcdacTableIndex;	uint16_t     scaledPcdac;	PCDACS_EEPROM *pSrcStruct;	PCDACS_EEPROM eepromPcdacs;	/* setup the pcdac struct to point to the correct info, based on mode */	switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) {	case IEEE80211_CHAN_A:	case IEEE80211_CHAN_ST:		eepromPcdacs.numChannels     = ee->ee_numChannels11a;		eepromPcdacs.pChannelList    = ee->ee_channels11a;		eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a;		break;	case IEEE80211_CHAN_B:		eepromPcdacs.numChannels     = ee->ee_numChannels2_4;		eepromPcdacs.pChannelList    = ee->ee_channels11b;		eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b;		break;	case IEEE80211_CHAN_G:	case IEEE80211_CHAN_108G:		eepromPcdacs.numChannels     = ee->ee_numChannels2_4;		eepromPcdacs.pChannelList    = ee->ee_channels11g;		eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g;		break;	default:		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x/n",		    __func__, chan->ic_flags);		return AH_FALSE;	}	pSrcStruct = &eepromPcdacs;	OS_MEMZERO(&pcdacStruct, sizeof(pcdacStruct));	pPcdacValues = pcdacStruct.PcdacValues;	pScaledUpDbm = pcdacStruct.PwrValues;	/* Initialize the pcdacs to dBM structs pcdacs to be 1 to 63 */	for (i = PCDAC_START, j = 0; i <= PCDAC_STOP; i+= PCDAC_STEP, j++)		pPcdacValues[j] = i;	pcdacStruct.numPcdacValues = j;	pcdacStruct.pcdacMin = PCDAC_START;	pcdacStruct.pcdacMax = PCDAC_STOP;	/* Fill out the power values for this channel */	for (j = 0; j < pcdacStruct.numPcdacValues; j++ )		pScaledUpDbm[j] = ar5212GetScaledPower(freq,			pPcdacValues[j], pSrcStruct);	/* Now scale the pcdac values to fit in the 64 entry power table */	minScaledPwr = pScaledUpDbm[0];	maxScaledPwr = pScaledUpDbm[pcdacStruct.numPcdacValues - 1];	/* find minimum and make monotonic */	for (j = 0; j < pcdacStruct.numPcdacValues; j++) {		if (minScaledPwr >= pScaledUpDbm[j]) {			minScaledPwr = pScaledUpDbm[j];			pcdacMin = j;		}		/*		 * Make the full_hsh monotonically increasing otherwise		 * interpolation algorithm will get fooled gotta start		 * working from the top, hence i = 63 - j.		 */		i = (uint16_t)(pcdacStruct.numPcdacValues - 1 - j);		if (i == 0)			break;		if (pScaledUpDbm[i-1] > pScaledUpDbm[i]) {			/*			 * It could be a glitch, so make the power for			 * this pcdac the same as the power from the			 * next highest pcdac.			 */			pScaledUpDbm[i - 1] = pScaledUpDbm[i];		}	}//.........这里部分代码省略.........

/* * Reads EEPROM header info from device structure and programs * all rf registers * * REQUIRES: Access to the analog rf device */static HAL_BOOLar5111SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,	uint16_t modesIndex, uint16_t *rfXpdGain){	uint16_t freq = ath_hal_gethwchannel(ah, chan);	struct ath_hal_5212 *ahp = AH5212(ah);	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;	uint16_t rfXpdGainFixed, rfPloSel, rfPwdXpd, gainI;	uint16_t tempOB, tempDB;	uint32_t ob2GHz, db2GHz, rfReg[NELEM(ar5212Bank6_5111)];	int i, regWrites = 0;	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u/n",	    __func__, chan->ic_freq, chan->ic_flags, modesIndex);	/* Setup rf parameters */	switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {	case IEEE80211_CHAN_A:		if (4000 < freq && freq < 5260) {			tempOB = ee->ee_ob1;			tempDB = ee->ee_db1;		} else if (5260 <= freq && freq < 5500) {			tempOB = ee->ee_ob2;			tempDB = ee->ee_db2;		} else if (5500 <= freq && freq < 5725) {			tempOB = ee->ee_ob3;			tempDB = ee->ee_db3;		} else if (freq >= 5725) {			tempOB = ee->ee_ob4;			tempDB = ee->ee_db4;		} else {			/* XXX when does this happen??? */			tempOB = tempDB = 0;		}		ob2GHz = db2GHz = 0;		rfXpdGainFixed = ee->ee_xgain[headerInfo11A];		rfPloSel = ee->ee_xpd[headerInfo11A];		rfPwdXpd = !ee->ee_xpd[headerInfo11A];		gainI = ee->ee_gainI[headerInfo11A];		break;	case IEEE80211_CHAN_B:		tempOB = ee->ee_obFor24;		tempDB = ee->ee_dbFor24;		ob2GHz = ee->ee_ob2GHz[0];		db2GHz = ee->ee_db2GHz[0];		rfXpdGainFixed = ee->ee_xgain[headerInfo11B];		rfPloSel = ee->ee_xpd[headerInfo11B];		rfPwdXpd = !ee->ee_xpd[headerInfo11B];		gainI = ee->ee_gainI[headerInfo11B];		break;	case IEEE80211_CHAN_G:	case IEEE80211_CHAN_PUREG:	/* NB: really 108G */		tempOB = ee->ee_obFor24g;		tempDB = ee->ee_dbFor24g;		ob2GHz = ee->ee_ob2GHz[1];		db2GHz = ee->ee_db2GHz[1];		rfXpdGainFixed = ee->ee_xgain[headerInfo11G];		rfPloSel = ee->ee_xpd[headerInfo11G];		rfPwdXpd = !ee->ee_xpd[headerInfo11G];		gainI = ee->ee_gainI[headerInfo11G];		break;	default:		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x/n",		    __func__, chan->ic_flags);		return AH_FALSE;	}	HALASSERT(1 <= tempOB && tempOB <= 5);	HALASSERT(1 <= tempDB && tempDB <= 5);	/* Bank 0 Write */	for (i = 0; i < NELEM(ar5212Bank0_5111); i++)		rfReg[i] = ar5212Bank0_5111[i][modesIndex];	if (IEEE80211_IS_CHAN_2GHZ(chan)) {		ar5212ModifyRfBuffer(rfReg, ob2GHz, 3, 119, 0);		ar5212ModifyRfBuffer(rfReg, db2GHz, 3, 122, 0);	}	HAL_INI_WRITE_BANK(ah, ar5212Bank0_5111, rfReg, regWrites);	/* Bank 1 Write */	HAL_INI_WRITE_ARRAY(ah, ar5212Bank1_5111, 1, regWrites);	/* Bank 2 Write */	HAL_INI_WRITE_ARRAY(ah, ar5212Bank2_5111, modesIndex, regWrites);	/* Bank 3 Write */	HAL_INI_WRITE_ARRAY(ah, ar5212Bank3_5111, modesIndex, regWrites);	/* Bank 6 Write */	for (i = 0; i < NELEM(ar5212Bank6_5111); i++)		rfReg[i] = ar5212Bank6_5111[i][modesIndex];//.........这里部分代码省略.........

static HAL_BOOLar2133GetChannelMaxMinPower(struct ath_hal *ah,	const struct ieee80211_channel *chan,	int16_t *maxPow, int16_t *minPow){#if 0    struct ath_hal_5212 *ahp = AH5212(ah);    int numChannels=0,i,last;    int totalD, totalF,totalMin;    EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;    EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;    *maxPow = 0;    if (IS_CHAN_A(chan)) {        powerArray = ahp->ah_modePowerArray5112;        data = powerArray[headerInfo11A].pDataPerChannel;        numChannels = powerArray[headerInfo11A].numChannels;    } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {        /* XXX - is this correct? Should we also use the same power for turbo G? */        powerArray = ahp->ah_modePowerArray5112;        data = powerArray[headerInfo11G].pDataPerChannel;        numChannels = powerArray[headerInfo11G].numChannels;    } else if (IS_CHAN_B(chan)) {        powerArray = ahp->ah_modePowerArray5112;        data = powerArray[headerInfo11B].pDataPerChannel;        numChannels = powerArray[headerInfo11B].numChannels;    } else {        return (AH_TRUE);    }    /* Make sure the channel is in the range of the TP values     *  (freq piers)     */    if ((numChannels < 1) ||        (chan->channel < data[0].channelValue) ||        (chan->channel > data[numChannels-1].channelValue))        return(AH_FALSE);    /* Linearly interpolate the power value now */    for (last=0,i=0;         (i<numChannels) && (chan->channel > data[i].channelValue);         last=i++);    totalD = data[i].channelValue - data[last].channelValue;    if (totalD > 0) {        totalF = data[i].maxPower_t4 - data[last].maxPower_t4;        *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);        totalMin = ar2133GetMinPower(ah,&data[i]) - ar2133GetMinPower(ah, &data[last]);        *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar2133GetMinPower(ah, &data[last])*totalD)/totalD);        return (AH_TRUE);    } else {        if (chan->channel == data[i].channelValue) {            *maxPow = data[i].maxPower_t4;            *minPow = ar2133GetMinPower(ah, &data[i]);            return(AH_TRUE);        } else            return(AH_FALSE);    }#else    *maxPow = *minPow = 0;	return AH_FALSE;#endif}

/* * Set all the beacon related bits on the h/w for stations * i.e. initializes the corresponding h/w timers; * also tells the h/w whether to anticipate PCF beacons */voidar5212SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs){	struct ath_hal_5212 *ahp = AH5212(ah);	uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod;	HALASSERT(bs->bs_intval != 0);	/* if the AP will do PCF */	if (bs->bs_cfpmaxduration != 0) {		/* tell the h/w that the associated AP is PCF capable */		OS_REG_WRITE(ah, AR_STA_ID1,			OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);		/* set CFP_PERIOD(1.024ms) register */		OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);		/* set CFP_DUR(1.024ms) register to max cfp duration */		OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);		/* set TIMER2(128us) to anticipated time of next CFP */		OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);	} else {		/* tell the h/w that the associated AP is not PCF capable */		OS_REG_WRITE(ah, AR_STA_ID1,			OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);	}	/*	 * Set TIMER0(1.024ms) to the anticipated time of the next beacon.	 */	OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);	/*	 * Start the beacon timers by setting the BEACON register	 * to the beacon interval; also write the tim offset which	 * we should know by now.  The code, in ar5211WriteAssocid,	 * also sets the tim offset once the AID is known which can	 * be left as such for now.	 */	OS_REG_WRITE(ah, AR_BEACON, 		(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))		| SM(bs->bs_intval, AR_BEACON_PERIOD)		| SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)	);	/*	 * Configure the BMISS interrupt.  Note that we	 * assume the caller blocks interrupts while enabling	 * the threshold.	 */	HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));	ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)			| SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);	/*	 * Program the sleep registers to correlate with the beacon setup.	 */	/*	 * Oahu beacons timers on the station were used for power	 * save operation (waking up in anticipation of a beacon)	 * and any CFP function; Venice does sleep/power-save timers	 * differently - so this is the right place to set them up;	 * don't think the beacon timers are used by venice sta hw	 * for any useful purpose anymore	 * Setup venice's sleep related timers	 * Current implementation assumes sw processing of beacons -	 *   assuming an interrupt is generated every beacon which	 *   causes the hardware to become awake until the sw tells	 *   it to go to sleep again; beacon timeout is to allow for	 *   beacon jitter; cab timeout is max time to wait for cab	 *   after seeing the last DTIM or MORE CAB bit	 */#define CAB_TIMEOUT_VAL     10 /* in TU */#define BEACON_TIMEOUT_VAL  10 /* in TU */#define SLEEP_SLOP          3  /* in TU */	/*	 * For max powersave mode we may want to sleep for longer than a	 * beacon period and not want to receive all beacons; modify the	 * timers accordingly; make sure to align the next TIM to the	 * next DTIM if we decide to wake for DTIMs only	 */	beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;	HALASSERT(beaconintval != 0);	if (bs->bs_sleepduration > beaconintval) {		HALASSERT(roundup(bs->bs_sleepduration, beaconintval) ==				bs->bs_sleepduration);		beaconintval = bs->bs_sleepduration;	}	dtimperiod = bs->bs_dtimperiod;	if (bs->bs_sleepduration > dtimperiod) {		HALASSERT(dtimperiod == 0 ||			roundup(bs->bs_sleepduration, dtimperiod) ==//.........这里部分代码省略.........

static voidar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan){	u_int modesIndex, freqIndex;	int regWrites = 0;	int i;	const HAL_INI_ARRAY *ia;	/* Setup the indices for the next set of register array writes */	/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */	if (IEEE80211_IS_CHAN_2GHZ(chan)) {		freqIndex = 2;		if (IEEE80211_IS_CHAN_HT40(chan))			modesIndex = 3;		else if (IEEE80211_IS_CHAN_108G(chan))			modesIndex = 5;		else			modesIndex = 4;	} else {		freqIndex = 1;		if (IEEE80211_IS_CHAN_HT40(chan) ||		    IEEE80211_IS_CHAN_TURBO(chan))			modesIndex = 2;		else			modesIndex = 1;	}	/* Set correct Baseband to analog shift setting to access analog chips. */	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);	OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);	/*	 * This is unwound because at the moment, there's a requirement	 * for Merlin (and later, perhaps) to have a specific bit fixed	 * in the AR_AN_TOP2 register before writing it.	 */	ia = &AH5212(ah)->ah_ini_modes;#if 0	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,	    modesIndex, regWrites);#endif	HALASSERT(modesIndex < ia->cols);	for (i = 0; i < ia->rows; i++) {		uint32_t reg = HAL_INI_VAL(ia, i, 0);		uint32_t val = HAL_INI_VAL(ia, i, modesIndex);		if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup)			val &= ~AR_AN_TOP2_PWDCLKIND;		OS_REG_WRITE(ah, reg, val);		/* Analog shift register delay seems needed for Merlin - PR kern/154220 */		if (reg >= 0x7800 && reg < 0x7900)			OS_DELAY(100);		DMA_YIELD(regWrites);	}	if (AR_SREV_MERLIN_20_OR_LATER(ah)) {		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,		    modesIndex, regWrites);		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,		    modesIndex, regWrites);	}	/* XXX Merlin 100us delay for shift registers */	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,	    1, regWrites);	if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {		/* 5GHz channels w/ Fast Clock use different modal values */		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,		    modesIndex, regWrites);	}}

/* * Places the device in and out of reset and then places sane * values in the registers based on EEPROM config, initialization * vectors (as determined by the mode), and station configuration * * bChannelChange is used to preserve DMA/PCU registers across * a HW Reset during channel change. */HAL_BOOLar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,	struct ieee80211_channel *chan,	HAL_BOOL bChannelChange,	HAL_RESET_TYPE resetType,	HAL_STATUS *status){#define	N(a)	(sizeof (a) / sizeof (a[0]))#define	FAIL(_code)	do { ecode = _code; goto bad; } while (0)	struct ath_hal_5212 *ahp = AH5212(ah);	HAL_CHANNEL_INTERNAL *ichan;	const HAL_EEPROM *ee;	uint32_t saveFrameSeqCount, saveDefAntenna;	uint32_t macStaId1, synthDelay, txFrm2TxDStart;	uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL];	int16_t cckOfdmPwrDelta = 0;	u_int modesIndex, freqIndex;	HAL_STATUS ecode;	int i, regWrites = 0;	uint32_t testReg;	uint32_t saveLedState = 0;	HALASSERT(ah->ah_magic == AR5212_MAGIC);	ee = AH_PRIVATE(ah)->ah_eeprom;	OS_MARK(ah, AH_MARK_RESET, bChannelChange);	/*	 * Map public channel to private.	 */	ichan = ath_hal_checkchannel(ah, chan);	if (ichan == AH_NULL) {		HALDEBUG(ah, HAL_DEBUG_ANY,		    "%s: invalid channel %u/0x%x; no mapping/n",		    __func__, chan->ic_freq, chan->ic_flags);		FAIL(HAL_EINVAL);	}	switch (opmode) {	case HAL_M_STA:	case HAL_M_IBSS:	case HAL_M_HOSTAP:	case HAL_M_MONITOR:		break;	default:		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u/n",		    __func__, opmode);		FAIL(HAL_EINVAL);		break;	}	HALASSERT(ahp->ah_eeversion >= AR_EEPROM_VER3);	/* Preserve certain DMA hardware registers on a channel change */	if (bChannelChange) {		/*		 * On Venice, the TSF is almost preserved across a reset;		 * it requires the doubling writes to the RESET_TSF		 * bit in the AR_BEACON register; it also has the quirk		 * of the TSF going back in time on the station (station		 * latches onto the last beacon's tsf during a reset 50%		 * of the times); the latter is not a problem for adhoc		 * stations since as long as the TSF is behind, it will		 * get resynchronized on receiving the next beacon; the		 * TSF going backwards in time could be a problem for the		 * sleep operation (supported on infrastructure stations		 * only) - the best and most general fix for this situation		 * is to resynchronize the various sleep/beacon timers on		 * the receipt of the next beacon i.e. when the TSF itself		 * gets resynchronized to the AP's TSF - power save is		 * needed to be temporarily disabled until that time		 *		 * Need to save the sequence number to restore it after		 * the reset!		 */		saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);	} else		saveFrameSeqCount = 0;		/* NB: silence compiler */	/* If the channel change is across the same mode - perform a fast channel change */	if ((IS_2413(ah) || IS_5413(ah))) {		/*		 * Channel change can only be used when:		 *  -channel change requested - so it's not the initial reset.		 *  -it's not a change to the current channel - often called when switching modes		 *   on a channel		 *  -the modes of the previous and requested channel are the same - some ugly code for XR		 */		if (bChannelChange &&		    AH_PRIVATE(ah)->ah_curchan != AH_NULL &&		    (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) &&		    ((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) ==		     (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) {			if (ar5212ChannelChange(ah, chan))				/* If ChannelChange completed - skip the rest of reset *///.........这里部分代码省略.........

/* * Reads EEPROM header info from device structure and programs * all rf registers * * REQUIRES: Access to the analog rf device */static HAL_BOOLar2316SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain){#define	RF_BANK_SETUP(_priv, _ix, _col) do {				    /	int i;								    /	for (i = 0; i < N(ar5212Bank##_ix##_2316); i++)			    /		(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2316[i][_col];/} while (0)	struct ath_hal_5212 *ahp = AH5212(ah);	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;	uint16_t ob2GHz = 0, db2GHz = 0;	struct ar2316State *priv = AR2316(ah);	int regWrites = 0;	HALDEBUG(ah, HAL_DEBUG_RFPARAM,	    "%s: chan 0x%x flag 0x%x modesIndex 0x%x/n",	    __func__, chan->channel, chan->channelFlags, modesIndex);	HALASSERT(priv != AH_NULL);	/* Setup rf parameters */	switch (chan->channelFlags & CHANNEL_ALL) {	case CHANNEL_B:		ob2GHz = ee->ee_obFor24;		db2GHz = ee->ee_dbFor24;		break;	case CHANNEL_G:	case CHANNEL_108G:		ob2GHz = ee->ee_obFor24g;		db2GHz = ee->ee_dbFor24g;		break;	default:		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x/n",		    __func__, chan->channelFlags);		return AH_FALSE;	}	/* Bank 1 Write */	RF_BANK_SETUP(priv, 1, 1);	/* Bank 2 Write */	RF_BANK_SETUP(priv, 2, modesIndex);	/* Bank 3 Write */	RF_BANK_SETUP(priv, 3, modesIndex);	/* Bank 6 Write */	RF_BANK_SETUP(priv, 6, modesIndex);	ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz,   3, 178, 0);	ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz,   3, 175, 0);	/* Bank 7 Setup */	RF_BANK_SETUP(priv, 7, modesIndex);	/* Write Analog registers */	HAL_INI_WRITE_BANK(ah, ar5212Bank1_2316, priv->Bank1Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank2_2316, priv->Bank2Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank3_2316, priv->Bank3Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank6_2316, priv->Bank6Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank7_2316, priv->Bank7Data, regWrites);	/* Now that we have reprogrammed rfgain value, clear the flag. */	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;	return AH_TRUE;#undef	RF_BANK_SETUP}

/* * Attach for an AR9280 part. */static struct ath_hal *ar9280Attach(uint16_t devid, HAL_SOFTC sc,             HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status){    struct ath_hal_9280 *ahp9280;    struct ath_hal_5212 *ahp;    struct ath_hal *ah;    uint32_t val;    HAL_STATUS ecode;    HAL_BOOL rfStatus;    HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p/n",             __func__, sc, (void*) st, (void*) sh);    /* NB: memory is returned zero'd */    ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280));    if (ahp9280 == AH_NULL) {        HALDEBUG(AH_NULL, HAL_DEBUG_ANY,                 "%s: cannot allocate memory for state block/n", __func__);        *status = HAL_ENOMEM;        return AH_NULL;    }    ahp = AH5212(ahp9280);    ah = &ahp->ah_priv.h;    ar5416InitState(AH5416(ah), devid, sc, st, sh, status);    /* XXX override with 9280 specific state */    /* override 5416 methods for our needs */    ah->ah_setAntennaSwitch		= ar9280SetAntennaSwitch;    ah->ah_configPCIE		= ar9280ConfigPCIE;    AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;    AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;    AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;    AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;    AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;    AH5416(ah)->ah_spurMitigate	= ar9280SpurMitigate;    AH5416(ah)->ah_writeIni		= ar9280WriteIni;    AH5416(ah)->ah_rx_chainmask	= AR9280_DEFAULT_RXCHAINMASK;    AH5416(ah)->ah_tx_chainmask	= AR9280_DEFAULT_TXCHAINMASK;    if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {        /* reset chip */        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip/n",                 __func__);        ecode = HAL_EIO;        goto bad;    }    if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip/n",                 __func__);        ecode = HAL_EIO;        goto bad;    }    /* Read Revisions from Chips before taking out of reset */    val = OS_REG_READ(ah, AR_SREV);    HALDEBUG(ah, HAL_DEBUG_ATTACH,             "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x/n",             __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),             MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));    /* NB: include chip type to differentiate from pre-Sowl versions */    AH_PRIVATE(ah)->ah_macVersion =        (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;    AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);    AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;    /* setup common ini data; rf backends handle remainder */    if (AR_SREV_MERLIN_20_OR_LATER(ah)) {        HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);        HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);        HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,                     ar9280PciePhy_clkreq_always_on_L1_v2, 2);        HAL_INI_INIT(&ahp9280->ah_ini_xmodes,                     ar9280Modes_fast_clock_v2, 3);    } else {        HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6);        HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2);        HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,                     ar9280PciePhy_v1, 2);    }    ar5416AttachPCIE(ah);    ecode = ath_hal_v14EepromAttach(ah);    if (ecode != HAL_OK)        goto bad;    if (!ar5416ChipReset(ah, AH_NULL)) {	/* reset chip */        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed/n", __func__);        ecode = HAL_EIO;        goto bad;    }    AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);//.........这里部分代码省略.........

/* * Return the current ANI state of the channel we're on */struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *ah){	return AH5212(ah)->ah_curani;}

static voidar9287AniSetup(struct ath_hal *ah){	/*	 * These are the parameters from the AR5416 ANI code;	 * they likely need quite a bit of adjustment for the	 * AR9287.	 */        static const struct ar5212AniParams aniparams = {                .maxNoiseImmunityLevel  = 4,    /* levels 0..4 */                .totalSizeDesired       = { -55, -55, -55, -55, -62 },                .coarseHigh             = { -14, -14, -14, -14, -12 },                .coarseLow              = { -64, -64, -64, -64, -70 },                .firpwr                 = { -78, -78, -78, -78, -80 },                .maxSpurImmunityLevel   = 7,                .cycPwrThr1             = { 2, 4, 6, 8, 10, 12, 14, 16 },                .maxFirstepLevel        = 2,    /* levels 0..2 */                .firstep                = { 0, 4, 8 },                .ofdmTrigHigh           = 500,                .ofdmTrigLow            = 200,                .cckTrigHigh            = 200,                .cckTrigLow             = 100,                .rssiThrHigh            = 40,                .rssiThrLow             = 7,                .period                 = 100,        };	/* NB: disable ANI noise immmunity for reliable RIFS rx */	AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL;        /* NB: ANI is not enabled yet */        ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);}/* * Attach for an AR9287 part. */static struct ath_hal *ar9287Attach(uint16_t devid, HAL_SOFTC sc,	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,	HAL_STATUS *status){	struct ath_hal_9287 *ahp9287;	struct ath_hal_5212 *ahp;	struct ath_hal *ah;	uint32_t val;	HAL_STATUS ecode;	HAL_BOOL rfStatus;	int8_t pwr_table_offset;	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p/n",	    __func__, sc, (void*) st, (void*) sh);	/* NB: memory is returned zero'd */	ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287));	if (ahp9287 == AH_NULL) {		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,		    "%s: cannot allocate memory for state block/n", __func__);		*status = HAL_ENOMEM;		return AH_NULL;	}	ahp = AH5212(ahp9287);	ah = &ahp->ah_priv.h;	ar5416InitState(AH5416(ah), devid, sc, st, sh, status);	if (eepromdata != AH_NULL) {		AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;		AH_PRIVATE(ah)->ah_eepromWrite = NULL;		ah->ah_eepromdata = eepromdata;	}	/* XXX override with 9280 specific state */	/* override 5416 methods for our needs */	AH5416(ah)->ah_initPLL = ar9280InitPLL;	ah->ah_setAntennaSwitch		= ar9287SetAntennaSwitch;	ah->ah_configPCIE		= ar9287ConfigPCIE;	ah->ah_disablePCIE		= ar9287DisablePCIE;	AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal;	AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal;	AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal;	AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal;	/* Better performance without ADC Gain Calibration */	AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL;	AH5416(ah)->ah_spurMitigate	= ar9280SpurMitigate;	AH5416(ah)->ah_writeIni		= ar9287WriteIni;	ah->ah_setTxPower		= ar9287SetTransmitPower;	ah->ah_setBoardValues		= ar9287SetBoardValues;	AH5416(ah)->ah_olcInit		= ar9287olcInit;	AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation;	//AH5416(ah)->ah_setPowerCalTable	= ar9287SetPowerCalTable;	AH5416(ah)->ah_cal_initcal	= ar9287InitCalHardware;	AH5416(ah)->ah_cal_pacal	= ar9287PACal;	/* XXX NF calibration *///.........这里部分代码省略.........

static voidar5212AniOfdmErrTrigger(struct ath_hal *ah){	struct ath_hal_5212 *ahp = AH5212(ah);	const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;	struct ar5212AniState *aniState;	const struct ar5212AniParams *params;	HALASSERT(chan != AH_NULL);	if (!ANI_ENA(ah))		return;	aniState = ahp->ah_curani;	params = aniState->params;	/* First, raise noise immunity level, up to max */	if (aniState->noiseImmunityLevel+1 <= params->maxNoiseImmunityLevel) {		HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u/n", __func__,		    aniState->noiseImmunityLevel + 1);		ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 				 aniState->noiseImmunityLevel + 1);		return;	}	/* then, raise spur immunity level, up to max */	if (aniState->spurImmunityLevel+1 <= params->maxSpurImmunityLevel) {		HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise SI to %u/n", __func__,		    aniState->spurImmunityLevel + 1);		ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,				 aniState->spurImmunityLevel + 1);		return;	}	if (ANI_ENA_RSSI(ah)) {		int32_t rssi = BEACON_RSSI(ahp);		if (rssi > params->rssiThrHigh) {			/*			 * Beacon rssi is high, can turn off ofdm			 * weak sig detect.			 */			if (!aniState->ofdmWeakSigDetectOff) {				HALDEBUG(ah, HAL_DEBUG_ANI,				    "%s: rssi %d OWSD off/n", __func__, rssi);				ar5212AniControl(ah,				    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,				    AH_FALSE);				ar5212AniControl(ah,				    HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);				return;			}			/* 			 * If weak sig detect is already off, as last resort,			 * raise firstep level 			 */			if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {				HALDEBUG(ah, HAL_DEBUG_ANI,				    "%s: rssi %d raise ST %u/n", __func__, rssi,				    aniState->firstepLevel+1);				ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,						 aniState->firstepLevel + 1);				return;			}		} else if (rssi > params->rssiThrLow) {			/* 			 * Beacon rssi in mid range, need ofdm weak signal			 * detect, but we can raise firststepLevel.			 */			if (aniState->ofdmWeakSigDetectOff) {				HALDEBUG(ah, HAL_DEBUG_ANI,				    "%s: rssi %d OWSD on/n", __func__, rssi);				ar5212AniControl(ah,				    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,				    AH_TRUE);			}			if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {				HALDEBUG(ah, HAL_DEBUG_ANI,				    "%s: rssi %d raise ST %u/n", __func__, rssi,				    aniState->firstepLevel+1);				ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,				     aniState->firstepLevel + 1);			}			return;		} else {			/* 			 * Beacon rssi is low, if in 11b/g mode, turn off ofdm			 * weak signal detection and zero firstepLevel to			 * maximize CCK sensitivity 			 */			if (IEEE80211_IS_CHAN_CCK(chan)) {				if (!aniState->ofdmWeakSigDetectOff) {					HALDEBUG(ah, HAL_DEBUG_ANI,					    "%s: rssi %d OWSD off/n",					    __func__, rssi);					ar5212AniControl(ah,					    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,					    AH_FALSE);				}				if (aniState->firstepLevel > 0) {					HALDEBUG(ah, HAL_DEBUG_ANI,					    "%s: rssi %d zero ST (was %u)/n",					    __func__, rssi,//.........这里部分代码省略.........

/* * Reads EEPROM header info from device structure and programs * all rf registers * * REQUIRES: Access to the analog rf device */static HAL_BOOLar2413SetRfRegs(struct ath_hal *ah,	const struct ieee80211_channel *chan,	uint16_t modesIndex, uint16_t *rfXpdGain){#define	RF_BANK_SETUP(_priv, _ix, _col) do {				    /	int i;								    /	for (i = 0; i < N(ar5212Bank##_ix##_2413); i++)			    /		(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2413[i][_col];/} while (0)	struct ath_hal_5212 *ahp = AH5212(ah);	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;	uint16_t ob2GHz = 0, db2GHz = 0;	struct ar2413State *priv = AR2413(ah);	int regWrites = 0;	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u/n",	    __func__, chan->ic_freq, chan->ic_flags, modesIndex);	HALASSERT(priv);	/* Setup rf parameters */	if (IEEE80211_IS_CHAN_B(chan)) {		ob2GHz = ee->ee_obFor24;		db2GHz = ee->ee_dbFor24;	} else {		ob2GHz = ee->ee_obFor24g;		db2GHz = ee->ee_dbFor24g;	}	/* Bank 1 Write */	RF_BANK_SETUP(priv, 1, 1);	/* Bank 2 Write */	RF_BANK_SETUP(priv, 2, modesIndex);	/* Bank 3 Write */	RF_BANK_SETUP(priv, 3, modesIndex);	/* Bank 6 Write */	RF_BANK_SETUP(priv, 6, modesIndex);	ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz,   3, 168, 0);	ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz,   3, 165, 0);	/* Bank 7 Setup */	RF_BANK_SETUP(priv, 7, modesIndex);	/* Write Analog registers */	HAL_INI_WRITE_BANK(ah, ar5212Bank1_2413, priv->Bank1Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank2_2413, priv->Bank2Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank3_2413, priv->Bank3Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank6_2413, priv->Bank6Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank7_2413, priv->Bank7Data, regWrites);	/* Now that we have reprogrammed rfgain value, clear the flag. */	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;	return AH_TRUE;#undef	RF_BANK_SETUP}

/* * Process a MIB interrupt.  We may potentially be invoked because * any of the MIB counters overflow/trigger so don't assume we're * here because a PHY error counter triggered. */voidar5212ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats){	struct ath_hal_5212 *ahp = AH5212(ah);	uint32_t phyCnt1, phyCnt2;	HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "	    "filtofdm 0x%x filtcck 0x%x/n",	    __func__, OS_REG_READ(ah, AR_MIBC),	    OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),	    OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));	/*	 * First order of business is to clear whatever caused	 * the interrupt so we don't keep getting interrupted.	 * We have the usual mib counters that are reset-on-read	 * and the additional counters that appeared starting in	 * Hainan.  We collect the mib counters and explicitly	 * zero additional counters we are not using.  Anything	 * else is reset only if it caused the interrupt.	 */	/* NB: these are not reset-on-read */	phyCnt1 = OS_REG_READ(ah, AR_PHYCNT1);	phyCnt2 = OS_REG_READ(ah, AR_PHYCNT2);	/* not used, always reset them in case they are the cause */	OS_REG_WRITE(ah, AR_FILTOFDM, 0);	OS_REG_WRITE(ah, AR_FILTCCK, 0);	/* Clear the mib counters and save them in the stats */	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);	ahp->ah_stats.ast_nodestats = *stats;	/*	 * Check for an ani stat hitting the trigger threshold.	 * When this happens we get a MIB interrupt and the top	 * 2 bits of the counter register will be 0b11, hence	 * the mask check of phyCnt?.	 */	if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || 	    ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {		struct ar5212AniState *aniState = ahp->ah_curani;		const struct ar5212AniParams *params = aniState->params;		uint32_t ofdmPhyErrCnt, cckPhyErrCnt;		ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;		ahp->ah_stats.ast_ani_ofdmerrs +=			ofdmPhyErrCnt - aniState->ofdmPhyErrCount;		aniState->ofdmPhyErrCount = ofdmPhyErrCnt;		cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;		ahp->ah_stats.ast_ani_cckerrs +=			cckPhyErrCnt - aniState->cckPhyErrCount;		aniState->cckPhyErrCount = cckPhyErrCnt;		/*		 * NB: figure out which counter triggered.  If both		 * trigger we'll only deal with one as the processing		 * clobbers the error counter so the trigger threshold		 * check will never be true.		 */		if (aniState->ofdmPhyErrCount > params->ofdmTrigHigh)			ar5212AniOfdmErrTrigger(ah);		if (aniState->cckPhyErrCount > params->cckTrigHigh)			ar5212AniCckErrTrigger(ah);		/* NB: always restart to insure the h/w counters are reset */		ar5212AniRestart(ah, aniState);	}}

/*  * Return an approximation of the time spent ``listening'' by * deducting the cycles spent tx'ing and rx'ing from the total * cycle count since our last call.  A return value <0 indicates * an invalid/inconsistent time. */static int32_tar5212AniGetListenTime(struct ath_hal *ah){	struct ath_hal_5212 *ahp = AH5212(ah);	struct ar5212AniState *aniState = NULL;	int32_t listenTime = 0;	int good;	HAL_SURVEY_SAMPLE hs;	HAL_CHANNEL_SURVEY *cs = AH_NULL;	/*	 * We shouldn't see ah_curchan be NULL, but just in case..	 */	if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) {		ath_hal_printf(ah, "%s: ah_curchan = NULL?/n", __func__);		return (0);	}	cs = &ahp->ah_chansurvey;	/*	 * Fetch the current statistics, squirrel away the current	 * sample, bump the sequence/sample counter.	 */	OS_MEMZERO(&hs, sizeof(hs));	good = ar5212GetMibCycleCounts(ah, &hs);	if (cs != AH_NULL) {		OS_MEMCPY(&cs->samples[cs->cur_sample], &hs, sizeof(hs));		cs->samples[cs->cur_sample].seq_num = cs->cur_seq;		cs->cur_sample =		    (cs->cur_sample + 1) % CHANNEL_SURVEY_SAMPLE_COUNT;		cs->cur_seq++;	}	if (ANI_ENA(ah))		aniState = ahp->ah_curani;	if (good == AH_FALSE) {		/*		 * Cycle counter wrap (or initial call); it's not possible		 * to accurately calculate a value because the registers		 * right shift rather than wrap--so punt and return 0.		 */		listenTime = 0;		ahp->ah_stats.ast_ani_lzero++;	} else if (ANI_ENA(ah)) {		/*		 * Only calculate and update the cycle count if we have		 * an ANI state.		 */		int32_t ccdelta =		    AH5212(ah)->ah_cycleCount - aniState->cycleCount;		int32_t rfdelta =		    AH5212(ah)->ah_rxBusy - aniState->rxFrameCount;		int32_t tfdelta =		    AH5212(ah)->ah_txBusy - aniState->txFrameCount;		listenTime = (ccdelta - rfdelta - tfdelta) / CLOCK_RATE;	}	/*	 * Again, only update ANI state if we have it.	 */	if (ANI_ENA(ah)) {		aniState->cycleCount = AH5212(ah)->ah_cycleCount;		aniState->rxFrameCount = AH5212(ah)->ah_rxBusy;		aniState->txFrameCount = AH5212(ah)->ah_txBusy;	}	return listenTime;}