自学教程：C++ APIC_COMMON函数代码示例

void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,                                   TPRAccess access){    APICCommonState *s = APIC_COMMON(dev);    vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);}

void apic_init_reset(DeviceState *dev){    APICCommonState *s = APIC_COMMON(dev);    int i;    if (!s) {        return;    }    s->tpr = 0;    s->spurious_vec = 0xff;    s->log_dest = 0;    s->dest_mode = 0xf;    memset(s->isr, 0, sizeof(s->isr));    memset(s->tmr, 0, sizeof(s->tmr));    memset(s->irr, 0, sizeof(s->irr));    for (i = 0; i < APIC_LVT_NB; i++) {        s->lvt[i] = APIC_LVT_MASKED;    }    s->esr = 0;    memset(s->icr, 0, sizeof(s->icr));    s->divide_conf = 0;    s->count_shift = 0;    s->initial_count = 0;    s->initial_count_load_time = 0;    s->next_time = 0;    s->wait_for_sipi = !cpu_is_bsp(s->cpu);    if (s->timer) {        timer_del(s->timer);    }    s->timer_expiry = -1;}

static void apic_common_realize(struct uc_struct *uc, DeviceState *dev, Error **errp){    APICCommonState *s = APIC_COMMON(uc, dev);    APICCommonClass *info;    if (uc->apic_no >= MAX_APICS) {        error_setg(errp, "%s initialization failed.",                   object_get_typename(OBJECT(dev)));        return;    }    s->idx = uc->apic_no++;    info = APIC_COMMON_GET_CLASS(uc, s);    info->realize(uc, dev, errp);    if (!uc->mmio_registered) {        ICCBus *b = ICC_BUS(uc, qdev_get_parent_bus(dev));        memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory);        uc->mmio_registered = true;    }    /* Note: We need at least 1M to map the VAPIC option ROM */    if (!uc->vapic && s->vapic_control & VAPIC_ENABLE_MASK) {        // ram_size >= 1024 * 1024) {	// FIXME        uc->vapic = NULL;    }    s->vapic = uc->vapic;    if (uc->apic_report_tpr_access && info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, true);    }}

static void apic_common_realize(DeviceState *dev, Error **errp){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info;    static DeviceState *vapic;    int instance_id = s->id;    info = APIC_COMMON_GET_CLASS(s);    info->realize(dev, errp);    /* Note: We need at least 1M to map the VAPIC option ROM */    if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&        ram_size >= 1024 * 1024) {        vapic = sysbus_create_simple("kvmvapic", -1, NULL);    }    s->vapic = vapic;    if (apic_report_tpr_access && info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, true);    }    if (s->legacy_instance_id) {        instance_id = -1;    }    vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,                                   s, -1, 0);}

static void apic_common_realize(DeviceState *dev, Error **errp){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info;    static DeviceState *vapic;    static int apic_no;    static bool mmio_registered;    if (apic_no >= MAX_APICS) {        error_setg(errp, "%s initialization failed.",                   object_get_typename(OBJECT(dev)));        return;    }    s->idx = apic_no++;    info = APIC_COMMON_GET_CLASS(s);    info->realize(dev, errp);    if (!mmio_registered) {        ICCBus *b = ICC_BUS(qdev_get_parent_bus(dev));        memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory);        mmio_registered = true;    }    /* Note: We need at least 1M to map the VAPIC option ROM */    if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&        ram_size >= 1024 * 1024) {        vapic = sysbus_create_simple("kvmvapic", -1, NULL);    }    s->vapic = vapic;    if (apic_report_tpr_access && info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, true);    }}

static void apic_common_realize(DeviceState *dev, Error **errp){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info;    static DeviceState *vapic;    static int apic_no;    if (apic_no >= MAX_APICS) {        error_setg(errp, "%s initialization failed.",                   object_get_typename(OBJECT(dev)));        return;    }    s->idx = apic_no++;    info = APIC_COMMON_GET_CLASS(s);    info->realize(dev, errp);    /* Note: We need at least 1M to map the VAPIC option ROM */    if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&        ram_size >= 1024 * 1024) {        vapic = sysbus_create_simple("kvmvapic", -1, NULL);    }    s->vapic = vapic;    if (apic_report_tpr_access && info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, true);    }}

static int apic_init_common(SysBusDevice *dev){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info;    static DeviceState *vapic;    static int apic_no;    if (apic_no >= MAX_APICS) {        return -1;    }    s->idx = apic_no++;    info = APIC_COMMON_GET_CLASS(s);    info->init(s);    sysbus_init_mmio(dev, &s->io_memory);    /* Note: We need at least 1M to map the VAPIC option ROM */    if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&        ram_size >= 1024 * 1024) {        vapic = sysbus_create_simple("kvmvapic", -1, NULL);    }    s->vapic = vapic;    if (apic_report_tpr_access && info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, true);    }    return 0;}

void apic_deliver_nmi(DeviceState *dev){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);    info->external_nmi(s);}

void apic_enable_vapic(DeviceState *dev, hwaddr paddr){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);    s->vapic_paddr = paddr;    info->vapic_base_update(s);}

void cpu_set_apic_base(struct uc_struct *uc, DeviceState *dev, uint64_t val){    if (dev) {        APICCommonState *s = APIC_COMMON(uc, dev);        APICCommonClass *info = APIC_COMMON_GET_CLASS(uc, s);        info->set_base(s, val);    }}

static void apic_common_get_id(Object *obj, Visitor *v, const char *name,                               void *opaque, Error **errp){    APICCommonState *s = APIC_COMMON(obj);    uint32_t value;    value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;    visit_type_uint32(v, name, &value, errp);}

void apic_designate_bsp(DeviceState *d){    if (d == NULL) {        return;    }    APICCommonState *s = APIC_COMMON(d);    s->apicbase |= MSR_IA32_APICBASE_BSP;}

void apic_designate_bsp(struct uc_struct *uc, DeviceState *dev){    if (dev == NULL) {        return;    }    APICCommonState *s = APIC_COMMON(uc, dev);    s->apicbase |= MSR_IA32_APICBASE_BSP;}

uint64_t cpu_get_apic_base(struct uc_struct *uc, DeviceState *dev){    if (dev) {        APICCommonState *s = APIC_COMMON(uc, dev);        return s->apicbase;    } else {        return MSR_IA32_APICBASE_BSP;    }}

static void apic_dispatch_pre_save(void *opaque){    APICCommonState *s = APIC_COMMON(opaque);    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);    if (info->pre_save) {        info->pre_save(s);    }}

static void apic_common_initfn(Object *obj){    APICCommonState *s = APIC_COMMON(obj);    s->id = s->initial_apic_id = -1;    object_property_add(obj, "id", "uint32",                        apic_common_get_id,                        apic_common_set_id, NULL, NULL, NULL);}

static int apic_dispatch_post_load(void *opaque, int version_id){    APICCommonState *s = APIC_COMMON(opaque);    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);    if (info->post_load) {        info->post_load(s);    }    return 0;}

void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);    apic_report_tpr_access = enable;    if (info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, enable);    }}

void cpu_set_apic_base(DeviceState *dev, uint64_t val){    trace_cpu_set_apic_base(val);    if (dev) {        APICCommonState *s = APIC_COMMON(dev);        APICCommonClass *info = APIC_COMMON_GET_CLASS(s);        info->set_base(s, val);    }}

uint64_t cpu_get_apic_base(DeviceState *dev){    if (dev) {        APICCommonState *s = APIC_COMMON(dev);        trace_cpu_get_apic_base((uint64_t)s->apicbase);        return s->apicbase;    } else {        trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);        return MSR_IA32_APICBASE_BSP;    }}

static int apic_pre_load(void *opaque){    APICCommonState *s = APIC_COMMON(opaque);    /* The default is !cpu_is_bsp(s->cpu), but the common value is 0     * so that's what apic_common_sipi_needed checks for.  Reset to     * the value that is assumed when the apic_sipi subsection is     * absent.     */    s->wait_for_sipi = 0;    return 0;}

static void apic_common_unrealize(DeviceState *dev, Error **errp){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);    vmstate_unregister(NULL, &vmstate_apic_common, s);    info->unrealize(dev, errp);    if (apic_report_tpr_access && info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, false);    }}

void apic_designate_bsp(DeviceState *dev, bool bsp){    if (dev == NULL) {        return;    }    APICCommonState *s = APIC_COMMON(dev);    if (bsp) {        s->apicbase |= MSR_IA32_APICBASE_BSP;    } else {        s->apicbase &= ~MSR_IA32_APICBASE_BSP;    }}

uint8_t cpu_get_apic_tpr(DeviceState *dev){    APICCommonState *s;    APICCommonClass *info;    if (!dev) {        return 0;    }    s = APIC_COMMON(dev);    info = APIC_COMMON_GET_CLASS(s);    return info->get_tpr(s);}

void cpu_set_apic_tpr(DeviceState *dev, uint8_t val){    APICCommonState *s;    APICCommonClass *info;    if (!dev) {        return;    }    s = APIC_COMMON(dev);    info = APIC_COMMON_GET_CLASS(s);    info->set_tpr(s, val);}

static void apic_reset_common(DeviceState *dev){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info = APIC_COMMON_GET_CLASS(s);    uint32_t bsp;    bsp = s->apicbase & MSR_IA32_APICBASE_BSP;    s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;    s->vapic_paddr = 0;    info->vapic_base_update(s);    apic_init_reset(dev);}

void cpu_set_apic_base(DeviceState *dev, uint64_t val){    trace_cpu_set_apic_base(val);    if (dev) {        APICCommonState *s = APIC_COMMON(dev);        APICCommonClass *info = APIC_COMMON_GET_CLASS(s);        /* switching to x2APIC, reset possibly modified xAPIC ID */        if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) &&            (val & MSR_IA32_APICBASE_EXTD)) {            s->id = s->initial_apic_id;        }        info->set_base(s, val);    }}

static void apic_common_set_id(Object *obj, Visitor *v, const char *name,                               void *opaque, Error **errp){    APICCommonState *s = APIC_COMMON(obj);    DeviceState *dev = DEVICE(obj);    Error *local_err = NULL;    uint32_t value;    if (dev->realized) {        qdev_prop_set_after_realize(dev, name, errp);        return;    }    visit_type_uint32(v, name, &value, &local_err);    if (local_err) {        error_propagate(errp, local_err);        return;    }    s->initial_apic_id = value;    s->id = (uint8_t)value;}

static void apic_reset_common(struct uc_struct *uc, DeviceState *dev){    APICCommonState *s = APIC_COMMON(uc, dev);    APICCommonClass *info = APIC_COMMON_GET_CLASS(uc, s);    bool bsp;    bsp = cpu_is_bsp(s->cpu);    s->apicbase = APIC_DEFAULT_ADDRESS |        (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;    s->vapic_paddr = 0;    info->vapic_base_update(s);    apic_init_reset(uc, dev);    if (bsp) {        /*         * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization         * time typically by BIOS, so PIC interrupt can be delivered to the         * processor when local APIC is enabled.         */        s->lvt[APIC_LVT_LINT0] = 0x700;    }}

static bool apic_common_sipi_needed(void *opaque){    APICCommonState *s = APIC_COMMON(opaque);    return s->wait_for_sipi != 0;}