自学教程：C++ sr32函数代码示例

/***************************************** * Routine: board_init * Description: Early hardware init. *****************************************/int board_init(void){	unsigned int rev = omap_revision();	if (rev != OMAP4430_ES1_0) {		if (__raw_readl(0x4805D138) & (1<<22)) {			/* enable software ioreq */			sr32(0x4A30a31C, 8, 1, 0x1);			/* set for sys_clk (38.4MHz) */			sr32(0x4A30a31C, 1, 2, 0x0);			/* set divisor to 2 */			sr32(0x4A30a31C, 16, 4, 0x1);			/* set the clock source to active */			sr32(0x4A30a110, 0, 1, 0x1);			/* enable clocks */			sr32(0x4A30a110, 2, 2, 0x3);		} else {			/* enable software ioreq */			sr32(0x4A30a314, 8, 1, 0x1);			/* set for PER_DPLL */			sr32(0x4A30a314, 1, 2, 0x2);			/* set divisor to 16 */			sr32(0x4A30a314, 16, 4, 0xf);			/* set the clock source to active */			sr32(0x4A30a110, 0, 1, 0x1);			/* enable clocks */			sr32(0x4A30a110, 2, 2, 0x3);		}	}	return 0;}

static void iva_init_36xx(u32 sil_index, u32 clk_index){	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;	dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();	/* Moving to the right sysclk */	ptr += clk_index;	/* IVA DPLL */	/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */	sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);	wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */	sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);	/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */	sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);	/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */	sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);	/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */	sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);	wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);}

static inline void dram_set_mode(struct sunxi_dram_reg *dram) {	sr32(&dram->mr, 0, 3, MR_BURST_LENGTH);	sr32(&dram->mr, 12, 1, MR_POWER_DOWN);	sr32(&dram->mr, 4, 3, MR_CAS_LATENCY);	sr32(&dram->mr, 9, 3, MR_WRITE_RECOVERY);}

static void configure_iva_dpll(u32 clk_index){	struct dpll_param *dpll_param_p;	/* Unlock the IVA dpll */	sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY);	/* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */	sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1);	/* Program IVA DPLL */	dpll_param_p = &iva_dpll_param[clk_index];	sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */	/* Set M,N,M4,M5 */	sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n);	sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4);	sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1);	sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5);	sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1);	/* Lock the iva dpll */	sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY);}

/****************************************************************************** * Setting the Clock speed  * *****************************************************************************/void set_mpu_clk(int speed){	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;	/* Set M */	sr32(&prcm_base->clksel1_pll_mpu, 8, 11, speed);	/* lock mode */	sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);}

static void configure_usb_dpll(u32 clk_index){	dpll_param *dpll_param_p;	/* Select the 60Mhz clock 480/8 = 60*/	sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1);	/* Unlock the USB dpll */	sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY);	/* Program USB DPLL */	dpll_param_p = &usb_dpll_param[clk_index];	/* Disable autoidle */	sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0);	sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n);	/* Force DPLL CLKOUT to stay active */	sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100);	sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2);	/* Lock the usb dpll */	sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY);	/* force enable the CLKDCOLDO clock */	sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100);	return;}

void lcd_ctrl_init(void *lcdbase){   sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);   sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);       udelay(200);     omap3_dss_panel_config(&panel_info.dss_panel_config);   omap3_dss_mem_config(&panel_info.dss_panel_config, lcdbase);   lcd_set_base = lcdbase;}

void omap_temp_sensor_check(void){	u32 temp;	/* Set the counter to 1 ms */	sr32(CORE_BANDGAP_COUNTER, BGAP_COUNTER_START_BIT,			BGAP_COUNTER_NUM_BITS, BGAP_COUNTER_VALUE);	/* Enable continuous mode. */	sr32(CORE_BANDGAP_CTRL, BGAP_SINGLE_MODE_START_BIT,			BGAP_SINGLE_MODE_NUM_BITS, BGAP_CONTINUOUS_MODE);	/* Wait till the first conversion is done wait for at least 1ms */	spin_delay(20000);	/* Read the temperature adc_value */	temp = readl(CORE_TEMP_SENSOR);	temp = temp & BGAP_TEMP_SENSOR_DTEMP_MASK;	/* If the samples are untrimmed divide by 1.2 */	if (readl(STD_FUSE_OPP_BGAP) == 0)		temp = temp * 5 / 6;	/*	 * Compare with TSHUT high temperature. If high ask the	 * user to shut down and restart after sometime else	 * Disable continuous mode.	 */	if (temp < TSHUT_HIGH_ADC_CODE) {		/* Disable contiuous mode */		sr32(CORE_BANDGAP_CTRL, BGAP_SINGLE_MODE_START_BIT,			BGAP_SINGLE_MODE_NUM_BITS, ~BGAP_CONTINUOUS_MODE);	} else {		printf("OMAP chip temperature is too high!!!/n");		printf("Please power off and try booting after sometime/n");		/* Bypass MPU, CORE, IVA, PER, ABE, USB DPLLs */		sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_FAST_RELOCK_BYPASS);		wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY);		sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_FAST_RELOCK_BYPASS);		wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);		sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_FAST_RELOCK_BYPASS);		wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY);		sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_FAST_RELOCK_BYPASS);		wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY);		sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_FAST_RELOCK_BYPASS);		wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);		sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_FAST_RELOCK_BYPASS);		wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY);		while (1);	}}

/* * ===  FUNCTION  ====================================================================== *         Name:  cat3648_init *  Description:  initialize GPIO pin which cat3648 use as input * ===================================================================================== */static void cat3648_init(void){    gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;    /*enable GPIO bank 5*/    sr32(CM_ICLKEN_PER,CLKEN_PER_EN_GPIO5_BIT, 1, 1);    sr32(CM_FCLKEN_PER,CLKEN_PER_EN_GPIO5_BIT, 1, 1);    /*set GPIO155 direction output*/    /*set GPIO155 low level,LCD BL shutdown */    set_gpio_dataout(155,0);    udelay(2000);    DEBUG_BL("cat3648 initialized/n");}

/* Reset is needed otherwise the kernel-driver will throw an error. */int ehci_hcd_stop(void){	pr_debug("Resetting OMAP3 EHCI/n");	gpio_set_value(GPIO_PHY_RESET, 0);	writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);	/* disable USB clocks */	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;	sr32(&prcm_base->iclken_usbhost, 0, 1, 0);	sr32(&prcm_base->fclken_usbhost, 0, 2, 0);	sr32(&prcm_base->iclken3_core, 2, 1, 0);	sr32(&prcm_base->fclken3_core, 2, 1, 0);	return 0;}

static void mpu_dpll_init_36XX(int clk_index, int sil_index){	dpll_param *mpu;	mpu = _get_mpu_dpll(clk_index, sil_index);	/* MPU DPLL (unlocked already) */	sr32(CM_CLKSEL1_PLL_MPU, 8, 11, mpu->m);	sr32(CM_CLKSEL1_PLL_MPU, 0,  7, mpu->n);	sr32(CM_CLKSEL2_PLL_MPU, 0,  5, mpu->m2);	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */	wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);}

static inline void dram_ddr_reset(struct sunxi_dram_reg *dram) {	/* different cpu revision in bit [7:6] */	if(readl(SUNXI_CPU_CFG)) {		sr32(&dram->mcr, 12, 1, SDRAM_RST_PIN_HIGH);		sdelay(0x100);		sr32(&dram->mcr, 12, 1, SDRAM_RST_PIN_LOW);	} else {		sr32(&dram->mcr, 12, 1, SDRAM_RST_PIN_LOW);		sdelay(0x100);		sr32(&dram->mcr, 12, 1, SDRAM_RST_PIN_HIGH);	}}

/* * Enable usb ehci uhh, tll clocks */void ehci_clocks_enable(void){	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;	/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */	sr32(&prcm_base->iclken_usbhost, 0, 1, 1);	/*	 * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)	 * and USBHOST_120M_FCLK (USBHOST_FCLK2)	 */	sr32(&prcm_base->fclken_usbhost, 0, 2, 3);	/* Enable USBTTL_ICLK */	sr32(&prcm_base->iclken3_core, 2, 1, 1);	/* Enable USBTTL_FCLK */	sr32(&prcm_base->fclken3_core, 2, 1, 1);}

void watchdog_reset(void){	static struct sunxi_wdog *wdog =		&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;	sr32(&wdog->ctl, 0, 1, WDT_CTRL_RESTART);}

void disable_backlight(void){    DECLARE_GLOBAL_DATA_PTR;    u32 l;    l = read_gpt8_reg(TCLR);    l &= ~GPT8_PWM_EN;    write_gpt8_reg(TLDR, 0x0);    write_gpt8_reg(TTGR, 0x0);    write_gpt8_reg(TMAR, 0x0);    sr32(CM_FCLKEN_PER, 9, 1, 0x0); /* FCLKEN GPT8 */    sr32(CM_ICLKEN_PER, 9, 1, 0x0); /* ICLKEN GPT8 */    gpio_pin_write( GPIO_BACKLIGHT_EN_EVT2, 1 );}

static void mpu_dpll_init_34XX(int clk_index, int sil_index){	dpll_param *dpll_param_p;	/* Getting the base address to MPU DPLL param table*/	dpll_param_p = (dpll_param *)get_mpu_dpll_param();	/* Moving it to the right sysclk and ES rev base */	dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;	/* MPU DPLL (unlocked already) */	sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2);	/* Set M2 */	sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m);	/* Set M */	sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n);	/* Set N */	sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel);	/* FREQSEL */	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */	wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);}

/****************************************************************************** * Routine: watchdog_init * Description: Shut down watch dogs *****************************************************************************/void watchdog_init(void){	/* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is	 * either taken care of by ROM (HS/EMU) or not accessible (GP).	 * We need to take care of WD2-MPU or take a PRCM reset. WD3	 * should not be running and does not generate a PRCM reset.	 */	sr32(CM_FCLKEN_WKUP, 5, 1, 1);	sr32(CM_ICLKEN_WKUP, 5, 1, 1);	wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5);	/* some issue here */	__raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);	wait_for_command_complete(WD2_BASE);	__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);}

static void noinline pcm049_init_lowlevel(void){	struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;	struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;	struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;	struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;	struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2;	unsigned int rev = omap4_revision();	set_muxconf_regs();#ifdef CONFIG_1024MB_DDR2RAM		omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core);#else		omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);#endif	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */	if (rev < OMAP4460_ES1_0)		omap4430_scale_vcores();	else		omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320);	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);	/* Configure all DPLL's at 100% OPP */	if (rev < OMAP4460_ES1_0)		omap4_configure_mpu_dpll(&mpu44xx);	else		omap4_configure_mpu_dpll(&mpu4460);	omap4_configure_iva_dpll(&iva);	omap4_configure_per_dpll(&per);	omap4_configure_abe_dpll(&abe);	omap4_configure_usb_dpll(&usb);	/* Enable all clocks */	omap4_enable_all_clocks();	sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);  /* enable software ioreq */	sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);  /* set for sys_clk (19.2MHz) */	sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x0); /* set divisor to 1 */	sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);  /* activate clock source */	sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);  /* enable clocks */}

void lock_core_dpll(void){	/* Lock the core dpll */	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);	return;}

void lcd_disable(void){    disable_backlight();    sr32(CM_FCLKEN_DSS, 0, 32, 0x0);	sr32(CM_ICLKEN_DSS, 0, 32, 0x0);     gpio_pin_write(36, 0);    // Restore SPI registers    MUX_VAL(CP(McBSP1_CLKR),    (IEN  | PTD | DIS | M1)) /*McSPI4-CLK*/ /    MUX_VAL(CP(McBSP1_DX),      (IDIS | PTD | DIS | M1)) /*McSPI4-SIMO*/ /    MUX_VAL(CP(McBSP1_DR),      (IEN  | PTD | DIS | M1)) /*McSPI4-SOMI*//    MUX_VAL(CP(McBSP1_FSX),     (IDIS | PTD | DIS | M1)) /*McSPI4-CS0*/    lcd_disabled = 1;}

static void dpll5_init_36xx(u32 sil_index, u32 clk_index){	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;	dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();	/* Moving it to the right sysclk base */	ptr = ptr + clk_index;	/* PER2 DPLL (DPLL5) */	sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);	wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);	sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */	sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */	sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/	sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK);   /* lock mode */	wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);}

static void configure_mpu_dpll(u32 clk_index){	dpll_param *dpll_param_p;	/* Unlock the MPU dpll */	sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY);	/* Program MPU DPLL */	dpll_param_p = &mpu_dpll_param[clk_index];	sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */	/* Set M,N,M2 values */	sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n);	sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2);	sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1);	/* Lock the mpu dpll */	sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY);	return;}

static void mpu_init_36xx(u32 sil_index, u32 clk_index){	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;	dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();	/* Moving to the right sysclk */	ptr += clk_index;	/* MPU DPLL (unlocked already */	/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */	sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);	/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */	sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);	/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */	sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);}

 void enable_backlight(void) {    DECLARE_GLOBAL_DATA_PTR;    u32 l;         sr32(CM_CLKSEL_PER, 6, 1, 0x0); /* CLKSEL = 32Khz */    sr32(CM_FCLKEN_PER, 9, 1, 0x1); /* FCLKEN GPT8 */    sr32(CM_ICLKEN_PER, 9, 1, 0x1); /* ICLKEN GPT8 */       udelay(200);    /*start with a random brightness which consumes less than 500mA such that we will gain      current into battery even when display is showing UI image*/    lcd_adjust_brightness(40);        	gpio_pin_init(GPIO_BACKLIGHT_EN_EVT2, GPIO_OUTPUT, 0);  }

static void dpll4_init_36xx(u32 sil_index, u32 clk_index){	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;	struct dpll_per_36x_param *ptr;	ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();	/* Moving it to the right sysclk base */	ptr += clk_index;	/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */	sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);	wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);	/* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */	sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);	/* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */	sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);	/* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */	sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);	/* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */	sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */	sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);	/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */	sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);	/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */	sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);	/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */	sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);	/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */	sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);}

static noinline void pcaaxl2_init_lowlevel(void){	struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;	struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;	struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;	struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;	struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2;	unsigned int rev = omap4_revision();	set_muxconf_regs();	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);	if (rev < OMAP4460_ES1_0)		omap4430_scale_vcores();	else		omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320);	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);	/* Configure all DPLL's at 100% OPP */	if (rev < OMAP4460_ES1_0)		omap4_configure_mpu_dpll(&mpu44xx);	else		omap4_configure_mpu_dpll(&mpu4460);	omap4_configure_iva_dpll(&iva);	omap4_configure_per_dpll(&per);	omap4_configure_abe_dpll(&abe);	omap4_configure_usb_dpll(&usb);	/* Enable all clocks */	omap4_enable_all_clocks();	sr32(0x4A30a31C, 8, 1, 0x1);  /* enable software ioreq */	sr32(0x4A30a31C, 1, 2, 0x0);  /* set for sys_clk (19.2MHz) */	sr32(0x4A30a31C, 16, 4, 0x0); /* set divisor to 1 */	sr32(0x4A30a110, 0, 1, 0x1);  /* set the clock source to active */	sr32(0x4A30a110, 2, 2, 0x3);  /* enable clocks */}

/****************************************************************************** * Routine: watchdog_init * Description: Shut down watch dogs *****************************************************************************/void watchdog_init(void){	watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;	/*	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is	 * either taken care of by ROM (HS/EMU) or not accessible (GP).	 * We need to take care of WD2-MPU or take a PRCM reset. WD3	 * should not be running and does not generate a PRCM reset.	 */	sr32(&prcm_base->fclken_wkup, 5, 1, 1);	sr32(&prcm_base->iclken_wkup, 5, 1, 1);	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);	writel(WD_UNLOCK1, &wd2_base->wspr);	wait_for_command_complete(wd2_base);	writel(WD_UNLOCK2, &wd2_base->wspr);}

static inline void dram_set_high_speed(struct sunxi_dram_reg *dram) {	sr32(&dram->mcr, 13, 2, MCR_ENABLE_MODE);	sr32(&dram->mcr, 0, 2, MCR_MODE_NORMAL);	sr32(&dram->mcr, 2, 2, MCR_DQ_OUT_MODE_HS);	sr32(&dram->mcr, 4, 2, MCR_ADDR_OUT_MODE_HS);	sr32(&dram->mcr, 6, 2, MCR_DQ_IN_MODE_HS);	sr32(&dram->mcr, 8, 3, MCR_DQ_HS_TURNON_DLY);	sr32(&dram->mcr, 11, 1, MCR_ADDR_IN_MODE_HS);}