自学教程：C++ strmhz函数代码示例

/* * Check board identity.  Always successful (gives information only) */int checkboard (void){	DECLARE_GLOBAL_DATA_PTR;	char *s;	char buf[64];	int i;	i = getenv_r ("board_id", buf, sizeof (buf));	s = (i > 0) ? buf : NULL;	if (s) {		printf ("%s ", s);	} else {		printf ("<unknown> ");	}	i = getenv_r ("serial#", buf, sizeof (buf));	s = (i > 0) ? buf : NULL;	if (s) {		printf ("S/N %s/n", s);	} else {		printf ("S/N <unknown>/n");	}	printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));	printf ("local bus at %s MHz/n", strmhz (buf, gd->bus_clk));	return (0);}

phys_size_t fixed_sdram(void){	int i;	char buf[32];	fsl_ddr_cfg_regs_t ddr_cfg_regs;	phys_size_t ddr_size;	ulong ddr_freq, ddr_freq_mhz;	ddr_freq = get_ddr_freq(0);	ddr_freq_mhz = ddr_freq / 1000000;	printf("Configuring DDR for %s MT/s data rate/n",	       strmhz(buf, ddr_freq));	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&		    (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {			memcpy(&ddr_cfg_regs,			       fixed_ddr_parm_0[i].ddr_settings,			       sizeof(ddr_cfg_regs));			break;		}	}	if (fixed_ddr_parm_0[i].max_freq == 0)		panic("Unsupported DDR data rate %s MT/s data rate/n",		      strmhz(buf, ddr_freq));	ddr_size = (phys_size_t)2048 * 1024 * 1024;	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);	return ddr_size;}

/* * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to * determine which one we are running on, based on the Chip Identification * Register (CIR). */int print_cpuinfo(void){	char buf[32];	unsigned short cir;	/* Chip Identification Register */	unsigned short pin;	/* Part identification number */	unsigned char prn;	/* Part revision number */	char *cpu_model;	cir = mbar_readShort(MCF_CCM_CIR);	pin = cir >> MCF_CCM_CIR_PIN_LEN;	prn = cir & MCF_CCM_CIR_PRN_MASK;	switch (pin) {	case MCF_CCM_CIR_PIN_MCF5270:		cpu_model = "5270";		break;	case MCF_CCM_CIR_PIN_MCF5271:		cpu_model = "5271";		break;	default:		cpu_model = NULL;		break;	}	if (cpu_model)		printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz/n",		       cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));	else		printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"		       " (PIN: 0x%x) rev. %hu, at %s MHz/n",		       pin, prn, strmhz(buf, CONFIG_SYS_CLK));	return 0;}

int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){	bd_t *bd = gd->bd;	char buf[32];	printf("U-Boot      = %s/n", bd->bi_r_version);	printf("CPU         = %s/n", bd->bi_cpu);	printf("Board       = %s/n", bd->bi_board_name);	print_str("VCO",         strmhz(buf, bd->bi_vco));	print_str("CCLK",        strmhz(buf, bd->bi_cclk));	print_str("SCLK",        strmhz(buf, bd->bi_sclk));	print_num("boot_params", (ulong)bd->bi_boot_params);	print_num("memstart",    (ulong)bd->bi_memstart);	print_lnum("memsize",    (u64)bd->bi_memsize);	print_num("flashstart",  (ulong)bd->bi_flashstart);	print_num("flashsize",   (ulong)bd->bi_flashsize);	print_num("flashoffset", (ulong)bd->bi_flashoffset);	print_eth(0);	printf("ip_addr     = %pI4/n", &bd->bi_ip_addr);	printf("baudrate    = %d bps/n", bd->bi_baudrate);	return 0;}

int checkboard (void){	sys_info_t sysinfo;	char buf[32];	get_sys_info (&sysinfo);#ifdef CONFIG_SBC8560	printf ("Board: Wind River SBC8560 Board/n");#else	printf ("Board: Wind River SBC8540 Board/n");#endif	printf ("/tCPU: %s MHz/n", strmhz(buf, sysinfo.freqProcessor[0]));	printf ("/tCCB: %s MHz/n", strmhz(buf, sysinfo.freqSystemBus));	printf ("/tDDR: %s MHz/n", strmhz(buf, sysinfo.freqSystemBus/2));	if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 /		|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {		printf ("/tLBC: %s MHz/n",			strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));	} else {		printf("/tLBC: unknown/n");	}	printf("/tCPM: %s MHz/n", strmhz(buf, sysinfo.freqSystemBus));	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled./n");	return (0);}

int checkcpu(void){	siu_t *siu = (siu_t *) MMAP_SIU;	u16 id = 0;	puts("CPU:   ");	switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {	case 0x0C:		id = 5485;		break;	case 0x0D:		id = 5484;		break;	case 0x0E:		id = 5483;		break;	case 0x0F:		id = 5482;		break;	case 0x10:		id = 5481;		break;	case 0x11:		id = 5480;		break;	case 0x12:		id = 5475;		break;	case 0x13:		id = 5474;		break;	case 0x14:		id = 5473;		break;	case 0x15:		id = 5472;		break;	case 0x16:		id = 5471;		break;	case 0x17:		id = 5470;		break;	}	if (id) {		char buf1[32], buf2[32];		printf("Freescale MCF%d/n", id);		printf("       CPU CLK %s MHz BUS CLK %s MHz/n",		       strmhz(buf1, gd->cpu_clk),		       strmhz(buf2, gd->bus_clk));	}	return 0;};

phys_size_t fixed_sdram(void){    int i;    char buf[32];    fsl_ddr_cfg_regs_t ddr_cfg_regs;    phys_size_t ddr_size;    unsigned int lawbar1_target_id;    ulong ddr_freq, ddr_freq_mhz;    ddr_freq = get_ddr_freq(0);    ddr_freq_mhz = ddr_freq / 1000000;    printf("Configuring DDR for %s MT/s data rate/n",           strmhz(buf, ddr_freq));    for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {        if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&                (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {            memcpy(&ddr_cfg_regs,                   fixed_ddr_parm_0[i].ddr_settings,                   sizeof(ddr_cfg_regs));            break;        }    }    if (fixed_ddr_parm_0[i].max_freq == 0)        panic("Unsupported DDR data rate %s MT/s data rate/n",              strmhz(buf, ddr_freq));    ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;    ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;    fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);    /*     * setup laws for DDR. If not interleaving, presuming half memory on     * DDR1 and the other half on DDR2     */    if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {        if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,                         ddr_size,                         LAW_TRGT_IF_DDR_INTRLV) < 0) {            printf("ERROR setting Local Access Windows for DDR/n");            return 0;        }    } else {        lawbar1_target_id = LAW_TRGT_IF_DDR_1;        if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,                         ddr_size,                         lawbar1_target_id) < 0) {            printf("ERROR setting Local Access Windows for DDR/n");            return 0;        }    }    return ddr_size;}

int prt_mpc5xxx_clks (void){    char buf1[32], buf2[32], buf3[32];    printf ("       Bus %s MHz, IPB %s MHz, PCI %s MHz/n",            strmhz(buf1, gd->bus_clk),            strmhz(buf2, gd->arch.ipb_clk),            strmhz(buf3, gd->pci_clk)           );    return (0);}

int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){	char buf[32];	printf("Clock configuration:/n");	printf("  CPU:                 %-4s MHz/n", strmhz(buf, gd->cpu_clk));	printf("  Coherent System Bus: %-4s MHz/n", strmhz(buf, gd->csb_clk));	printf("  IPS Bus:             %-4s MHz/n", strmhz(buf, gd->ips_clk));	printf("  PCI:                 %-4s MHz/n", strmhz(buf, gd->pci_clk));	printf("  DDR:                 %-4s MHz/n", strmhz(buf, 2*gd->csb_clk));	return 0;}

int print_cpuinfo(void){	char buf[32];	printf("CPU: %s/n", AT91_CPU_NAME);	printf("Crystal frequency: %8s MHz/n",					strmhz(buf, get_main_clk_rate()));	printf("CPU clock        : %8s MHz/n",					strmhz(buf, get_cpu_clk_rate()));	printf("Master clock     : %8s MHz/n",					strmhz(buf, get_mck_clk_rate()));	return 0;}

void lcd_show_board_info(void){	ulong dram_size;	uint64_t nand_size;	int i;	char temp[32];	lcd_printf("%s/n", U_BOOT_VERSION);	lcd_printf("(C) 2013 ATMEL Corp/n");	lcd_printf("[email
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