自学教程：C++ syscon_regmap_lookup_by_phandle函数代码示例

static void *ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac){	struct device *dev = &gmac->pdev->dev;	gmac->phy_mode = of_get_phy_mode(dev->of_node);	if (gmac->phy_mode < 0) {		dev_err(dev, "missing phy mode property/n");		return ERR_PTR(-EINVAL);	}	if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) {		dev_err(dev, "missing qcom id property/n");		return ERR_PTR(-EINVAL);	}	/* The GMACs are called 1 to 4 in the documentation, but to simplify the	 * code and keep it consistent with the Linux convention, we'll number	 * them from 0 to 3 here.	 */	if (gmac->id < 0 || gmac->id > 3) {		dev_err(dev, "invalid gmac id/n");		return ERR_PTR(-EINVAL);	}	gmac->core_clk = devm_clk_get(dev, "stmmaceth");	if (IS_ERR(gmac->core_clk)) {		dev_err(dev, "missing stmmaceth clk property/n");		return gmac->core_clk;	}	clk_set_rate(gmac->core_clk, 266000000);	/* Setup the register map for the nss common registers */	gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node,							   "qcom,nss-common");	if (IS_ERR(gmac->nss_common)) {		dev_err(dev, "missing nss-common node/n");		return gmac->nss_common;	}	/* Setup the register map for the qsgmii csr registers */	gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node,							   "qcom,qsgmii-csr");	if (IS_ERR(gmac->qsgmii_csr)) {		dev_err(dev, "missing qsgmii-csr node/n");		return gmac->qsgmii_csr;	}	return NULL;}

static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,				struct device_node *dn){	struct device *dev = mtk->dev;	/*	* wakeup function is optional, so it is not an error if this property	* does not exist, and in such case, no need to get relative	* properties anymore.	*/	of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);	if (!mtk->wakeup_src)		return 0;	mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");	if (IS_ERR(mtk->wk_deb_p0)) {		dev_err(dev, "fail to get wakeup_deb_p0/n");		return PTR_ERR(mtk->wk_deb_p0);	}	mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");	if (IS_ERR(mtk->wk_deb_p1)) {		dev_err(dev, "fail to get wakeup_deb_p1/n");		return PTR_ERR(mtk->wk_deb_p1);	}	mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,						"mediatek,syscon-wakeup");	if (IS_ERR(mtk->pericfg)) {		dev_err(dev, "fail to get pericfg regs/n");		return PTR_ERR(mtk->pericfg);	}	return 0;}

static int exynos_dp_video_phy_probe(struct platform_device *pdev){	struct exynos_dp_video_phy *state;	struct device *dev = &pdev->dev;	const struct of_device_id *match;	struct phy_provider *phy_provider;	struct phy *phy;	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);	if (!state)		return -ENOMEM;	state->regs = syscon_regmap_lookup_by_phandle(dev->of_node,						      "samsung,pmu-syscon");	if (IS_ERR(state->regs)) {		dev_err(dev, "Failed to lookup PMU regmap/n");		return PTR_ERR(state->regs);	}	match = of_match_node(exynos_dp_video_phy_of_match, dev->of_node);	state->drvdata = match->data;	phy = devm_phy_create(dev, NULL, &exynos_dp_video_phy_ops);	if (IS_ERR(phy)) {		dev_err(dev, "failed to create Display Port PHY/n");		return PTR_ERR(phy);	}	phy_set_drvdata(phy, state);	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);	return PTR_ERR_OR_ZERO(phy_provider);}

static int spear1340_miphy_probe(struct platform_device *pdev){	struct device *dev = &pdev->dev;	struct spear1340_miphy_priv *priv;	struct phy_provider *phy_provider;	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);	if (!priv)		return -ENOMEM;	priv->misc =		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");	if (IS_ERR(priv->misc)) {		dev_err(dev, "failed to find misc regmap/n");		return PTR_ERR(priv->misc);	}	priv->phy = devm_phy_create(dev, NULL, &spear1340_miphy_ops);	if (IS_ERR(priv->phy)) {		dev_err(dev, "failed to create SATA PCIe PHY/n");		return PTR_ERR(priv->phy);	}	dev_set_drvdata(dev, priv);	phy_set_drvdata(priv->phy, priv);	phy_provider =		devm_of_phy_provider_register(dev, spear1340_miphy_xlate);	if (IS_ERR(phy_provider)) {		dev_err(dev, "failed to register phy provider/n");		return PTR_ERR(phy_provider);	}	return 0;}

static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,				  struct device *dev){	struct device_node *np = dev->of_node;	int err;	/*  Get TX/RX clocks */	dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx");	if (IS_ERR(dwmac->clk_tx)) {		dev_err(dev, "No tx clock provided.../n");		return PTR_ERR(dwmac->clk_tx);	}	dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx");	if (IS_ERR(dwmac->clk_rx)) {		dev_err(dev, "No rx clock provided.../n");		return PTR_ERR(dwmac->clk_rx);	}	/* Get mode register */	dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");	if (IS_ERR(dwmac->regmap))		return PTR_ERR(dwmac->regmap);	err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);	if (err)		dev_err(dev, "Can't get sysconfig mode offset (%d)/n", err);	return err;}

static int hix5hd2_sata_phy_probe(struct platform_device *pdev){	struct phy_provider *phy_provider;	struct device *dev = &pdev->dev;	struct resource *res;	struct phy *phy;	struct hix5hd2_priv *priv;	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);	if (!priv)		return -ENOMEM;	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	if (!res)		return -EINVAL;	priv->base = devm_ioremap(dev, res->start, resource_size(res));	if (!priv->base)		return -ENOMEM;	priv->peri_ctrl = syscon_regmap_lookup_by_phandle(dev->of_node,					"hisilicon,peripheral-syscon");	if (IS_ERR(priv->peri_ctrl))		priv->peri_ctrl = NULL;	phy = devm_phy_create(dev, NULL, &hix5hd2_sata_phy_ops);	if (IS_ERR(phy)) {		dev_err(dev, "failed to create PHY/n");		return PTR_ERR(phy);	}	phy_set_drvdata(phy, priv);	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);	return PTR_ERR_OR_ZERO(phy_provider);}

static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi){	struct device_node *np = hdmi->dev->of_node;	hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");	if (IS_ERR(hdmi->regmap)) {		DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf/n");		return PTR_ERR(hdmi->regmap);	}	hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");	if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {		hdmi->vpll_clk = NULL;	} else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {		return -EPROBE_DEFER;	} else if (IS_ERR(hdmi->vpll_clk)) {		DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock/n");		return PTR_ERR(hdmi->vpll_clk);	}	hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");	if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {		hdmi->grf_clk = NULL;	} else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {		return -EPROBE_DEFER;	} else if (IS_ERR(hdmi->grf_clk)) {		DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock/n");		return PTR_ERR(hdmi->grf_clk);	}	return 0;}

static int uni_player_parse_dt_audio_glue(struct platform_device *pdev,					  struct uniperif *player){	struct device_node *node = pdev->dev.of_node;	struct regmap *regmap;	struct reg_field regfield[2] = {		/* PCM_CLK_SEL */		REG_FIELD(SYS_CFG_AUDIO_GLUE,			  8 + player->id,			  8 + player->id),		/* PCMP_VALID_SEL */		REG_FIELD(SYS_CFG_AUDIO_GLUE, 0, 1)	};	regmap = syscon_regmap_lookup_by_phandle(node, "st,syscfg");	if (IS_ERR(regmap)) {		dev_err(&pdev->dev, "sti-audio-clk-glue syscf not found/n");		return PTR_ERR(regmap);	}	player->clk_sel = regmap_field_alloc(regmap, regfield[0]);	player->valid_sel = regmap_field_alloc(regmap, regfield[1]);	return 0;}

int of_flash_probe_gemini(struct platform_device *pdev,			  struct device_node *np,			  struct map_info *map){	static struct regmap *rmap;	struct device *dev = &pdev->dev;	u32 val;	int ret;	/* Multiplatform guard */	if (!of_device_is_compatible(np, "cortina,gemini-flash"))		return 0;	rmap = syscon_regmap_lookup_by_phandle(np, "syscon");	if (IS_ERR(rmap)) {		dev_err(dev, "no syscon/n");		return PTR_ERR(rmap);	}	ret = regmap_read(rmap, GLOBAL_STATUS, &val);	if (ret) {		dev_err(dev, "failed to read global status register/n");		return -ENODEV;	}	dev_dbg(dev, "global status reg: %08x/n", val);	/*	 * It would be contradictory if a physmap flash was NOT parallel.	 */	if ((val & FLASH_TYPE_MASK) != FLASH_TYPE_PARALLEL) {		dev_err(dev, "flash is not parallel/n");		return -ENODEV;	}	/*	 * Complain if DT data and hardware definition is different.	 */	if (val & FLASH_WIDTH_16BIT) {		if (map->bankwidth != 2)			dev_warn(dev, "flash hardware say flash is 16 bit wide but DT says it is %d bits wide/n",				 map->bankwidth * 8);	} else {		if (map->bankwidth != 1)			dev_warn(dev, "flash hardware say flash is 8 bit wide but DT says it is %d bits wide/n",				 map->bankwidth * 8);	}	/* Activate parallel (NOR flash) mode */	ret = regmap_update_bits(rmap, GLOBAL_MISC_CTRL,				 FLASH_PADS_MASK,				 SFLASH_PADS_DISABLE | NAND_PADS_DISABLE);	if (ret) {		dev_err(dev, "unable to set up physmap pads/n");		return -ENODEV;	}	dev_info(&pdev->dev, "initialized Gemini-specific physmap control/n");	return 0;}

static int keystone_rproc_of_get_dev_syscon(struct platform_device *pdev,					    struct keystone_rproc *ksproc){	struct device_node *np = pdev->dev.of_node;	struct device *dev = &pdev->dev;	int ret;	if (!of_property_read_bool(np, "ti,syscon-dev")) {		dev_err(dev, "ti,syscon-dev property is absent/n");		return -EINVAL;	}	ksproc->dev_ctrl =		syscon_regmap_lookup_by_phandle(np, "ti,syscon-dev");	if (IS_ERR(ksproc->dev_ctrl)) {		ret = PTR_ERR(ksproc->dev_ctrl);		return ret;	}	if (of_property_read_u32_index(np, "ti,syscon-dev", 1,				       &ksproc->boot_offset)) {		dev_err(dev, "couldn't read the boot register offset/n");		return -EINVAL;	}	return 0;}

static int __init rockchip_ddr_probe(struct platform_device *pdev){	struct device_node *np;	np = pdev->dev.of_node;	ddr_data =	    devm_kzalloc(&pdev->dev, sizeof(struct rockchip_ddr), GFP_KERNEL);	if (!ddr_data) {		dev_err(&pdev->dev, "no memory for state/n");		return -ENOMEM;	}	/* ddrpctl */	ddr_data->ddrpctl_regs =	    syscon_regmap_lookup_by_phandle(np, "rockchip,ddrpctl");	if (IS_ERR(ddr_data->ddrpctl_regs)) {		dev_err(&pdev->dev, "%s: could not find ddrpctl dt node/n",			__func__);		return -ENXIO;	}	/* grf */	ddr_data->grf_regs =	    syscon_regmap_lookup_by_phandle(np, "rockchip,grf");	if (IS_ERR(ddr_data->grf_regs)) {		dev_err(&pdev->dev, "%s: could not find grf dt node/n",			__func__);		return -ENXIO;	}	/* msch */	ddr_data->msch_regs =	    syscon_regmap_lookup_by_phandle(np, "rockchip,msch");	if (IS_ERR(ddr_data->msch_regs)) {		dev_err(&pdev->dev, "%s: could not find msch dt node/n",			__func__);		return -ENXIO;	}	platform_set_drvdata(pdev, ddr_data);	ddr_change_freq = _ddr_change_freq;	ddr_round_rate = _ddr_round_rate;	ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;	ddr_bandwidth_get = _ddr_bandwidth_get;	ddr_recalc_rate = _ddr_recalc_rate;	ddr_init(DDR3_DEFAULT, 0);	pr_info("%s: success/n", __func__);	return 0;}

static int gswip_gphy_fw_list(struct gswip_priv *priv,			      struct device_node *gphy_fw_list_np, u32 version){	struct device *dev = priv->dev;	struct device_node *gphy_fw_np;	const struct of_device_id *match;	int err;	int i = 0;	/* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older	 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also	 * needs a different GPHY firmware.	 */	if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) {		switch (version) {		case GSWIP_VERSION_2_0:			priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data;			break;		case GSWIP_VERSION_2_1:			priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;			break;		default:			dev_err(dev, "unknown GSWIP version: 0x%x", version);			return -ENOENT;		}	}	match = of_match_node(xway_gphy_match, gphy_fw_list_np);	if (match && match->data)		priv->gphy_fw_name_cfg = match->data;	if (!priv->gphy_fw_name_cfg) {		dev_err(dev, "GPHY compatible type not supported");		return -ENOENT;	}	priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);	if (!priv->num_gphy_fw)		return -ENOENT;	priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np,							   "lantiq,rcu");	if (IS_ERR(priv->rcu_regmap))		return PTR_ERR(priv->rcu_regmap);	priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw,					   sizeof(*priv->gphy_fw),					   GFP_KERNEL | __GFP_ZERO);	if (!priv->gphy_fw)		return -ENOMEM;	for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) {		err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i],					  gphy_fw_np, i);		if (err)			goto remove_gphy;		i++;	}

static int syscon_gpio_probe(struct platform_device *pdev){	struct device *dev = &pdev->dev;	const struct of_device_id *of_id;	struct syscon_gpio_priv *priv;	struct device_node *np = dev->of_node;	int ret;	of_id = of_match_device(syscon_gpio_ids, dev);	if (!of_id)		return -ENODEV;	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);	if (!priv)		return -ENOMEM;	priv->data = of_id->data;	if (priv->data->compatible) {		priv->syscon = syscon_regmap_lookup_by_compatible(					priv->data->compatible);		if (IS_ERR(priv->syscon))			return PTR_ERR(priv->syscon);	} else {		priv->syscon =			syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");		if (IS_ERR(priv->syscon))			return PTR_ERR(priv->syscon);		ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,						 &priv->dreg_offset);		if (ret)			dev_err(dev, "can't read the data register offset!/n");		priv->dreg_offset <<= 3;		ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,						 &priv->dir_reg_offset);		if (ret)			dev_dbg(dev, "can't read the dir register offset!/n");		priv->dir_reg_offset <<= 3;	}	priv->chip.parent = dev;	priv->chip.owner = THIS_MODULE;	priv->chip.label = dev_name(dev);	priv->chip.base = -1;	priv->chip.ngpio = priv->data->bit_count;	priv->chip.get = syscon_gpio_get;	if (priv->data->flags & GPIO_SYSCON_FEAT_IN)		priv->chip.direction_input = syscon_gpio_dir_in;	if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {		priv->chip.set = priv->data->set ? : syscon_gpio_set;		priv->chip.direction_output = syscon_gpio_dir_out;	}

static int ks_sa_rng_probe(struct platform_device *pdev){	struct ks_sa_rng	*ks_sa_rng;	struct device		*dev = &pdev->dev;	int			ret;	struct resource		*mem;	ks_sa_rng = devm_kzalloc(dev, sizeof(*ks_sa_rng), GFP_KERNEL);	if (!ks_sa_rng)		return -ENOMEM;	ks_sa_rng->dev = dev;	ks_sa_rng->rng = (struct hwrng) {		.name = "ks_sa_hwrng",		.init = ks_sa_rng_init,		.data_read = ks_sa_rng_data_read,		.data_present = ks_sa_rng_data_present,		.cleanup = ks_sa_rng_cleanup,	};	ks_sa_rng->rng.priv = (unsigned long)dev;	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);	ks_sa_rng->reg_rng = devm_ioremap_resource(dev, mem);	if (IS_ERR(ks_sa_rng->reg_rng))		return PTR_ERR(ks_sa_rng->reg_rng);	ks_sa_rng->regmap_cfg =		syscon_regmap_lookup_by_phandle(dev->of_node,						"ti,syscon-sa-cfg");	if (IS_ERR(ks_sa_rng->regmap_cfg)) {		dev_err(dev, "syscon_node_to_regmap failed/n");		return -EINVAL;	}	pm_runtime_enable(dev);	ret = pm_runtime_get_sync(dev);	if (ret < 0) {		dev_err(dev, "Failed to enable SA power-domain/n");		pm_runtime_disable(dev);		return ret;	}	platform_set_drvdata(pdev, ks_sa_rng);	return devm_hwrng_register(&pdev->dev, &ks_sa_rng->rng);}static int ks_sa_rng_remove(struct platform_device *pdev){	pm_runtime_put_sync(&pdev->dev);	pm_runtime_disable(&pdev->dev);	return 0;}

static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi){	struct device_node *np = hdmi->dev->of_node;	hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");	if (IS_ERR(hdmi->regmap)) {		dev_err(hdmi->dev, "Unable to get gpr/n");		return PTR_ERR(hdmi->regmap);	}	return 0;}

static int __init vf610_mscm_ir_of_init(struct device_node *node,			       struct device_node *parent){	struct irq_domain *domain, *domain_parent;	struct regmap *mscm_cp_regmap;	int ret, cpuid;	domain_parent = irq_find_host(parent);	if (!domain_parent) {		pr_err("vf610_mscm_ir: interrupt-parent not found/n");		return -EINVAL;	}	mscm_ir_data = kzalloc(sizeof(*mscm_ir_data), GFP_KERNEL);	if (!mscm_ir_data)		return -ENOMEM;	mscm_ir_data->mscm_ir_base = of_io_request_and_map(node, 0, "mscm-ir");	if (!mscm_ir_data->mscm_ir_base) {		pr_err("vf610_mscm_ir: unable to map mscm register/n");		ret = -ENOMEM;		goto out_free;	}	mscm_cp_regmap = syscon_regmap_lookup_by_phandle(node, "fsl,cpucfg");	if (IS_ERR(mscm_cp_regmap)) {		ret = PTR_ERR(mscm_cp_regmap);		pr_err("vf610_mscm_ir: regmap lookup for cpucfg failed/n");		goto out_unmap;	}	regmap_read(mscm_cp_regmap, MSCM_CPxNUM, &cpuid);	mscm_ir_data->cpu_mask = 0x1 << cpuid;	domain = irq_domain_add_hierarchy(domain_parent, 0,					  MSCM_IRSPRC_NUM, node,					  &mscm_irq_domain_ops, mscm_ir_data);	if (!domain) {		ret = -ENOMEM;		goto out_unmap;	}	cpu_pm_register_notifier(&mscm_ir_notifier_block);	return 0;out_unmap:	iounmap(mscm_ir_data->mscm_ir_base);out_free:	kfree(mscm_ir_data);	return ret;}

static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi){	struct device_node *np = dsi->dev->of_node;	dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");	if (IS_ERR(dsi->grf_regmap)) {		dev_err(dsi->dev, "Unable to get rockchip,grf/n");		return PTR_ERR(dsi->grf_regmap);	}	return 0;}

static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev){	struct device_node *np = dev->of_node;	struct regmap *sys_mgr_base_addr;	u32 reg_offset, reg_shift;	int ret;	struct device_node *np_splitter;	struct resource res_splitter;	dwmac->interface = of_get_phy_mode(np);	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");	if (IS_ERR(sys_mgr_base_addr)) {		dev_info(dev, "No sysmgr-syscon node found/n");		return PTR_ERR(sys_mgr_base_addr);	}	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);	if (ret) {		dev_info(dev, "Could not read reg_offset from sysmgr-syscon!/n");		return -EINVAL;	}	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);	if (ret) {		dev_info(dev, "Could not read reg_shift from sysmgr-syscon!/n");		return -EINVAL;	}	dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");	np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);	if (np_splitter) {		if (of_address_to_resource(np_splitter, 0, &res_splitter)) {			dev_info(dev, "Missing emac splitter address/n");			return -EINVAL;		}		dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);		if (IS_ERR(dwmac->splitter_base)) {			dev_info(dev, "Failed to mapping emac splitter/n");			return PTR_ERR(dwmac->splitter_base);		}	}	dwmac->reg_offset = reg_offset;	dwmac->reg_shift = reg_shift;	dwmac->sys_mgr_base_addr = sys_mgr_base_addr;	dwmac->dev = dev;	return 0;}

static int ade_dts_parse(struct platform_device *pdev, struct ade_hw_ctx *ctx){	struct resource *res;	struct device *dev = &pdev->dev;	struct device_node *np = pdev->dev.of_node;	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	ctx->base = devm_ioremap_resource(dev, res);	if (IS_ERR(ctx->base)) {		DRM_ERROR("failed to remap ade io base/n");		return  PTR_ERR(ctx->base);	}	ctx->reset = devm_reset_control_get(dev, NULL);	if (IS_ERR(ctx->reset))		return PTR_ERR(ctx->reset);	ctx->noc_regmap =		syscon_regmap_lookup_by_phandle(np, "hisilicon,noc-syscon");	if (IS_ERR(ctx->noc_regmap)) {		DRM_ERROR("failed to get noc regmap/n");		return PTR_ERR(ctx->noc_regmap);	}	ctx->irq = platform_get_irq(pdev, 0);	if (ctx->irq < 0) {		DRM_ERROR("failed to get irq/n");		return -ENODEV;	}	ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core");	if (IS_ERR(ctx->ade_core_clk)) {		DRM_ERROR("failed to parse clk ADE_CORE/n");		return PTR_ERR(ctx->ade_core_clk);	}	ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg");	if (IS_ERR(ctx->media_noc_clk)) {		DRM_ERROR("failed to parse clk CODEC_JPEG/n");		return PTR_ERR(ctx->media_noc_clk);	}	ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix");	if (IS_ERR(ctx->ade_pix_clk)) {		DRM_ERROR("failed to parse clk ADE_PIX/n");		return PTR_ERR(ctx->ade_pix_clk);	}	return 0;}

static int rockchip_dp_init(struct rockchip_dp_device *dp){	struct device *dev = dp->dev;	struct device_node *np = dev->of_node;	int ret;	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");	if (IS_ERR(dp->grf)) {		dev_err(dev, "failed to get rockchip,grf property/n");		return PTR_ERR(dp->grf);	}	dp->grfclk = devm_clk_get(dev, "grf");	if (PTR_ERR(dp->grfclk) == -ENOENT) {		dp->grfclk = NULL;	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {		return -EPROBE_DEFER;	} else if (IS_ERR(dp->grfclk)) {		dev_err(dev, "failed to get grf clock/n");		return PTR_ERR(dp->grfclk);	}	dp->pclk = devm_clk_get(dev, "pclk");	if (IS_ERR(dp->pclk)) {		dev_err(dev, "failed to get pclk property/n");		return PTR_ERR(dp->pclk);	}	dp->rst = devm_reset_control_get(dev, "dp");	if (IS_ERR(dp->rst)) {		dev_err(dev, "failed to get dp reset control/n");		return PTR_ERR(dp->rst);	}	ret = clk_prepare_enable(dp->pclk);	if (ret < 0) {		dev_err(dp->dev, "failed to enable pclk %d/n", ret);		return ret;	}	ret = rockchip_dp_pre_init(dp);	if (ret < 0) {		dev_err(dp->dev, "failed to pre init %d/n", ret);		clk_disable_unprepare(dp->pclk);		return ret;	}	return 0;}

static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data){	struct device *dev = opp_data->cpu_dev;	struct device_node *np = opp_data->opp_node;	opp_data->syscon = syscon_regmap_lookup_by_phandle(np,							"syscon");	if (IS_ERR(opp_data->syscon)) {		dev_err(dev,			"/"syscon/" is missing, cannot use OPPv2 table./n");		return PTR_ERR(opp_data->syscon);	}	return 0;}

static int __init digicolor_of_init(struct device_node *node,				struct device_node *parent){	static void __iomem *reg_base;	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;	struct regmap *ucregs;	int ret;	reg_base = of_iomap(node, 0);	if (!reg_base) {		pr_err("%s: unable to map IC registers/n", node->full_name);		return -ENXIO;	}	/* disable all interrupts */	writel(0, reg_base + IC_INT0ENABLE_LO);	writel(0, reg_base + IC_INT0ENABLE_XLO);	ucregs = syscon_regmap_lookup_by_phandle(node, "syscon");	if (IS_ERR(ucregs)) {		pr_err("%s: unable to map UC registers/n", node->full_name);		return PTR_ERR(ucregs);	}	/* channel 1, regular IRQs */	regmap_write(ucregs, UC_IRQ_CONTROL, 1);	digicolor_irq_domain =		irq_domain_add_linear(node, 64, &irq_generic_chip_ops, NULL);	if (!digicolor_irq_domain) {		pr_err("%s: unable to create IRQ domain/n", node->full_name);		return -ENOMEM;	}	ret = irq_alloc_domain_generic_chips(digicolor_irq_domain, 32, 1,					     "digicolor_irq", handle_level_irq,					     clr, 0, 0);	if (ret) {		pr_err("%s: unable to allocate IRQ gc/n", node->full_name);		return ret;	}	digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO);	digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO);	set_handle_irq(digicolor_handle_irq);	return 0;}

static int hi6210_i2s_probe(struct platform_device *pdev){	struct device_node *node = pdev->dev.of_node;	struct device *dev = &pdev->dev;	struct hi6210_i2s *i2s;	struct resource *res;	int ret;	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);	if (!i2s)		return -ENOMEM;	i2s->dev = dev;	spin_lock_init(&i2s->lock);	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	i2s->base = devm_ioremap_resource(dev, res);	if (IS_ERR(i2s->base))		return PTR_ERR(i2s->base);	i2s->base_phys = (phys_addr_t)res->start;	i2s->dai = hi6210_i2s_dai_init;	dev_set_drvdata(&pdev->dev, i2s);	i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,						"hisilicon,sysctrl-syscon");	if (IS_ERR(i2s->sysctrl))		return PTR_ERR(i2s->sysctrl);	i2s->clk[CLK_DACODEC] = devm_clk_get(&pdev->dev, "dacodec");	if (IS_ERR_OR_NULL(i2s->clk[CLK_DACODEC]))		return PTR_ERR(i2s->clk[CLK_DACODEC]);	i2s->clocks++;	i2s->clk[CLK_I2S_BASE] = devm_clk_get(&pdev->dev, "i2s-base");	if (IS_ERR_OR_NULL(i2s->clk[CLK_I2S_BASE]))		return PTR_ERR(i2s->clk[CLK_I2S_BASE]);	i2s->clocks++;	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);	if (ret)		return ret;	ret = devm_snd_soc_register_component(&pdev->dev, &hi6210_i2s_i2s_comp,					 &i2s->dai, 1);	return ret;}

static int uniphier_pciephy_probe(struct platform_device *pdev){	struct uniphier_pciephy_priv *priv;	struct phy_provider *phy_provider;	struct device *dev = &pdev->dev;	struct regmap *regmap;	struct resource *res;	struct phy *phy;	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);	if (!priv)		return -ENOMEM;	priv->data = of_device_get_match_data(dev);	if (WARN_ON(!priv->data))		return -EINVAL;	priv->dev = dev;	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	priv->base = devm_ioremap_resource(dev, res);	if (IS_ERR(priv->base))		return PTR_ERR(priv->base);	priv->clk = devm_clk_get(dev, NULL);	if (IS_ERR(priv->clk))		return PTR_ERR(priv->clk);	priv->rst = devm_reset_control_get_shared(dev, NULL);	if (IS_ERR(priv->rst))		return PTR_ERR(priv->rst);	phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops);	if (IS_ERR(phy))		return PTR_ERR(phy);	regmap = syscon_regmap_lookup_by_phandle(dev->of_node,						 "socionext,syscon");	if (!IS_ERR(regmap) && priv->data->has_syscon)		regmap_update_bits(regmap, SG_USBPCIESEL,				   SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);	phy_set_drvdata(phy, priv);	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);	return PTR_ERR_OR_ZERO(phy_provider);}

static int exynos_mipi_video_phy_probe(struct platform_device *pdev){	struct exynos_mipi_video_phy *state;	struct device *dev = &pdev->dev;	struct phy_provider *phy_provider;	unsigned int i;	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);	if (!state)		return -ENOMEM;	state->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");	if (IS_ERR(state->regmap)) {		struct resource *res;		dev_info(dev, "regmap lookup failed: %ld/n",			 PTR_ERR(state->regmap));		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);		state->regs = devm_ioremap_resource(dev, res);		if (IS_ERR(state->regs))			return PTR_ERR(state->regs);	}	dev_set_drvdata(dev, state);	spin_lock_init(&state->slock);	for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) {		struct phy *phy = devm_phy_create(dev, NULL,						  &exynos_mipi_video_phy_ops);		if (IS_ERR(phy)) {			dev_err(dev, "failed to create PHY %d/n", i);			return PTR_ERR(phy);		}		state->phys[i].phy = phy;		state->phys[i].index = i;		phy_set_drvdata(phy, &state->phys[i]);	}	phy_provider = devm_of_phy_provider_register(dev,					exynos_mipi_video_phy_xlate);	return PTR_ERR_OR_ZERO(phy_provider);}

static int realview_soc_probe(struct platform_device *pdev){	static struct regmap *syscon_regmap;	struct soc_device *soc_dev;	struct soc_device_attribute *soc_dev_attr;	struct device_node *np = pdev->dev.of_node;	int ret;	syscon_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");	if (IS_ERR(syscon_regmap))		return PTR_ERR(syscon_regmap);	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);	if (!soc_dev_attr)		return -ENOMEM;	ret = of_property_read_string(np, "compatible",				      &soc_dev_attr->soc_id);	if (ret)		return -EINVAL;	soc_dev_attr->machine = "RealView";	soc_dev_attr->family = "Versatile";	soc_dev = soc_device_register(soc_dev_attr);	if (IS_ERR(soc_dev)) {		kfree(soc_dev_attr);		return -ENODEV;	}	ret = regmap_read(syscon_regmap, REALVIEW_SYS_ID_OFFSET,			  &realview_coreid);	if (ret)		return -ENODEV;	device_create_file(soc_device_to_device(soc_dev), &realview_manf_attr);	device_create_file(soc_device_to_device(soc_dev), &realview_board_attr);	device_create_file(soc_device_to_device(soc_dev), &realview_arch_attr);	device_create_file(soc_device_to_device(soc_dev), &realview_build_attr);	dev_info(&pdev->dev, "RealView Syscon Core ID: 0x%08x, HBI-%03x/n",		 realview_coreid,		 ((realview_coreid >> 16) & 0xfff));	/* FIXME: add attributes for SoC to sysfs */	return 0;}

static int syscon_poweroff_probe(struct platform_device *pdev){	char symname[KSYM_NAME_LEN];	int mask_err, value_err;	map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");	if (IS_ERR(map)) {		dev_err(&pdev->dev, "unable to get syscon");		return PTR_ERR(map);	}	if (of_property_read_u32(pdev->dev.of_node, "offset", &offset)) {		dev_err(&pdev->dev, "unable to read 'offset'");		return -EINVAL;	}	value_err = of_property_read_u32(pdev->dev.of_node, "value", &value);	mask_err = of_property_read_u32(pdev->dev.of_node, "mask", &mask);	if (value_err && mask_err) {		dev_err(&pdev->dev, "unable to read 'value' and 'mask'");		return -EINVAL;	}	if (value_err) {		/* support old binding */		value = mask;		mask = 0xFFFFFFFF;	} else if (mask_err) {		/* support value without mask*/		mask = 0xFFFFFFFF;	}	if (pm_power_off) {		lookup_symbol_name((ulong)pm_power_off, symname);		dev_err(&pdev->dev,		"pm_power_off already claimed %p %s",		pm_power_off, symname);		return -EBUSY;	}	pm_power_off = syscon_poweroff;	return 0;}

static int ltq_wdt_xrx_bootstatus_get(struct device *dev){	struct regmap *rcu_regmap;	u32 val;	int err;	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");	if (IS_ERR(rcu_regmap))		return PTR_ERR(rcu_regmap);	err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);	if (err)		return err;	if (val & LTQ_XRX_RCU_RST_STAT_WDT)		return WDIOF_CARDRESET;	return 0;}

static int ltq_wdt_falcon_bootstatus_get(struct device *dev){	struct regmap *rcu_regmap;	u32 val;	int err;	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,						     "lantiq,rcu");	if (IS_ERR(rcu_regmap))		return PTR_ERR(rcu_regmap);	err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);	if (err)		return err;	if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)		return WDIOF_CARDRESET;	return 0;}

static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev){	struct device_node *np = dev->of_node;	struct regmap *sys_mgr_base_addr;	u32 reg_offset, reg_shift;	int ret;	dwmac->stmmac_rst = devm_reset_control_get(dev,						  STMMAC_RESOURCE_NAME);	if (IS_ERR(dwmac->stmmac_rst)) {		dev_info(dev, "Could not get reset control!/n");		return -EINVAL;	}	dwmac->interface = of_get_phy_mode(np);	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");	if (IS_ERR(sys_mgr_base_addr)) {		dev_info(dev, "No sysmgr-syscon node found/n");		return PTR_ERR(sys_mgr_base_addr);	}	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);	if (ret) {		dev_info(dev, "Could not read reg_offset from sysmgr-syscon!/n");		return -EINVAL;	}	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);	if (ret) {		dev_info(dev, "Could not read reg_shift from sysmgr-syscon!/n");		return -EINVAL;	}	dwmac->reg_offset = reg_offset;	dwmac->reg_shift = reg_shift;	dwmac->sys_mgr_base_addr = sys_mgr_base_addr;	dwmac->dev = dev;	return 0;}