自学教程：C++ t1_tpi_read函数代码示例

static int my3126_interrupt_handler(struct cphy *cphy){	u32 val;	u16 val16;	u16 status;	u32 act_count;	adapter_t *adapter;	adapter = cphy->adapter;	if (cphy->count == 50) {		mdio_read(cphy, 0x1, 0x1, &val);		val16 = (u16) val;		status = cphy->bmsr ^ val16;		if (status & BMSR_LSTATUS)			t1_link_changed(adapter, 0);		cphy->bmsr = val16;		/* We have only enabled link change interrupts so it		   must be that		 */		cphy->count = 0;	}	t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL),		SUNI1x10GEXP_BITMSK_MSTAT_SNAP);	t1_tpi_read(adapter,		OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW), &act_count);	t1_tpi_read(adapter,		OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val);	act_count += val;	/* Populate elmer_gpo with the register value */	t1_tpi_read(adapter, A_ELMER0_GPO, &val);	cphy->elmer_gpo = val;	if ( (val & (1 << 8)) || (val & (1 << 19)) ||	     (cphy->act_count == act_count) || cphy->act_on ) {		if (is_T2(adapter))			val |= (1 << 9);		else if (t1_is_T1B(adapter))			val |= (1 << 20);		cphy->act_on = 0;	} else {		if (is_T2(adapter))			val &= ~(1 << 9);		else if (t1_is_T1B(adapter))			val &= ~(1 << 20);		cphy->act_on = 1;	}	t1_tpi_write(adapter, A_ELMER0_GPO, val);	cphy->elmer_gpo = val;	cphy->act_count = act_count;	cphy->count++;	return cphy_cause_link_change;}

static int pm3393_interrupt_clear(struct cmac *cmac){	u32 elmer;	u32 pl_intr;	u32 val32;	pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);	pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);	pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);	pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);	pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);	pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,	       &val32);	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);	pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);	t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);	elmer |= ELMER0_GP_BIT1;	t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);	pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);	pl_intr |= F_PL_INTR_EXT;	writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);	return 0;}

static int mv88x201x_interrupt_clear(struct cphy *cphy){	u32 elmer;	u32 val;#ifdef MV88x2010_LINK_STATUS_BUGS	/* Required to read twice before clear takes affect. */	mdio_read(cphy, 0x1, 0x9003, &val);	mdio_read(cphy, 0x1, 0x9004, &val);	mdio_read(cphy, 0x1, 0x9005, &val);	/* Read this register after the others above it else	 * the register doesn't clear correctly.	 */	mdio_read(cphy, 0x1, 0x1, &val);#endif	/* Clear link status. */	mdio_read(cphy, 0x1, 0x1, &val);	/* Clear PHY LASI interrupts. */	mdio_read(cphy, 0x1, 0x9005, &val);#ifdef MV88x2010_LINK_STATUS_BUGS	/* Do it again. */	mdio_read(cphy, 0x1, 0x9003, &val);	mdio_read(cphy, 0x1, 0x9004, &val);#endif	/* Clear Marvell interrupts through Elmer0. */	t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);	elmer |= ELMER0_GP_BIT6;	t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);	return 0;}

static int pm3393_interrupt_disable(struct cmac *cmac){	u32 elmer;		pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);		pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);		t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);	elmer &= ~ELMER0_GP_BIT1;	t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);		return 0;}

/* Chip Reset */static int mv88x201x_phy_reset(adapter_t *adapter){	u32 val;	t1_tpi_read(adapter, A_ELMER0_GPO, &val);	val &= ~4;	t1_tpi_write(adapter, A_ELMER0_GPO, val);	msleep(100);	t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);	msleep(1000);	/* Now lets enable the Laser. Delay 100us */	t1_tpi_read(adapter, A_ELMER0_GPO, &val);	val |= 0x8000;	t1_tpi_write(adapter, A_ELMER0_GPO, val);	udelay(100);	return 0;}

/* Chip Reset */static int mv88x201x_phy_reset(adapter_t *adapter){	u32 val;	(void) t1_tpi_read(adapter, A_ELMER0_GPO, &val);	val &= ~4;	(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);	DELAY_MS(100);	(void) t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);	DELAY_MS(1000);	/* Now lets enable the Laser. Delay 100us */	(void) t1_tpi_read(adapter, A_ELMER0_GPO, &val);	val |= 0x8000;	(void) t1_tpi_write(adapter, A_ELMER0_GPO, val);	DELAY_US(100);	return 0;}

static int mv88x201x_interrupt_disable(struct cphy *cphy){	u32 elmer;	/* Disable PHY LASI interrupts. */	mdio_write(cphy, 0x1, 0x9002, 0x0);	/* Disable Marvell interrupts through Elmer0. */	t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);	elmer &= ~ELMER0_GP_BIT6;	t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);	return 0;}

/* * External interrupt handler for boards using elmer0. */int t1_elmer0_ext_intr_handler(adapter_t *adapter){	struct cphy *phy;	int phy_cause;	u32 cause;	t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);	switch (board_info(adapter)->board) {#ifdef CONFIG_CHELSIO_T1_1G	case CHBT_BOARD_CHT204:	case CHBT_BOARD_CHT204E:	case CHBT_BOARD_CHN204:	case CHBT_BOARD_CHT204V: {		int i, port_bit;		for_each_port(adapter, i) {			port_bit = i + 1;			if (!(cause & (1 << port_bit)))				continue;			phy = adapter->port[i].phy;			phy_cause = phy->ops->interrupt_handler(phy);			if (phy_cause & cphy_cause_link_change)				t1_link_changed(adapter, i);		}		break;	}	case CHBT_BOARD_CHT101:		if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */			phy = adapter->port[0].phy;			phy_cause = phy->ops->interrupt_handler(phy);			if (phy_cause & cphy_cause_link_change)				t1_link_changed(adapter, 0);		}		break;	case CHBT_BOARD_7500: {		int p;		/*		 * Elmer0's interrupt cause isn't useful here because there is		 * only one bit that can be set for all 4 ports.  This means		 * we are forced to check every PHY's interrupt status		 * register to see who initiated the interrupt.		 */		for_each_port(adapter, p) {			phy = adapter->port[p].phy;			phy_cause = phy->ops->interrupt_handler(phy);			if (phy_cause & cphy_cause_link_change)			    t1_link_changed(adapter, p);		}		break;	}

static int mv88x201x_interrupt_disable(struct cphy *cphy){	/* Disable PHY LASI interrupts. */	cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0x0);	/* Disable Marvell interrupts through Elmer0. */	if (t1_is_asic(cphy->adapter)) {		u32 elmer;		t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);		elmer &= ~ELMER0_GP_BIT6;		t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);	}	return 0;}

static int mv88x201x_interrupt_enable(struct cphy *cphy){	/* Enable PHY LASI interrupts. */	(void) mdio_write(cphy, 0x1, 0x9002, 0x1);	/* Enable Marvell interrupts through Elmer0. */	if (t1_is_asic(cphy->adapter)) {		u32 elmer;		(void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);		elmer |= ELMER0_GP_BIT6;		(void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);	}	return 0;}

static int mv88e1xxx_interrupt_disable(struct cphy *cphy){	/* Disable all phy interrupts. */	(void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0);	/* Disable Marvell interrupts through Elmer0. */	if (t1_is_asic(cphy->adapter)) {		u32 elmer;		t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);		elmer &= ~ELMER0_GP_BIT1;		if (is_T2(cphy->adapter))		    elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4);		t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);	}	return 0;}

static int mv88e1xxx_interrupt_clear(struct cphy *cphy){	u32 elmer;	/* Clear PHY interrupts by reading the register. */	(void) simple_mdio_read(cphy,			MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer);	/* Clear Marvell interrupts through Elmer0. */	if (t1_is_asic(cphy->adapter)) {		t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);		elmer |= ELMER0_GP_BIT1;		if (is_T2(cphy->adapter))		    elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;		t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);	}	return 0;}

static int mv88e1xxx_interrupt_enable(struct cphy *cphy){	/* Enable PHY interrupts. */	(void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER,		   INTR_ENABLE_MASK);	/* Enable Marvell interrupts through Elmer0. */	if (t1_is_asic(cphy->adapter)) {		u32 elmer;		(void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);		elmer |= ELMER0_GP_BIT1;		if (is_T2(cphy->adapter)) {			elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;		}		(void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);	}	return 0;}

static int pm3393_interrupt_clear(struct cmac *cmac){	u32 elmer;	u32 pl_intr;	u32 val32;	/* PM3393 - Clearing HW interrupt blocks. Note, this assumes	 *          bit WCIMODE=0 for a clear-on-read.	 */	pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);	pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);	pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);	pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);	pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);	pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,	       &val32);	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);	/* PM3393 - Global interrupt status	 */	pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);	/* ELMER - External chip interrupts.	 */	t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);	elmer |= ELMER0_GP_BIT1;	t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);	/* TERMINATOR - PL_INTERUPTS_EXT	 */	pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);	pl_intr |= F_PL_INTR_EXT;	writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);	return 0;}

/* To check the activity LED */static int my3126_get_link_status(struct cphy *cphy,			int *link_ok, int *speed, int *duplex, int *fc){	u32 val;	u16 val16;	adapter_t *adapter;	adapter = cphy->adapter;	mdio_read(cphy, 0x1, 0x1, &val);	val16 = (u16) val;	/* Populate elmer_gpo with the register value */	t1_tpi_read(adapter, A_ELMER0_GPO, &val);	cphy->elmer_gpo = val;	*link_ok = (val16 & BMSR_LSTATUS);	if (*link_ok) {		/* Turn on the LED. */		if (is_T2(adapter))			 val &= ~(1 << 8);		else if (t1_is_T1B(adapter))			 val &= ~(1 << 19);	} else {		/* Turn off the LED. */		if (is_T2(adapter))			 val |= (1 << 8);		else if (t1_is_T1B(adapter))			 val |= (1 << 19);	}	t1_tpi_write(adapter, A_ELMER0_GPO, val);	cphy->elmer_gpo = val;	*speed = SPEED_10000;	*duplex = DUPLEX_FULL;	/* need to add flow control */	if (fc)		*fc = PAUSE_RX | PAUSE_TX;	return 0;}

/* * External interrupt handler for boards using elmer0. */int elmer0_ext_intr_handler(adapter_t *adapter){    	struct cphy *phy;	int phy_cause;    	u32 cause;	t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);	switch (board_info(adapter)->board) {	case CHBT_BOARD_N210:	case CHBT_BOARD_N110:		if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */			phy = adapter->port[0].phy;			phy_cause = phy->ops->interrupt_handler(phy);			if (phy_cause & cphy_cause_link_change)				link_changed(adapter, 0);		}		break;	}	t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);	return 0;}

static int pm3393_interrupt_disable(struct cmac *cmac){	u32 elmer;	/* PM3393 - Enabling HW interrupt blocks. */	pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);	pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);	/* PM3393 - Global interrupt enable */	pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);	/* ELMER - External chip interrupts. */	t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);	elmer &= ~ELMER0_GP_BIT1;	t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);	/* TERMINATOR - PL_INTERUPTS_EXT */	/* DO NOT DISABLE TERMINATOR's EXTERNAL INTERRUPTS. ANOTHER CHIP	 * COULD WANT THEM ENABLED. We disable PM3393 at the ELMER level.	 */	return 0;}

static int mv88x201x_interrupt_clear(struct cphy *cphy){	u32 elmer;	u32 val;#ifdef MV88x2010_LINK_STATUS_BUGS	/* Required to read twice before clear takes affect. */	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);	/* Read this register after the others above it else	 * the register doesn't clear correctly.	 */	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);#endif	/* Clear link status. */	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);	/* Clear PHY LASI interrupts. */	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);#ifdef MV88x2010_LINK_STATUS_BUGS	/* Do it again. */	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);#endif	/* Clear Marvell interrupts through Elmer0. */	if (t1_is_asic(cphy->adapter)) {		t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);		elmer |= ELMER0_GP_BIT6;		t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);	}	return 0;}

static int my3126_interrupt_enable(struct cphy *cphy){	schedule_delayed_work(&cphy->phy_update, HZ/30);	t1_tpi_read(cphy->adapter, A_ELMER0_GPO, &cphy->elmer_gpo);	return 0;}

static int pmread(struct cmac *cmac, u32 reg, u32 * data32){	t1_tpi_read(cmac->adapter, OFFSET(reg), data32);	return 0;}