自学教程：C++ tc_init函数代码示例

/*************************************************************************//*******************************************************************************/void HAL_TimerInit(void){	halTimerIrqCount					= 0;	// System Tick	sysclk_enable_peripheral_clock(SYSTIMER_TICK_CHANNEL_ID);	tc_init(SYSTIMER, SYSTIMER_TICK_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK3 | TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC);	NVIC_DisableIRQ(SYSTIMER_TICK_CHANNEL_IRQn);	NVIC_ClearPendingIRQ(SYSTIMER_TICK_CHANNEL_IRQn);	NVIC_EnableIRQ(SYSTIMER_TICK_CHANNEL_IRQn);	tc_enable_interrupt(SYSTIMER, SYSTIMER_TICK_CHANNEL, TC_IER_CPCS);	tc_write_rc(SYSTIMER, SYSTIMER_TICK_CHANNEL, TIMER_TOP);	tc_start(SYSTIMER, SYSTIMER_TICK_CHANNEL);	sysclk_enable_peripheral_clock(SYSTIMER_DELAY_CHANNEL_ID);	tc_init(SYSTIMER, SYSTIMER_DELAY_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK3 | TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC | TC_CMR_CPCDIS | TC_CMR_CPCSTOP);	NVIC_DisableIRQ(SYSTIMER_DELAY_CHANNEL_IRQn);	NVIC_ClearPendingIRQ(SYSTIMER_DELAY_CHANNEL_IRQn);	NVIC_EnableIRQ(SYSTIMER_DELAY_CHANNEL_IRQn);		tc_enable_interrupt(SYSTIMER, SYSTIMER_DELAY_CHANNEL, TC_IER_CPCS);}

static voiddec_maxine_tc_init(void){#if defined(MIPS3)	static struct timecounter tc3 =  {		.tc_get_timecount = (timecounter_get_t *)mips3_cp0_count_read,		.tc_counter_mask = ~0u,		.tc_name = "mips3_cp0_counter",		.tc_quality = 200,	};#endif	static struct timecounter tc = {		.tc_get_timecount = dec_maxine_get_timecount,		.tc_quality = 100,		.tc_frequency = 1000000,		.tc_counter_mask = ~0,		.tc_name = "maxine_fctr",	};	tc_init(&tc);#if defined(MIPS3)	if (MIPS_HAS_CLOCK) {		tc3.tc_frequency = mips_options.mips_cpu_mhz * 1000000;		tc_init(&tc3);	}#endif}

/* 81 */int calc_init_81(LPCALC lpCalc, char *version) {	/* INTIALIZE 81 */	//v2 is basically an 82	if (version[0] == '2') {		memory_init_81(&lpCalc->mem_c);		tc_init(&lpCalc->timer_c, MHZ_2);		CPU_init(&lpCalc->cpu, &lpCalc->mem_c, &lpCalc->timer_c);		ClearDevices(&lpCalc->cpu);		device_init_83(&lpCalc->cpu, 1);	} else {		memory_init_81(&lpCalc->mem_c);		tc_init(&lpCalc->timer_c, MHZ_2);		CPU_init(&lpCalc->cpu, &lpCalc->mem_c, &lpCalc->timer_c);		ClearDevices(&lpCalc->cpu);		device_init_81(&lpCalc->cpu);		}	/* END INTIALIZE 81 */#ifdef WINVER // FIXME: dirty cheater!	lpCalc->flash_cond_break = (LPBREAKPOINT *) calloc(lpCalc->mem_c.flash_size, sizeof(LPBREAKPOINT *));	lpCalc->ram_cond_break = (LPBREAKPOINT *) calloc(lpCalc->mem_c.ram_size, sizeof(LPBREAKPOINT *));	if (version[0] == '2') {		lpCalc->audio			= &lpCalc->cpu.pio.link->audio;		lpCalc->audio->enabled	= FALSE;		lpCalc->audio->init		= FALSE;		lpCalc->audio->timer_c	= &lpCalc->timer_c;	}#endif	return TRUE;}

void sam_timer_early_init(void){#if 0	pmc_enable_periph_clk(ID_TC0);	uint32_t ul_div;	uint32_t ul_tcclks;	uint32_t ul_sysclk = MCLK; // sysclk_get_cpu_hz();	tc_find_mck_divisor(100, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);	tc_init(TC0, 0, TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_CPCTRG);	tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 4);	tc_find_mck_divisor(100, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);	tc_init(TC0, 0, TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_CPCTRG);	tc_write_rc(TC0, 0, 0xffff); // slowest we can run	/* Configure and enable interrupt on RC compare */	NVIC_SetPriority(ID_TC0, arm_cm_highest_priority());	NVIC_EnableIRQ((IRQn_Type) ID_TC0);	tc_enable_interrupt(TC0, 0, TC_IER_CPCS);#endif	tc_start(TC0, 0);    arm_cm_systick_init(MCLK);}

void *platform_configure_timer(platform_hw_timer_callback_t bus_tc_cb_ptr){	struct tc_config timer_config;		system_interrupt_enter_critical_section();	if (hw_timers[0].timer_usage == 0)	{		hw_timers[0].timer_usage = 1;		platform_cc1_cb = bus_tc_cb_ptr;		tc_get_config_defaults(&timer_config);		timer_config.clock_prescaler		= TC_CLOCK_PRESCALER_DIV1;		timer_config.oneshot				= true;		timer_config.counter_size			= TC_COUNTER_SIZE_32BIT;		timer_config.count_direction		= TC_COUNT_DIRECTION_UP;		tc_init(&bus_tc_instance, CONF_BUS_TC_MODULE, &timer_config);		timer_count_per_ms = ((system_gclk_gen_get_hz(timer_config.clock_source)) /1000);		tc_set_count_value(&bus_tc_instance, 0);		tc_enable(&bus_tc_instance);		tc_stop_counter(&bus_tc_instance);		tc_register_callback(&bus_tc_instance, tc_cc1_cb,		TC_CALLBACK_OVERFLOW);		tc_enable_callback(&bus_tc_instance, TC_CALLBACK_OVERFLOW);				hw_timers[0].timer_frequency = (system_gclk_gen_get_hz(timer_config.clock_source));		hw_timers[0].timer_instance = bus_tc_instance;		system_interrupt_leave_critical_section();		return (&hw_timers[0]);	}	system_interrupt_leave_critical_section();	return NULL;}

static void configure_tc(struct tc_module *tc_instance){	//! [setup_6]	struct tc_config config_tc;	struct tc_events config_events;	//! [setup_6]	//! [setup_7]	tc_get_config_defaults(&config_tc);	//! [setup_7]	//! [setup_8]	config_tc.counter_size    = TC_COUNTER_SIZE_8BIT;	config_tc.wave_generation = TC_WAVE_GENERATION_NORMAL_FREQ;	config_tc.clock_source    = GCLK_GENERATOR_1;	config_tc.clock_prescaler = TC_CLOCK_PRESCALER_DIV64;	//! [setup_8]	//! [setup_9]	tc_init(tc_instance, CONF_TC_MODULE, &config_tc);	//! [setup_9]	//! [setup_10]	config_events.generate_event_on_overflow = true;	tc_enable_events(tc_instance, &config_events);	//! [setup_10]	//! [setup_11]	tc_enable(tc_instance);	//! [setup_11]}

voidacpitimerattach(struct device *parent, struct device *self, void *aux){	struct acpitimer_softc *sc = (struct acpitimer_softc *) self;	struct acpi_softc *psc = (struct acpi_softc *) parent;	int rc;	if (psc->sc_fadt->hdr_revision >= 3 &&	    psc->sc_fadt->x_pm_tmr_blk.address != 0)		rc = acpi_map_address(psc, &psc->sc_fadt->x_pm_tmr_blk, 0,		    psc->sc_fadt->pm_tmr_len, &sc->sc_ioh, &sc->sc_iot);	else		rc = acpi_map_address(psc, NULL, psc->sc_fadt->pm_tmr_blk,		    psc->sc_fadt->pm_tmr_len, &sc->sc_ioh, &sc->sc_iot);	if (rc) {		printf(": can't map i/o space/n");		return;	}	printf(": %d Hz, %d bits/n", ACPI_FREQUENCY,	    psc->sc_fadt->flags & FADT_TMR_VAL_EXT ? 32 : 24);	if (psc->sc_fadt->flags & FADT_TMR_VAL_EXT)		acpi_timecounter.tc_counter_mask = 0xffffffffU;	acpi_timecounter.tc_priv = sc;	acpi_timecounter.tc_name = sc->sc_dev.dv_xname;	tc_init(&acpi_timecounter);}

/*---------------------------------------------------------------------------*/voidclock_init(void){#define TIMER_PERIOD  UINT16_MAX#define TIMER         TC3    struct tc_config cfg;    tc_get_config_defaults(&cfg);    cfg.clock_source = GCLK_GENERATOR_5;    cfg.clock_prescaler = TC_CLOCK_PRESCALER_DIV1;    cfg.run_in_standby = false;    cfg.counter_16_bit.compare_capture_channel[0] = TIMER_PERIOD;    tc_init(&tc_instance, TIMER, &cfg);    /*  tc_register_callback(&tc_instance, clock_irq_callback, TC_CALLBACK_OVERFLOW);*/    tc_register_callback(&tc_instance, clock_irq_callback, TC_CALLBACK_CC_CHANNEL0);    /*  tc_register_callback(&tc_instance, clock_irq_callback, TC_CALLBACK_CC_CHANNEL1);        tc_register_callback(&tc_instance, clock_irq_callback, TC_CALLBACK_ERROR);*/    /*  tc_enable_callback(&tc_instance, TC_CALLBACK_OVERFLOW);*/    tc_enable_callback(&tc_instance, TC_CALLBACK_CC_CHANNEL0);    /*  tc_enable_callback(&tc_instance, TC_CALLBACK_CC_CHANNEL1);        tc_enable_callback(&tc_instance, TC_CALLBACK_ERROR);*/    tc_enable(&tc_instance);}

static voidat91_st_initclocks(device_t dev, struct at91_st_softc *sc){	int rel_value;	/*	 * Real time counter increments every clock cycle, need to set before	 * initializing clocks so that DELAY works.	 */	WR4(ST_RTMR, 1);	/* disable watchdog timer */	WR4(ST_WDMR, 0);	rel_value = 32768 / hz;	if (rel_value < 1)		rel_value = 1;	if (32768 % hz) {		device_printf(dev, "Cannot get %d Hz clock; using %dHz/n", hz,		    32768 / rel_value);		hz = 32768 / rel_value;		tick = 1000000 / hz;	}	WR4(ST_PIMR, rel_value);	/* Enable PITS interrupts. */	WR4(ST_IER, ST_SR_PITS);	tc_init(&at91_st_timecounter);}

void config_uart(void){		/* configura pinos */	gpio_configure_group(PINS_UART0_PIO, PINS_UART0, PINS_UART0_FLAGS);		/* ativa clock */	sysclk_enable_peripheral_clock(CONSOLE_UART_ID);		/* Configura
C++ tc_log_error函数代码示例
C++ tc函数代码示例