自学教程：C++ tlb_flush函数代码示例

static void moxie_cpu_reset(CPUState *s){    MoxieCPU *cpu = MOXIE_CPU(s);    MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(cpu);    CPUMoxieState *env = &cpu->env;    mcc->parent_reset(s);    memset(env, 0, sizeof(CPUMoxieState));    env->pc = 0x1000;    tlb_flush(s, 1);}

voidas_activate(struct addrspace *as){#if OPT_ASID    tlb_activate_asid(at_assign(curcpu->c_asids, as));#else    // unused    (void)as;        // invalidate the entire tlb on a context switch    tlb_flush();#endif}

/* S390CPUClass::cpu_reset() */static void s390_cpu_reset(CPUState *s){    S390CPU *cpu = S390_CPU(s);    S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);    CPUS390XState *env = &cpu->env;    env->pfault_token = -1UL;    s390_del_running_cpu(cpu);    scc->parent_reset(s);#if !defined(CONFIG_USER_ONLY)    s->halted = 1;#endif    tlb_flush(s, 1);}

static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n){    switch (n) {    case S390_C0_REGNUM ... S390_C15_REGNUM:        env->cregs[n] = ldtul_p(mem_buf);        if (tcg_enabled()) {            tlb_flush(ENV_GET_CPU(env), 1);        }        cpu_synchronize_post_init(ENV_GET_CPU(env));        return 8;    default:        return 0;    }}

void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val){    CPUState *cs = CPU(x86_env_get_cpu(env));    if ((env->cr[4] & CR4_PKE_MASK) == 0) {        raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());    }    if (ecx != 0 || (val & 0xFFFFFFFF00000000ull)) {        raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());    }    env->pkru = val;    tlb_flush(cs);}

Address X86Memory::mapVirtual(X86Process *p, Address paddr,			      Address vaddr, ulong prot){    /* Map remote pages. */    mapRemote(p, vaddr);    /* Virtual address specified? */    if (vaddr == ZERO)    {	vaddr = findFree(PAGETABFROM_REMOTE, remPageDir);    }    /* Repoint to the correct (remote) page table. */    remPageTab = PAGETABADDR_FROM(vaddr, PAGETABFROM_REMOTE);        /* Does the remote process have the page table in memory? */    if (!(remPageDir[DIRENTRY(vaddr)] & PAGE_PRESENT))    {	/* Nope, allocate a page table first. */	Address newPageTab  = memory->allocatePhysical(PAGESIZE);	newPageTab |= PAGE_PRESENT | PAGE_RW | prot;		/* Map the new page table into remote memory. */	remPageDir[DIRENTRY(vaddr)] = newPageTab;		/* Update caches. */	tlb_flush(remPageTab);		/* Zero the new page. */	memset(remPageTab, 0, PAGESIZE);    }    /* Map physical address to remote virtual address. */    remPageTab[TABENTRY(vaddr)] = (paddr & PAGEMASK) | prot;    tlb_flush(vaddr);    /* Success. */    return (Address) vaddr;}

void openrisc_cpu_do_interrupt(CPUState *cs){    OpenRISCCPU *cpu = OPENRISC_CPU(cs);    CPUOpenRISCState *env = &cpu->env;#ifndef CONFIG_USER_ONLY    if (env->flags & D_FLAG) { /* Delay Slot insn */        env->flags &= ~D_FLAG;        env->sr |= SR_DSX;        if (env->exception_index == EXCP_TICK    ||            env->exception_index == EXCP_INT     ||            env->exception_index == EXCP_SYSCALL ||            env->exception_index == EXCP_FPE) {            env->epcr = env->jmp_pc;        } else {            env->epcr = env->pc - 4;        }    } else {        if (env->exception_index == EXCP_TICK    ||            env->exception_index == EXCP_INT     ||            env->exception_index == EXCP_SYSCALL ||            env->exception_index == EXCP_FPE) {            env->epcr = env->npc;        } else {            env->epcr = env->pc;        }    }    /* For machine-state changed between user-mode and supervisor mode,       we need flush TLB when we enter&exit EXCP.  */    tlb_flush(env, 1);    env->esr = env->sr;    env->sr &= ~SR_DME;    env->sr &= ~SR_IME;    env->sr |= SR_SM;    env->sr &= ~SR_IEE;    env->sr &= ~SR_TEE;    env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;    env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;    if (env->exception_index > 0 && env->exception_index < EXCP_NR) {        env->pc = (env->exception_index << 8);    } else {        cpu_abort(env, "Unhandled exception 0x%x/n", env->exception_index);    }#endif    env->exception_index = -1;}

/* CPUClass::reset() */static void sparc_cpu_reset(CPUState *s){    SPARCCPU *cpu = SPARC_CPU(s);    SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);    CPUSPARCState *env = &cpu->env;    if (qemu_loglevel_mask(CPU_LOG_RESET)) {        qemu_log("CPU Reset (CPU %d)/n", s->cpu_index);        log_cpu_state(env, 0);    }    scc->parent_reset(s);    memset(env, 0, offsetof(CPUSPARCState, breakpoints));    tlb_flush(env, 1);    env->cwp = 0;#ifndef TARGET_SPARC64    env->wim = 1;#endif    env->regwptr = env->regbase + (env->cwp * 16);    CC_OP = CC_OP_FLAGS;#if defined(CONFIG_USER_ONLY)#ifdef TARGET_SPARC64    env->cleanwin = env->nwindows - 2;    env->cansave = env->nwindows - 2;    env->pstate = PS_RMO | PS_PEF | PS_IE;    env->asi = 0x82; /* Primary no-fault */#endif#else#if !defined(TARGET_SPARC64)    env->psret = 0;    env->psrs = 1;    env->psrps = 1;#endif#ifdef TARGET_SPARC64    env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;    env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;    env->tl = env->maxtl;    cpu_tsptr(env)->tt = TT_POWER_ON_RESET;    env->lsu = 0;#else    env->mmuregs[0] &= ~(MMU_E | MMU_NF);    env->mmuregs[0] |= env->def->mmu_bm;#endif    env->pc = 0;    env->npc = env->pc + 4;#endif    env->cache_control = 0;}

static void uc32_cpu_initfn(Object *obj){    UniCore32CPU *cpu = UNICORE32_CPU(obj);    CPUUniCore32State *env = &cpu->env;    cpu_exec_init(env);#ifdef CONFIG_USER_ONLY    env->uncached_asr = ASR_MODE_USER;    env->regs[31] = 0;#else    env->uncached_asr = ASR_MODE_PRIV;    env->regs[31] = 0x03000000;#endif    tlb_flush(env, 1);}

/* * This function implements the munmap(2) syscall. * * As with do_mmap() it should perform the required error checking, * before calling upon vmmap_remove() to do most of the work. * Remember to clear the TLB. */intdo_munmap(void *addr, size_t len){	/*NOT_YET_IMPLEMENTED("VM: do_munmap");*/	int temp_addr = (uintptr_t) addr;	tlb_flush(temp_addr);	KASSERT(NULL != curproc->p_pagedir);	dbg(DBG_PRINT, "(GRADING3A 2.b)curproc->p_pagedir; first ten bits of the virtual address is NOT NULL/n ");	vmmap_remove(curproc->p_vmmap, 0, 0);	return 0;}

static void alpha_cpu_initfn(Object *obj){    AlphaCPU *cpu = ALPHA_CPU(obj);    CPUAlphaState *env = &cpu->env;    cpu_exec_init(env);    tlb_flush(env, 1);#if defined(CONFIG_USER_ONLY)    env->ps = PS_USER_MODE;    cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD                               | FPCR_UNFD | FPCR_INED | FPCR_DNOD                               | FPCR_DYN_NORMAL));#endif    env->lock_addr = -1;    env->fen = 1;}

/* * This function implements the mmap(2) syscall, but only * supports the MAP_SHARED, MAP_PRIVATE, MAP_FIXED, and * MAP_ANON flags. * * Add a mapping to the current process's address space. * You need to do some error checking; see the ERRORS section * of the manpage for the problems you should anticipate. * After error checking most of the work of this function is * done by vmmap_map(), but remember to clear the TLB. */intdo_mmap(void *addr, size_t len, int prot, int flags,int fd, off_t off, void **ret){	/*NOT_YET_IMPLEMENTED("VM: do_mmap");*/	int address = (uintptr_t) addr;	tlb_flush(address);	KASSERT(NULL != curproc->p_pagedir);	dbg(DBG_PRINT, "(GRADING3A 2.a)curproc->p_pagedir; first ten bits of the virtual address is NOT NULL/n ");	vmmap_map(curproc->p_vmmap, curproc->p_files[fd]->f_vnode, 0, 0, prot, flags, off, NULL, (vmarea_t**) ret);	return 0;}

/* CPUClass::reset() */static void s390_cpu_reset(CPUState *s){    S390CPU *cpu = S390_CPU(s);    S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);    CPUS390XState *env = &cpu->env;    if (qemu_loglevel_mask(CPU_LOG_RESET)) {        qemu_log("CPU Reset (CPU %d)/n", env->cpu_index);        log_cpu_state(env, 0);    }    scc->parent_reset(s);    memset(env, 0, offsetof(CPUS390XState, breakpoints));    /* FIXME: reset vector? */    tlb_flush(env, 1);    s390_add_running_cpu(env);}

void cpu_reset(CPUM68KState *env){    if (qemu_loglevel_mask(CPU_LOG_RESET)) {        qemu_log("CPU Reset (CPU %d)/n", env->cpu_index);        log_cpu_state(env, 0);    }    memset(env, 0, offsetof(CPUM68KState, breakpoints));#if !defined (CONFIG_USER_ONLY)    env->sr = 0x2700;#endif    m68k_switch_sp(env);    /* ??? FP regs should be initialized to NaN.  */    env->cc_op = CC_OP_FLAGS;    /* TODO: We should set PC from the interrupt vector.  */    env->pc = 0;    tlb_flush(env, 1);}

/* CPUClass::reset() */static void mips_cpu_reset(CPUState *s){    MIPSCPU *cpu = MIPS_CPU(s);    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);    CPUMIPSState *env = &cpu->env;    if (qemu_loglevel_mask(CPU_LOG_RESET)) {        qemu_log("CPU Reset (CPU %d)/n", s->cpu_index);        log_cpu_state(env, 0);    }    mcc->parent_reset(s);    memset(env, 0, offsetof(CPUMIPSState, breakpoints));    tlb_flush(env, 1);    cpu_state_reset(env);}

void cpu_reset(CPUAVR32State *env){   if (qemu_loglevel_mask(CPU_LOG_RESET)) {      qemu_log("CPU Reset/n");      log_cpu_state(env, 0);   }   memset(env, 0, offsetof(CPUAVR32State, breakpoints));#if defined (CONFIG_USER_ONLY)   env->sreg.sr = AVR32_SR_M_MASK & (AVR32_SR_M_APP << AVR32_SR_M_OFFSET);   /* SN: TBD - Should we enable interrupts??  */#else   /* Supervisor mode with interrupts disabled.  */   env->sreg.sr = (AVR32_SR_M_MASK & (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET)) | AVR32_SR_GM_MASK | AVR32_SR_EM_MASK;#endif   tlb_flush(env, 1);}

/* CPUClass::reset() */static void lm32_cpu_reset(CPUState *s){    LM32CPU *cpu = LM32_CPU(s);    LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);    CPULM32State *env = &cpu->env;    if (qemu_loglevel_mask(CPU_LOG_RESET)) {        qemu_log("CPU Reset (CPU %d)/n", s->cpu_index);        log_cpu_state(env, 0);    }    lcc->parent_reset(s);    tlb_flush(env, 1);    /* reset cpu state */    memset(env, 0, offsetof(CPULM32State, breakpoints));}

/* CPUClass::reset() */static void m68k_cpu_reset(CPUState *s){    M68kCPU *cpu = M68K_CPU(s);    M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu);    CPUM68KState *env = &cpu->env;    mcc->parent_reset(s);    memset(env, 0, offsetof(CPUM68KState, features));#if !defined(CONFIG_USER_ONLY)    env->sr = 0x2700;#endif    m68k_switch_sp(env);    /* ??? FP regs should be initialized to NaN.  */    env->cc_op = CC_OP_FLAGS;    /* TODO: We should set PC from the interrupt vector.  */    env->pc = 0;    tlb_flush(s, 1);}

void openrisc_cpu_do_interrupt(CPUState *cs){#ifndef CONFIG_USER_ONLY    OpenRISCCPU *cpu = OPENRISC_CPU(cs);    CPUOpenRISCState *env = &cpu->env;    env->epcr = env->pc;    if (env->flags & D_FLAG) {        env->flags &= ~D_FLAG;        env->sr |= SR_DSX;        env->epcr -= 4;    }    if (cs->exception_index == EXCP_SYSCALL) {        env->epcr += 4;    }    /* For machine-state changed between user-mode and supervisor mode,       we need flush TLB when we enter&exit EXCP.  */    tlb_flush(cs, 1);    env->esr = env->sr;    env->sr &= ~SR_DME;    env->sr &= ~SR_IME;    env->sr |= SR_SM;    env->sr &= ~SR_IEE;    env->sr &= ~SR_TEE;    env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;    env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;    if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {#ifdef OR32_ARCH_DEFAULT        env->pc = (cs->exception_index << 8);#else        env->pc = 0x100000 + (cs->exception_index << 8);#endif        //printf("pc = 0x%x/n", env->pc);    } else {        cpu_abort(cs, "Unhandled exception 0x%x/n", cs->exception_index);    }#endif    cs->exception_index = -1;}

/* CPUClass::reset() */static void mips_cpu_reset(CPUState *s){    MIPSCPU *cpu = MIPS_CPU(s);    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);    CPUMIPSState *env = &cpu->env;    mcc->parent_reset(s);    memset(env, 0, offsetof(CPUMIPSState, mvp));    tlb_flush(s, 1);    cpu_state_reset(env);#ifndef CONFIG_USER_ONLY    if (kvm_enabled()) {        kvm_mips_reset_vcpu(cpu);    }#endif}

void cpu_reset(CPUSPARCState *env){    if (qemu_loglevel_mask(CPU_LOG_RESET)) {        qemu_log("CPU Reset (CPU %d)/n", env->cpu_index);        log_cpu_state(env, 0);    }    tlb_flush(env, 1);    env->cwp = 0;#ifndef TARGET_SPARC64    env->wim = 1;#endif    env->regwptr = env->regbase + (env->cwp * 16);    CC_OP = CC_OP_FLAGS;#if defined(CONFIG_USER_ONLY)#ifdef TARGET_SPARC64    env->cleanwin = env->nwindows - 2;    env->cansave = env->nwindows - 2;    env->pstate = PS_RMO | PS_PEF | PS_IE;    env->asi = 0x82; /* Primary no-fault */#endif#else#if !defined(TARGET_SPARC64)    env->psret = 0;    env->psrs = 1;    env->psrps = 1;#endif#ifdef TARGET_SPARC64    env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;    env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;    env->tl = env->maxtl;    cpu_tsptr(env)->tt = TT_POWER_ON_RESET;    env->lsu = 0;#else    env->mmuregs[0] &= ~(MMU_E | MMU_NF);    env->mmuregs[0] |= env->def->mmu_bm;#endif    env->pc = 0;    env->npc = env->pc + 4;#endif    env->cache_control = 0;}

int page_replacement_init( FILE *fp, int mech ){  int i;  int err;  int pid;  unsigned int vaddr;  fseek( fp, 0, SEEK_SET );  /* start at beginning */  /* initialize process table, frame table, and TLB */  memset( processes, 0, sizeof(task_t) * MAX_PROCESSES );  memset( physical_mem, 0, sizeof(frame_t) * PHYSICAL_FRAMES );  tlb_flush( );  current_pt = 0;  /* initialize frames with numbers */  for ( i = 0; i < PHYSICAL_FRAMES ; i++ ) {    physical_mem[i].number = i;  }  /* create processes, including initial page table */  while ( fscanf( fp, "%d %x/n", &pid, &vaddr ) == 2 ) {    if ( processes[pid].pagetable == NULL ) {      err = process_create( pid );      if ( err )	return -1;    }  }  fseek( fp, 0, SEEK_SET );  /* reset at beginning */  /* init replacement specific data */  pt_replace_init[mech]( fp );  return 0;}

/* CPUClass::reset() */static void s390_cpu_reset(CPUState *s){    S390CPU *cpu = S390_CPU(s);    S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);    CPUS390XState *env = &cpu->env;    s390_del_running_cpu(cpu);    scc->parent_reset(s);    memset(env, 0, offsetof(CPUS390XState, breakpoints));    /* architectured initial values for CR 0 and 14 */    env->cregs[0] = CR0_RESET;    env->cregs[14] = CR14_RESET;    /* set halted to 1 to make sure we can add the cpu in     * s390_ipl_cpu code, where CPUState::halted is set back to 0     * after incrementing the cpu counter */#if !defined(CONFIG_USER_ONLY)    s->halted = 1;#endif    tlb_flush(env, 1);}

/* CPUClass::reset() */static void superh_cpu_reset(CPUState *s){    SuperHCPU *cpu = SUPERH_CPU(s);    SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);    CPUSH4State *env = &cpu->env;    scc->parent_reset(s);    memset(env, 0, offsetof(CPUSH4State, breakpoints));    tlb_flush(env, 1);    env->pc = 0xA0000000;#if defined(CONFIG_USER_ONLY)    env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */    set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */#else    env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;    env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */    set_float_rounding_mode(float_round_to_zero, &env->fp_status);    set_flush_to_zero(1, &env->fp_status);#endif    set_default_nan_mode(1, &env->fp_status);}

/* CPUClass::reset() */static void m68k_cpu_reset(CPUState *s){    M68kCPU *cpu = M68K_CPU(s);    M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu);    CPUM68KState *env = &cpu->env;    if (qemu_loglevel_mask(CPU_LOG_RESET)) {        qemu_log("CPU Reset (CPU %d)/n", s->cpu_index);        log_cpu_state(env, 0);    }    mcc->parent_reset(s);    memset(env, 0, offsetof(CPUM68KState, breakpoints));#if !defined(CONFIG_USER_ONLY)    env->sr = 0x2700;#endif    m68k_switch_sp(env);    /* ??? FP regs should be initialized to NaN.  */    env->cc_op = CC_OP_FLAGS;    /* TODO: We should set PC from the interrupt vector.  */    env->pc = 0;    tlb_flush(env, 1);}

/* CPUClass:reset() */static void s390_cpu_full_reset(CPUState *s){    S390CPU *cpu = S390_CPU(s);    S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);    CPUS390XState *env = &cpu->env;    int i;    scc->parent_reset(s);    cpu->env.sigp_order = 0;    s390_cpu_set_state(CPU_STATE_STOPPED, cpu);    memset(env, 0, offsetof(CPUS390XState, cpu_num));    /* architectured initial values for CR 0 and 14 */    env->cregs[0] = CR0_RESET;    env->cregs[14] = CR14_RESET;    /* architectured initial value for Breaking-Event-Address register */    env->gbea = 1;    env->pfault_token = -1UL;    env->ext_index = -1;    for (i = 0; i < ARRAY_SIZE(env->io_index); i++) {        env->io_index[i] = -1;    }    /* tininess for underflow is detected before rounding */    set_float_detect_tininess(float_tininess_before_rounding,                              &env->fpu_status);    /* Reset state inside the kernel that we cannot access yet from QEMU. */    if (kvm_enabled()) {        kvm_s390_reset_vcpu(cpu);    }    tlb_flush(s, 1);}

//.........这里部分代码省略.........    qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);    /* Load TLB */    qemu_get_be32s(f, &env->tlb->nb_tlb);    for(i = 0; i < MIPS_TLB_MAX; i++) {        uint16_t flags;        uint8_t asid;        qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);        qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);        qemu_get_8s(f, &asid);        env->tlb->mmu.r4k.tlb[i].ASID = asid;        qemu_get_be16s(f, &flags);        env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1;        env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;        env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;        env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;        env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;        env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;        env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;        qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);        qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);    }    /* Load CPU metastate */    qemu_get_be32s(f, &env->current_tc);    qemu_get_be32s(f, &env->current_fpu);    qemu_get_sbe32s(f, &env->error_code);    qemu_get_be32s(f, &env->hflags);    qemu_get_betls(f, &env->btarget);    qemu_get_sbe32s(f, &i);    env->bcond = i;    /* Load remaining CP1 registers */    qemu_get_sbe32s(f, &env->CP0_Index);    qemu_get_sbe32s(f, &env->CP0_Random);    qemu_get_sbe32s(f, &env->CP0_VPEControl);    qemu_get_sbe32s(f, &env->CP0_VPEConf0);    qemu_get_sbe32s(f, &env->CP0_VPEConf1);    qemu_get_betls(f, &env->CP0_YQMask);    qemu_get_betls(f, &env->CP0_VPESchedule);    qemu_get_betls(f, &env->CP0_VPEScheFBack);    qemu_get_sbe32s(f, &env->CP0_VPEOpt);    qemu_get_betls(f, &env->CP0_EntryLo0);    qemu_get_betls(f, &env->CP0_EntryLo1);    qemu_get_betls(f, &env->CP0_Context);    qemu_get_sbe32s(f, &env->CP0_PageMask);    qemu_get_sbe32s(f, &env->CP0_PageGrain);    qemu_get_sbe32s(f, &env->CP0_Wired);    qemu_get_sbe32s(f, &env->CP0_SRSConf0);    qemu_get_sbe32s(f, &env->CP0_SRSConf1);    qemu_get_sbe32s(f, &env->CP0_SRSConf2);    qemu_get_sbe32s(f, &env->CP0_SRSConf3);    qemu_get_sbe32s(f, &env->CP0_SRSConf4);    qemu_get_sbe32s(f, &env->CP0_HWREna);    qemu_get_betls(f, &env->CP0_BadVAddr);    qemu_get_sbe32s(f, &env->CP0_Count);    qemu_get_betls(f, &env->CP0_EntryHi);    qemu_get_sbe32s(f, &env->CP0_Compare);    qemu_get_sbe32s(f, &env->CP0_Status);    qemu_get_sbe32s(f, &env->CP0_IntCtl);    qemu_get_sbe32s(f, &env->CP0_SRSCtl);    qemu_get_sbe32s(f, &env->CP0_SRSMap);    qemu_get_sbe32s(f, &env->CP0_Cause);    qemu_get_betls(f, &env->CP0_EPC);    qemu_get_sbe32s(f, &env->CP0_PRid);    qemu_get_sbe32s(f, &env->CP0_EBase);    qemu_get_sbe32s(f, &env->CP0_Config0);    qemu_get_sbe32s(f, &env->CP0_Config1);    qemu_get_sbe32s(f, &env->CP0_Config2);    qemu_get_sbe32s(f, &env->CP0_Config3);    qemu_get_sbe32s(f, &env->CP0_Config6);    qemu_get_sbe32s(f, &env->CP0_Config7);    qemu_get_betls(f, &env->lladdr);    for(i = 0; i < 8; i++)        qemu_get_betls(f, &env->CP0_WatchLo[i]);    for(i = 0; i < 8; i++)        qemu_get_sbe32s(f, &env->CP0_WatchHi[i]);    qemu_get_betls(f, &env->CP0_XContext);    qemu_get_sbe32s(f, &env->CP0_Framemask);    qemu_get_sbe32s(f, &env->CP0_Debug);    qemu_get_betls(f, &env->CP0_DEPC);    qemu_get_sbe32s(f, &env->CP0_Performance0);    qemu_get_sbe32s(f, &env->CP0_TagLo);    qemu_get_sbe32s(f, &env->CP0_DataLo);    qemu_get_sbe32s(f, &env->CP0_TagHi);    qemu_get_sbe32s(f, &env->CP0_DataHi);    qemu_get_betls(f, &env->CP0_ErrorEPC);    qemu_get_sbe32s(f, &env->CP0_DESAVE);    /* Load inactive TC state */    for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)        load_tc(f, &env->tcs[i]);    for (i = 0; i < MIPS_FPU_MAX; i++)        load_fpu(f, &env->fpus[i]);    /* XXX: ensure compatiblity for halted bit ? */    tlb_flush(env, 1);    return 0;}

static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,			      uint32_t mem_value){    SH7750State *s = opaque;    uint16_t temp;    switch (addr) {	/* SDRAM controller */    case SH7750_BCR1_A7:        s->bcr1 = mem_value;        return;    case SH7750_BCR4_A7:	if(!has_bcr3_and_bcr4(s))	    error_access("long write", addr);	s->bcr4 = mem_value;	return;    case SH7750_WCR1_A7:    case SH7750_WCR2_A7:    case SH7750_WCR3_A7:    case SH7750_MCR_A7:	ignore_access("long write", addr);	return;	/* IO ports */    case SH7750_PCTRA_A7:	temp = porta_lines(s);	s->pctra = mem_value;	s->portdira = portdir(mem_value);	s->portpullupa = portpullup(mem_value);	porta_changed(s, temp);	return;    case SH7750_PCTRB_A7:	temp = portb_lines(s);	s->pctrb = mem_value;	s->portdirb = portdir(mem_value);	s->portpullupb = portpullup(mem_value);	portb_changed(s, temp);	return;    case SH7750_MMUCR_A7:        if (mem_value & MMUCR_TI) {            cpu_sh4_invalidate_tlb(s->cpu);        }        s->cpu->mmucr = mem_value & ~MMUCR_TI;        return;    case SH7750_PTEH_A7:        /* If asid changes, clear all registered tlb entries. */	if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))	    tlb_flush(s->cpu, 1);	s->cpu->pteh = mem_value;	return;    case SH7750_PTEL_A7:	s->cpu->ptel = mem_value;	return;    case SH7750_PTEA_A7:	s->cpu->ptea = mem_value & 0x0000000f;	return;    case SH7750_TTB_A7:	s->cpu->ttb = mem_value;	return;    case SH7750_TEA_A7:	s->cpu->tea = mem_value;	return;    case SH7750_TRA_A7:	s->cpu->tra = mem_value & 0x000007ff;	return;    case SH7750_EXPEVT_A7:	s->cpu->expevt = mem_value & 0x000007ff;	return;    case SH7750_INTEVT_A7:	s->cpu->intevt = mem_value & 0x000007ff;	return;    case SH7750_CCR_A7:	s->ccr = mem_value;	return;    default:	error_access("long write", addr);        abort();    }}

/* NOTE: must be called outside the CPU execute loop */void cpu_reset(CPUX86State *env){    int i;    if (qemu_loglevel_mask(CPU_LOG_RESET)) {        qemu_log("CPU Reset (CPU %d)/n", env->cpu_index);        log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);    }    memset(env, 0, offsetof(CPUX86State, breakpoints));    tlb_flush(env, 1);    env->old_exception = -1;    /* init to reset state */#ifdef CONFIG_SOFTMMU    env->hflags |= HF_SOFTMMU_MASK;#endif    env->hflags2 |= HF2_GIF_MASK;    cpu_x86_update_cr0(env, 0x60000010);    env->a20_mask = ~0x0;    env->smbase = 0x30000;    env->idt.limit = 0xffff;    env->gdt.limit = 0xffff;    env->ldt.limit = 0xffff;    env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);    env->tr.limit = 0xffff;    env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);    cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,                           DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |                           DESC_R_MASK | DESC_A_MASK);    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |                           DESC_A_MASK);    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |                           DESC_A_MASK);    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |                           DESC_A_MASK);    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |                           DESC_A_MASK);    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,                           DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |                           DESC_A_MASK);    env->eip = 0xfff0;    env->regs[R_EDX] = env->cpuid_version;    env->eflags = 0x2;    /* FPU init */    for(i = 0;i < 8; i++)        env->fptags[i] = 1;    env->fpuc = 0x37f;    env->mxcsr = 0x1f80;    memset(env->dr, 0, sizeof(env->dr));    env->dr[6] = DR6_FIXED_1;    env->dr[7] = DR7_FIXED_1;    cpu_breakpoint_remove_all(env, BP_CPU);    cpu_watchpoint_remove_all(env, BP_CPU);    env->mcg_status = 0;}

inline void cpu_riscv_tlb_flush (CPURISCVState *env, int flush_global){    RISCVCPU *cpu = riscv_env_get_cpu(env);    // Flush QEMU's TLB    tlb_flush(CPU(cpu), flush_global);}