自学教程：C++ to_intel_plane函数代码示例

static void intel_fbc_get_reg_params(struct intel_crtc *crtc,				     struct intel_fbc_reg_params *params){	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);	struct intel_fbc *fbc = &dev_priv->fbc;	struct intel_fbc_state_cache *cache = &fbc->state_cache;	/* Since all our fields are integer types, use memset here so the	 * comparison function can rely on memcmp because the padding will be	 * zero. */	memset(params, 0, sizeof(*params));	params->vma = cache->vma;	params->flags = cache->flags;	params->crtc.pipe = crtc->pipe;	params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;	params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);	params->fb.format = cache->fb.format;	params->fb.stride = cache->fb.stride;	params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))		params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,						32 * fbc->threshold) * 8;}

int intel_sprite_get_colorkey(struct drm_device *dev, void *data,			      struct drm_file *file_priv){	struct drm_intel_sprite_colorkey *get = data;	struct drm_i915_private *dev_priv = dev->dev_private;	struct drm_mode_object *obj;	struct drm_plane *plane;	struct intel_plane *intel_plane;	int ret = 0;	if (!dev_priv)		return -EINVAL;	lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE);	obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);	if (!obj) {		ret = -EINVAL;		goto out_unlock;	}	plane = obj_to_plane(obj);	intel_plane = to_intel_plane(plane);	intel_plane->get_colorkey(plane, get);out_unlock:	lockmgr(&dev->mode_config.mutex, LK_RELEASE);	return ret;}

int intel_sprite_get_colorkey(struct drm_device *dev, void *data,			      struct drm_file *file_priv){	struct drm_intel_sprite_colorkey *get = data;	struct drm_mode_object *obj;	struct drm_plane *plane;	struct intel_plane *intel_plane;	int ret = 0;	if (!drm_core_check_feature(dev, DRIVER_MODESET))		return -ENODEV;	mutex_lock(&dev->mode_config.mutex);	obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);	if (!obj) {		ret = -EINVAL;		goto out_unlock;	}	plane = obj_to_plane(obj);	intel_plane = to_intel_plane(plane);	intel_plane->get_colorkey(plane, get);out_unlock:	mutex_unlock(&dev->mode_config.mutex);	return ret;}

static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc){	if (fbc->enabled)		return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;	else		return fbc->possible_framebuffer_bits;}

static void intel_destroy_plane(struct drm_plane *plane){	struct intel_plane *intel_plane = to_intel_plane(plane);	intel_disable_plane(plane);	drm_plane_cleanup(plane);	drm_free(intel_plane, DRM_MEM_KMS);}

int intel_sprite_set_colorkey(struct drm_device *dev, void *data,			      struct drm_file *file_priv){	struct drm_intel_sprite_colorkey *set = data;	struct drm_i915_private *dev_priv = dev->dev_private;	struct drm_mode_object *obj;	struct drm_plane *plane;	struct intel_plane *intel_plane;	int ret = 0;	if (!dev_priv)		return -EINVAL;	/* Make sure we don't try to enable both src & dest simultaneously */	if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))		return -EINVAL;	lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE);		obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);	if (!obj) {		ret = -EINVAL;		goto out_unlock;	}	plane = obj_to_plane(obj);	intel_plane = to_intel_plane(plane);	ret = intel_plane->update_colorkey(plane, set);out_unlock:	lockmgr(&dev->mode_config.mutex, LK_RELEASE);	return ret;}

static intsnb_update_colorkey(struct drm_plane *plane,		    struct drm_intel_sprite_colorkey *key){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane;	u32 dvscntr;	int ret = 0;	intel_plane = to_intel_plane(plane);	I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);	I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);	I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);	dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));	dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);	if (key->flags & I915_SET_COLORKEY_DESTINATION)		dvscntr |= DVS_DEST_KEY;	else if (key->flags & I915_SET_COLORKEY_SOURCE)		dvscntr |= DVS_SOURCE_KEY;	I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);	POSTING_READ(DVSKEYMSK(intel_plane->pipe));	return ret;}

static intintel_disable_plane(struct drm_plane *plane){	struct drm_device *dev = plane->dev;	struct intel_plane *intel_plane = to_intel_plane(plane);	int ret = 0;	if (intel_plane->primary_disabled) {		intel_enable_primary(plane->crtc);		intel_plane->primary_disabled = false;	}	intel_plane->disable_plane(plane);	if (!intel_plane->obj)		goto out;	DRM_LOCK(dev);	intel_unpin_fb_obj(intel_plane->obj);	intel_plane->obj = NULL;	DRM_UNLOCK(dev);out:	return ret;}

static intivb_update_colorkey(struct drm_plane *plane,		    struct drm_intel_sprite_colorkey *key){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane;	u32 sprctl;	int ret = 0;	intel_plane = to_intel_plane(plane);	I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);	I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);	I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);	sprctl = I915_READ(SPRCTL(intel_plane->pipe));	sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);	if (key->flags & I915_SET_COLORKEY_DESTINATION)		sprctl |= SPRITE_DEST_KEY;	else if (key->flags & I915_SET_COLORKEY_SOURCE)		sprctl |= SPRITE_SOURCE_KEY;	I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);	POSTING_READ(SPRKEYMSK(intel_plane->pipe));	return ret;}

static void intel_plane_atomic_update(struct drm_plane *plane,				      struct drm_plane_state *old_state){	struct intel_atomic_state *state = to_intel_atomic_state(old_state->state);	struct intel_plane *intel_plane = to_intel_plane(plane);	const struct intel_plane_state *new_plane_state =		intel_atomic_get_new_plane_state(state, intel_plane);	struct drm_crtc *crtc = new_plane_state->base.crtc ?: old_state->crtc;	if (new_plane_state->base.visible) {		const struct intel_crtc_state *new_crtc_state =			intel_atomic_get_new_crtc_state(state, to_intel_crtc(crtc));		trace_intel_update_plane(plane,					 to_intel_crtc(crtc));		intel_plane->update_plane(intel_plane,					  new_crtc_state, new_plane_state);	} else {		trace_intel_disable_plane(plane,					  to_intel_crtc(crtc));		intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));	}}

int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,					struct intel_crtc_state *crtc_state,					const struct intel_plane_state *old_plane_state,					struct intel_plane_state *intel_state){	struct drm_plane *plane = intel_state->base.plane;	struct drm_plane_state *state = &intel_state->base;	struct intel_plane *intel_plane = to_intel_plane(plane);	int ret;	if (!intel_state->base.crtc && !old_plane_state->base.crtc)		return 0;	intel_state->base.visible = false;	ret = intel_plane->check_plane(crtc_state, intel_state);	if (ret)		return ret;	/* FIXME pre-g4x don't work like this */	if (state->visible)		crtc_state->active_planes |= BIT(intel_plane->id);	else		crtc_state->active_planes &= ~BIT(intel_plane->id);	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)		crtc_state->nv12_planes |= BIT(intel_plane->id);	else		crtc_state->nv12_planes &= ~BIT(intel_plane->id);	return intel_plane_atomic_calc_changes(old_crtc_state,					       &crtc_state->base,					       old_plane_state,					       state);}

static void intel_plane_atomic_update(struct drm_plane *plane,				      struct drm_plane_state *old_state){	struct intel_plane *intel_plane = to_intel_plane(plane);	struct intel_plane_state *intel_state =		to_intel_plane_state(plane->state);	intel_plane->commit_plane(plane, intel_state);}

/** * intel_atomic_check - validate state object * @dev: drm device * @state: state to validate */int intel_atomic_check(struct drm_device *dev,		       struct drm_atomic_state *state){	int nplanes = dev->mode_config.num_total_plane;	int ncrtcs = dev->mode_config.num_crtc;	int nconnectors = dev->mode_config.num_connector;	enum pipe nuclear_pipe = INVALID_PIPE;	int ret;	int i;	bool not_nuclear = false;	/*	 * FIXME:  At the moment, we only support "nuclear pageflip" on a	 * single CRTC.  Cross-crtc updates will be added later.	 */	for (i = 0; i < nplanes; i++) {		struct intel_plane *plane = to_intel_plane(state->planes[i]);		if (!plane)			continue;		if (nuclear_pipe == INVALID_PIPE) {			nuclear_pipe = plane->pipe;		} else if (nuclear_pipe != plane->pipe) {			DRM_DEBUG_KMS("i915 only support atomic plane operations on a single CRTC at the moment/n");			return -EINVAL;		}	}	/*	 * FIXME:  We only handle planes for now; make sure there are no CRTC's	 * or connectors involved.	 */	state->allow_modeset = false;	for (i = 0; i < ncrtcs; i++) {		struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]);		if (crtc && crtc->pipe != nuclear_pipe)			not_nuclear = true;	}	for (i = 0; i < nconnectors; i++)		if (state->connectors[i] != NULL)			not_nuclear = true;	if (not_nuclear) {		DRM_DEBUG_KMS("i915 only supports atomic plane operations at the moment/n");		return -EINVAL;	}	ret = drm_atomic_helper_check_planes(dev, state);	if (ret)		return ret;	return ret;}

static voidivb_disable_plane(struct drm_plane *plane){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane = to_intel_plane(plane);	int pipe = intel_plane->pipe;	I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);	/* Can't leave the scaler enabled... */	I915_WRITE(SPRSCALE(pipe), 0);	/* Activate double buffered register update */	I915_WRITE(SPRSURF(pipe), 0);	POSTING_READ(SPRSURF(pipe));}

static voidilk_disable_plane(struct drm_plane *plane){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane = to_intel_plane(plane);	int pipe = intel_plane->pipe;	I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);	/* Disable the scaler */	I915_WRITE(DVSSCALE(pipe), 0);	/* Flush double buffered register updates */	I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);	POSTING_READ(DVSSURF(pipe));}

static void intel_plane_atomic_update(struct drm_plane *plane,				      struct drm_plane_state *old_state){	struct intel_plane *intel_plane = to_intel_plane(plane);	struct intel_plane_state *intel_state =		to_intel_plane_state(plane->state);	struct drm_crtc *crtc = plane->state->crtc ?: old_state->crtc;	if (intel_state->visible)		intel_plane->update_plane(plane,					  to_intel_crtc_state(crtc->state),					  intel_state);	else		intel_plane->disable_plane(plane, crtc);}

int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,					struct intel_crtc_state *new_crtc_state,					const struct intel_plane_state *old_plane_state,					struct intel_plane_state *new_plane_state){	struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);	int ret;	new_crtc_state->active_planes &= ~BIT(plane->id);	new_crtc_state->nv12_planes &= ~BIT(plane->id);	new_crtc_state->c8_planes &= ~BIT(plane->id);	new_crtc_state->data_rate[plane->id] = 0;	new_plane_state->base.visible = false;	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)		return 0;	ret = plane->check_plane(new_crtc_state, new_plane_state);	if (ret)		return ret;	/* FIXME pre-g4x don't work like this */	if (new_plane_state->base.visible)		new_crtc_state->active_planes |= BIT(plane->id);	if (new_plane_state->base.visible &&	    is_planar_yuv_format(new_plane_state->base.fb->format->format))		new_crtc_state->nv12_planes |= BIT(plane->id);	if (new_plane_state->base.visible &&	    new_plane_state->base.fb->format->format == DRM_FORMAT_C8)		new_crtc_state->c8_planes |= BIT(plane->id);	if (new_plane_state->base.visible || old_plane_state->base.visible)		new_crtc_state->update_planes |= BIT(plane->id);	new_crtc_state->data_rate[plane->id] =		intel_plane_data_rate(new_crtc_state, new_plane_state);	return intel_plane_atomic_calc_changes(old_crtc_state,					       &new_crtc_state->base,					       old_plane_state,					       &new_plane_state->base);}

static voidivb_disable_plane(struct drm_plane *plane){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane = to_intel_plane(plane);	int pipe = intel_plane->pipe;	I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);	/* Can't leave the scaler enabled... */	if (intel_plane->can_scale)		I915_WRITE(SPRSCALE(pipe), 0);	/* Activate double buffered register update */	I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);	POSTING_READ(SPRSURF(pipe));	dev_priv->sprite_scaling_enabled = false;	intel_update_watermarks(dev);}

static intintel_disable_plane(struct drm_plane *plane){	struct drm_device *dev = plane->dev;	struct intel_plane *intel_plane = to_intel_plane(plane);	int ret = 0;	if (plane->crtc)		intel_enable_primary(plane->crtc);	intel_plane->disable_plane(plane);	if (!intel_plane->obj)		goto out;	mutex_lock(&dev->struct_mutex);	intel_unpin_fb_obj(intel_plane->obj);	intel_plane->obj = NULL;	mutex_unlock(&dev->struct_mutex);out:	return ret;}

static voidilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane;	u32 dvscntr;	intel_plane = to_intel_plane(plane);	key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));	key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));	key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));	key->flags = 0;	dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));	if (dvscntr & DVS_DEST_KEY)		key->flags = I915_SET_COLORKEY_DESTINATION;	else if (dvscntr & DVS_SOURCE_KEY)		key->flags = I915_SET_COLORKEY_SOURCE;	else		key->flags = I915_SET_COLORKEY_NONE;}

static voidivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane;	u32 sprctl;	intel_plane = to_intel_plane(plane);	key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));	key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));	key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));	key->flags = 0;	sprctl = I915_READ(SPRCTL(intel_plane->pipe));	if (sprctl & SPRITE_DEST_KEY)		key->flags = I915_SET_COLORKEY_DESTINATION;	else if (sprctl & SPRITE_SOURCE_KEY)		key->flags = I915_SET_COLORKEY_SOURCE;	else		key->flags = I915_SET_COLORKEY_NONE;}

static voidivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,		 unsigned int crtc_w, unsigned int crtc_h,		 uint32_t x, uint32_t y,		 uint32_t src_w, uint32_t src_h){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane = to_intel_plane(plane);	int pipe = intel_plane->pipe;	u32 sprctl, sprscale = 0;	int pixel_size;	sprctl = I915_READ(SPRCTL(pipe));	/* Mask out pixel format bits in case we change it */	sprctl &= ~SPRITE_PIXFORMAT_MASK;	sprctl &= ~SPRITE_RGB_ORDER_RGBX;	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;	switch (fb->pixel_format) {	case DRM_FORMAT_XBGR8888:		sprctl |= SPRITE_FORMAT_RGBX888;		pixel_size = 4;		break;	case DRM_FORMAT_XRGB8888:		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;		pixel_size = 4;		break;	case DRM_FORMAT_YUYV:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;		pixel_size = 2;		break;	case DRM_FORMAT_YVYU:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;		pixel_size = 2;		break;	case DRM_FORMAT_UYVY:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;		pixel_size = 2;		break;	case DRM_FORMAT_VYUY:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;		pixel_size = 2;		break;	default:		DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888/n");		sprctl |= DVS_FORMAT_RGBX888;		pixel_size = 4;		break;	}	if (obj->tiling_mode != I915_TILING_NONE)		sprctl |= SPRITE_TILED;	/* must disable */	sprctl |= SPRITE_TRICKLE_FEED_DISABLE;	sprctl |= SPRITE_ENABLE;	/* Sizes are 0 based */	src_w--;	src_h--;	crtc_w--;	crtc_h--;	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);	/*	 * IVB workaround: must disable low power watermarks for at least	 * one frame before enabling scaling.  LP watermarks can be re-enabled	 * when scaling is disabled.	 */	if (crtc_w != src_w || crtc_h != src_h) {		if (!dev_priv->sprite_scaling_enabled) {			dev_priv->sprite_scaling_enabled = true;			intel_update_watermarks(dev);			intel_wait_for_vblank(dev, pipe);		}		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;	} else {		if (dev_priv->sprite_scaling_enabled) {			dev_priv->sprite_scaling_enabled = false;			/* potentially re-enable LP watermarks */			intel_update_watermarks(dev);		}	}	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);	if (obj->tiling_mode != I915_TILING_NONE) {		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);	} else {		unsigned long offset;		offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);		I915_WRITE(SPRLINOFF(pipe), offset);	}	I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);	I915_WRITE(SPRSCALE(pipe), sprscale);//.........这里部分代码省略.........

static intintel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,		   struct drm_framebuffer *fb, int crtc_x, int crtc_y,		   unsigned int crtc_w, unsigned int crtc_h,		   uint32_t src_x, uint32_t src_y,		   uint32_t src_w, uint32_t src_h){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	struct intel_plane *intel_plane = to_intel_plane(plane);	struct intel_framebuffer *intel_fb;	struct drm_i915_gem_object *obj, *old_obj;	int pipe = intel_plane->pipe;	int ret = 0;	int x = src_x >> 16, y = src_y >> 16;	int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;	bool disable_primary = false;	intel_fb = to_intel_framebuffer(fb);	obj = intel_fb->obj;	old_obj = intel_plane->obj;	src_w = src_w >> 16;	src_h = src_h >> 16;	/* Pipe must be running... */	if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))		return -EINVAL;	if (crtc_x >= primary_w || crtc_y >= primary_h)		return -EINVAL;	/* Don't modify another pipe's plane */	if (intel_plane->pipe != intel_crtc->pipe)		return -EINVAL;	/*	 * Clamp the width & height into the visible area.  Note we don't	 * try to scale the source if part of the visible region is offscreen.	 * The caller must handle that by adjusting source offset and size.	 */	if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {		crtc_w += crtc_x;		crtc_x = 0;	}	if ((crtc_x + crtc_w) <= 0) /* Nothing to display */		goto out;	if ((crtc_x + crtc_w) > primary_w)		crtc_w = primary_w - crtc_x;	if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {		crtc_h += crtc_y;		crtc_y = 0;	}	if ((crtc_y + crtc_h) <= 0) /* Nothing to display */		goto out;	if (crtc_y + crtc_h > primary_h)		crtc_h = primary_h - crtc_y;	if (!crtc_w || !crtc_h) /* Again, nothing to display */		goto out;	/*	 * We can take a larger source and scale it down, but	 * only so much...  16x is the max on SNB.	 */	if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)		return -EINVAL;	/*	 * If the sprite is completely covering the primary plane,	 * we can disable the primary and save power.	 */	if ((crtc_x == 0) && (crtc_y == 0) &&	    (crtc_w == primary_w) && (crtc_h == primary_h))		disable_primary = true;	DRM_LOCK(dev);	ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);	if (ret)		goto out_unlock;	intel_plane->obj = obj;	/*	 * Be sure to re-enable the primary before the sprite is no longer	 * covering it fully.	 */	if (!disable_primary && intel_plane->primary_disabled) {		intel_enable_primary(crtc);		intel_plane->primary_disabled = false;	}	intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,				  crtc_w, crtc_h, x, y, src_w, src_h);	if (disable_primary) {//.........这里部分代码省略.........

/** * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests * @dev: DRM device * @crtc: intel crtc * @crtc_state: incoming crtc_state to validate and setup scalers * * This function sets up scalers based on staged scaling requests for * a @crtc and its planes. It is called from crtc level check path. If request * is a supportable request, it attaches scalers to requested planes and crtc. * * This function takes into account the current scaler(s) in use by any planes * not being part of this atomic state * *  Returns: *         0 - scalers were setup succesfully *         error code - otherwise */int intel_atomic_setup_scalers(struct drm_device *dev,	struct intel_crtc *intel_crtc,	struct intel_crtc_state *crtc_state){	struct drm_plane *plane = NULL;	struct intel_plane *intel_plane;	struct intel_plane_state *plane_state = NULL;	struct intel_crtc_scaler_state *scaler_state =		&crtc_state->scaler_state;	struct drm_atomic_state *drm_state = crtc_state->base.state;	int num_scalers_need;	int i, j;	num_scalers_need = hweight32(scaler_state->scaler_users);	/*	 * High level flow:	 * - staged scaler requests are already in scaler_state->scaler_users	 * - check whether staged scaling requests can be supported	 * - add planes using scalers that aren't in current transaction	 * - assign scalers to requested users	 * - as part of plane commit, scalers will be committed	 *   (i.e., either attached or detached) to respective planes in hw	 * - as part of crtc_commit, scaler will be either attached or detached	 *   to crtc in hw	 */	/* fail if required scalers > available scalers */	if (num_scalers_need > intel_crtc->num_scalers){		DRM_DEBUG_KMS("Too many scaling requests %d > %d/n",			num_scalers_need, intel_crtc->num_scalers);		return -EINVAL;	}	/* walkthrough scaler_users bits and start assigning scalers */	for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {		int *scaler_id;		const char *name;		int idx;		/* skip if scaler not required */		if (!(scaler_state->scaler_users & (1 << i)))			continue;		if (i == SKL_CRTC_INDEX) {			name = "CRTC";			idx = intel_crtc->base.base.id;			/* panel fitter case: assign as a crtc scaler */			scaler_id = &scaler_state->scaler_id;		} else {			name = "PLANE";			/* plane scaler case: assign as a plane scaler */			/* find the plane that set the bit as scaler_user */			plane = drm_state->planes[i];			/*			 * to enable/disable hq mode, add planes that are using scaler			 * into this transaction			 */			if (!plane) {				struct drm_plane_state *state;				plane = drm_plane_from_index(dev, i);				state = drm_atomic_get_plane_state(drm_state, plane);				if (IS_ERR(state)) {					DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state/n",						plane->base.id);					return PTR_ERR(state);				}				/*				 * the plane is added after plane checks are run,				 * but since this plane is unchanged just do the				 * minimum required validation.				 */				crtc_state->base.planes_changed = true;			}			intel_plane = to_intel_plane(plane);			idx = plane->base.id;			/* plane on different crtc cannot be a scaler user of this crtc *///.........这里部分代码省略.........

static voidilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,		 unsigned int crtc_w, unsigned int crtc_h,		 uint32_t x, uint32_t y,		 uint32_t src_w, uint32_t src_h){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane = to_intel_plane(plane);	int pipe = intel_plane->pipe, pixel_size;	u32 dvscntr, dvsscale;	dvscntr = I915_READ(DVSCNTR(pipe));	/* Mask out pixel format bits in case we change it */	dvscntr &= ~DVS_PIXFORMAT_MASK;	dvscntr &= ~DVS_RGB_ORDER_XBGR;	dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;	switch (fb->pixel_format) {	case DRM_FORMAT_XBGR8888:		dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;		pixel_size = 4;		break;	case DRM_FORMAT_XRGB8888:		dvscntr |= DVS_FORMAT_RGBX888;		pixel_size = 4;		break;	case DRM_FORMAT_YUYV:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;		pixel_size = 2;		break;	case DRM_FORMAT_YVYU:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;		pixel_size = 2;		break;	case DRM_FORMAT_UYVY:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;		pixel_size = 2;		break;	case DRM_FORMAT_VYUY:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;		pixel_size = 2;		break;	default:		DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888/n");		dvscntr |= DVS_FORMAT_RGBX888;		pixel_size = 4;		break;	}	if (obj->tiling_mode != I915_TILING_NONE)		dvscntr |= DVS_TILED;	if (IS_GEN6(dev))		dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */	dvscntr |= DVS_ENABLE;	/* Sizes are 0 based */	src_w--;	src_h--;	crtc_w--;	crtc_h--;	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);	dvsscale = 0;	if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);	if (obj->tiling_mode != I915_TILING_NONE) {		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);	} else {		unsigned long offset;		offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);		I915_WRITE(DVSLINOFF(pipe), offset);	}	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);	I915_WRITE(DVSSCALE(pipe), dvsscale);	I915_WRITE(DVSCNTR(pipe), dvscntr);	I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset);	POSTING_READ(DVSSURF(pipe));}

static voidivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,		 unsigned int crtc_w, unsigned int crtc_h,		 uint32_t x, uint32_t y,		 uint32_t src_w, uint32_t src_h){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane = to_intel_plane(plane);	int pipe = intel_plane->pipe;	u32 sprctl, sprscale = 0;	unsigned long sprsurf_offset, linear_offset;	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);	bool scaling_was_enabled = dev_priv->sprite_scaling_enabled;	sprctl = I915_READ(SPRCTL(pipe));	/* Mask out pixel format bits in case we change it */	sprctl &= ~SPRITE_PIXFORMAT_MASK;	sprctl &= ~SPRITE_RGB_ORDER_RGBX;	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;	sprctl &= ~SPRITE_TILED;	switch (fb->pixel_format) {	case DRM_FORMAT_XBGR8888:		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;		break;	case DRM_FORMAT_XRGB8888:		sprctl |= SPRITE_FORMAT_RGBX888;		break;	case DRM_FORMAT_YUYV:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;		break;	case DRM_FORMAT_YVYU:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;		break;	case DRM_FORMAT_UYVY:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;		break;	case DRM_FORMAT_VYUY:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;		break;	default:		BUG();	}	if (obj->tiling_mode != I915_TILING_NONE)		sprctl |= SPRITE_TILED;	/* must disable */	sprctl |= SPRITE_TRICKLE_FEED_DISABLE;	sprctl |= SPRITE_ENABLE;	if (IS_HASWELL(dev))		sprctl |= SPRITE_PIPE_CSC_ENABLE;	/* Sizes are 0 based */	src_w--;	src_h--;	crtc_w--;	crtc_h--;	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);	/*	 * IVB workaround: must disable low power watermarks for at least	 * one frame before enabling scaling.  LP watermarks can be re-enabled	 * when scaling is disabled.	 */	if (crtc_w != src_w || crtc_h != src_h) {		dev_priv->sprite_scaling_enabled |= 1 << pipe;		if (!scaling_was_enabled) {			intel_update_watermarks(dev);			intel_wait_for_vblank(dev, pipe);		}		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;	} else		dev_priv->sprite_scaling_enabled &= ~(1 << pipe);	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);	linear_offset = y * fb->pitches[0] + x * pixel_size;	sprsurf_offset =		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,					       pixel_size, fb->pitches[0]);	linear_offset -= sprsurf_offset;	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET	 * register */	if (IS_HASWELL(dev))		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);	else if (obj->tiling_mode != I915_TILING_NONE)		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);	else		I915_WRITE(SPRLINOFF(pipe), linear_offset);	I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);//.........这里部分代码省略.........

static int intel_plane_atomic_check(struct drm_plane *plane,				    struct drm_plane_state *state){	struct drm_crtc *crtc = state->crtc;	struct intel_crtc *intel_crtc;	struct intel_crtc_state *crtc_state;	struct intel_plane *intel_plane = to_intel_plane(plane);	struct intel_plane_state *intel_state = to_intel_plane_state(state);	struct drm_crtc_state *drm_crtc_state;	int ret;	crtc = crtc ? crtc : plane->state->crtc;	intel_crtc = to_intel_crtc(crtc);	/*	 * Both crtc and plane->crtc could be NULL if we're updating a	 * property while the plane is disabled.  We don't actually have	 * anything driver-specific we need to test in that case, so	 * just return success.	 */	if (!crtc)		return 0;	drm_crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);	if (WARN_ON(!drm_crtc_state))		return -EINVAL;	crtc_state = to_intel_crtc_state(drm_crtc_state);	/*	 * The original src/dest coordinates are stored in state->base, but	 * we want to keep another copy internal to our driver that we can	 * clip/modify ourselves.	 */	intel_state->src.x1 = state->src_x;	intel_state->src.y1 = state->src_y;	intel_state->src.x2 = state->src_x + state->src_w;	intel_state->src.y2 = state->src_y + state->src_h;	intel_state->dst.x1 = state->crtc_x;	intel_state->dst.y1 = state->crtc_y;	intel_state->dst.x2 = state->crtc_x + state->crtc_w;	intel_state->dst.y2 = state->crtc_y + state->crtc_h;	/* Clip all planes to CRTC size, or 0x0 if CRTC is disabled */	intel_state->clip.x1 = 0;	intel_state->clip.y1 = 0;	intel_state->clip.x2 =		crtc_state->base.enable ? crtc_state->pipe_src_w : 0;	intel_state->clip.y2 =		crtc_state->base.enable ? crtc_state->pipe_src_h : 0;	if (state->fb && intel_rotation_90_or_270(state->rotation)) {		if (!(state->fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||			state->fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)) {			DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!/n");			return -EINVAL;		}		/*		 * 90/270 is not allowed with RGB64 16:16:16:16,		 * RGB 16-bit 5:6:5, and Indexed 8-bit.		 * TBD: Add RGB64 case once its added in supported format list.		 */		switch (state->fb->pixel_format) {		case DRM_FORMAT_C8:		case DRM_FORMAT_RGB565:			DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!/n",					drm_get_format_name(state->fb->pixel_format));			return -EINVAL;		default:			break;		}	}	intel_state->visible = false;	ret = intel_plane->check_plane(plane, crtc_state, intel_state);	if (ret)		return ret;	return intel_plane_atomic_calc_changes(&crtc_state->base, state);}