自学教程：C++ to_platform_device函数代码示例

static int armada_drm_bind(struct device *dev){	return drm_platform_init(&armada_drm_driver, to_platform_device(dev));}

static int s3cfb_ioctl(struct fb_info *fb, unsigned int cmd, unsigned long arg){	struct s3cfb_global *fbdev =		platform_get_drvdata(to_platform_device(fb->device));	struct fb_var_screeninfo *var = &fb->var;	struct s3cfb_window *win = fb->par;	struct s3cfb_lcd *lcd = fbdev->lcd;	struct fb_fix_screeninfo *fix = &fb->fix;	struct s3cfb_next_info next_fb_info;	int ret = 0;	union {		struct s3cfb_user_window user_window;		struct s3cfb_user_plane_alpha user_alpha;		struct s3cfb_user_chroma user_chroma;		int vsync;	} p;	switch (cmd) {	case FBIO_WAITFORVSYNC:		s3cfb_wait_for_vsync(fbdev);		break;	// Custom IOCTL added to return the VSYNC timestamp	case S3CFB_WAIT_FOR_VSYNC:		ret = s3cfb_wait_for_vsync(fbdev);		if(ret > 0) {			u64 nsecs = ktime_to_ns(fbdev->vsync_timestamp);			copy_to_user((void*)arg, &nsecs, sizeof(u64));		}		break;	case S3CFB_WIN_POSITION:		if (copy_from_user(&p.user_window,				   (struct s3cfb_user_window __user *)arg,				   sizeof(p.user_window)))			ret = -EFAULT;		else {			if (p.user_window.x < 0)				p.user_window.x = 0;			if (p.user_window.y < 0)				p.user_window.y = 0;			if (p.user_window.x + var->xres > lcd->width)				win->x = lcd->width - var->xres;			else				win->x = p.user_window.x;			if (p.user_window.y + var->yres > lcd->height)				win->y = lcd->height - var->yres;			else				win->y = p.user_window.y;			s3cfb_set_window_position(fbdev, win->id);		}		break;	case S3CFB_WIN_SET_PLANE_ALPHA:		if (copy_from_user(&p.user_alpha,				   (struct s3cfb_user_plane_alpha __user *)arg,				   sizeof(p.user_alpha)))			ret = -EFAULT;		else {			win->alpha.mode = PLANE_BLENDING;			win->alpha.channel = p.user_alpha.channel;			win->alpha.value =			    S3CFB_AVALUE(p.user_alpha.red,					 p.user_alpha.green, p.user_alpha.blue);			s3cfb_set_alpha_blending(fbdev, win->id);		}		break;	case S3CFB_WIN_SET_CHROMA:		if (copy_from_user(&p.user_chroma,				   (struct s3cfb_user_chroma __user *)arg,				   sizeof(p.user_chroma)))			ret = -EFAULT;		else {			win->chroma.enabled = p.user_chroma.enabled;			win->chroma.key = S3CFB_CHROMA(p.user_chroma.red,						       p.user_chroma.green,						       p.user_chroma.blue);			s3cfb_set_chroma_key(fbdev, win->id);		}		break;	case S3CFB_SET_VSYNC_INT:		if (get_user(p.vsync, (int __user *)arg))			ret = -EFAULT;		else {			if (p.vsync)				s3cfb_set_global_interrupt(fbdev, 1);			s3cfb_set_vsync_interrupt(fbdev, p.vsync);		}		break;//.........这里部分代码省略.........

void s3cfb_late_resume(struct early_suspend *h){	struct s3cfb_global *fbdev =		container_of(h, struct s3cfb_global, early_suspend);	struct s3c_platform_fb *pdata = to_fb_plat(fbdev->dev);	struct platform_device *pdev = to_platform_device(fbdev->dev);	struct fb_info *fb;	struct s3cfb_window *win;	int i, j, ret;	pr_info("s3cfb_late_resume is called/n");	ret = regulator_enable(fbdev->regulator);	if (ret < 0)		dev_err(fbdev->dev, "failed to enable regulator/n");	ret = regulator_enable(fbdev->vcc_lcd);	if (ret < 0)		dev_err(fbdev->dev, "failed to enable vcc_lcd/n");	ret = regulator_enable(fbdev->vlcd);	if (ret < 0)		dev_err(fbdev->dev, "failed to enable vlcd/n");#if defined(CONFIG_FB_S3C_TL2796)	lcd_cfg_gpio_late_resume();#endif	dev_dbg(fbdev->dev, "wake up from suspend/n");	if (pdata->cfg_gpio)		pdata->cfg_gpio(pdev);	clk_enable(fbdev->clock);#ifdef CONFIG_FB_S3C_MDNIE	writel(0x1, S5P_MDNIE_SEL);	writel(3,fbdev->regs + 0x27c);#endif	s3cfb_init_global(fbdev);	s3cfb_set_clock(fbdev);#ifdef CONFIG_FB_S3C_MDNIE	s3c_mdnie_init_global(fbdev);	s3c_mdnie_start(fbdev);#endif	s3cfb_set_alpha_value_width(fbdev, pdata->default_win);	s3cfb_display_on(fbdev);	for (i = pdata->default_win;		i < pdata->nr_wins + pdata->default_win; i++) {			j = i % pdata->nr_wins;			fb = fbdev->fb[j];			win = fb->par;			if ((win->path == DATA_PATH_DMA) && (win->enabled)) {				s3cfb_set_par(fb);				s3cfb_set_window(fbdev, win->id, 1);			}	}	s3cfb_set_vsync_interrupt(fbdev, 1);	s3cfb_set_global_interrupt(fbdev, 1);	if (pdata->backlight_on)		pdata->backlight_on(pdev);	if (pdata->reset_lcd)		pdata->reset_lcd(pdev);	pr_info("s3cfb_late_resume is complete/n");	return ;}

static void sbus_esp_reset_dma(struct esp *esp){	int can_do_burst16, can_do_burst32, can_do_burst64;	int can_do_sbus64, lim;	struct platform_device *op = to_platform_device(esp->dev);	u32 val;	can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;	can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;	can_do_burst64 = 0;	can_do_sbus64 = 0;	if (sbus_can_dma_64bit())		can_do_sbus64 = 1;	if (sbus_can_burst64())		can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;	/* Put the DVMA into a known state. */	if (esp->dmarev != dvmahme) {		val = dma_read32(DMA_CSR);		dma_write32(val | DMA_RST_SCSI, DMA_CSR);		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);	}	switch (esp->dmarev) {	case dvmahme:		dma_write32(DMA_RESET_FAS366, DMA_CSR);		dma_write32(DMA_RST_SCSI, DMA_CSR);		esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS |					DMA_SCSI_DISAB | DMA_INT_ENAB);		esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |					  DMA_BRST_SZ);		if (can_do_burst64)			esp->prev_hme_dmacsr |= DMA_BRST64;		else if (can_do_burst32)			esp->prev_hme_dmacsr |= DMA_BRST32;		if (can_do_sbus64) {			esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;			sbus_set_sbus64(&op->dev, esp->bursts);		}		lim = 1000;		while (dma_read32(DMA_CSR) & DMA_PEND_READ) {			if (--lim == 0) {				printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "				       "will not clear!/n",				       esp->host->unique_id);				break;			}			udelay(1);		}		dma_write32(0, DMA_CSR);		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);		dma_write32(0, DMA_ADDR);		break;	case dvmarev2:		if (esp->rev != ESP100) {			val = dma_read32(DMA_CSR);			dma_write32(val | DMA_3CLKS, DMA_CSR);		}		break;	case dvmarev3:		val = dma_read32(DMA_CSR);		val &= ~DMA_3CLKS;		val |= DMA_2CLKS;		if (can_do_burst32) {			val &= ~DMA_BRST_SZ;			val |= DMA_BRST32;		}		dma_write32(val, DMA_CSR);		break;	case dvmaesc1:		val = dma_read32(DMA_CSR);		val |= DMA_ADD_ENABLE;		val &= ~DMA_BCNT_ENAB;		if (!can_do_burst32 && can_do_burst16) {			val |= DMA_ESC_BURST;		} else {			val &= ~(DMA_ESC_BURST);		}		dma_write32(val, DMA_CSR);		break;	default:		break;	}	/* Enable interrupts.  */	val = dma_read32(DMA_CSR);	dma_write32(val | DMA_INT_ENAB, DMA_CSR);}

int s5p_dp_psr_exit(struct s5p_dp_device *dp){	struct platform_device *pdev;	struct s5p_dp_platdata *pdata;	int timeout_loop = 0;	u8 data;	u32 reg;	int ret = 0;	pdev = to_platform_device(dp->dev);	pdata = pdev->dev.platform_data;	mutex_lock(&dp->lock);	dev_dbg(dp->dev, "%s +/n", __func__);	if (dp->psr_enter_state == PSR_NONE) {		dev_info(dp->dev, "%s: Already edP PSR_EXIT state/n", __func__);		dp->psr_exit_state = PSR_NONE;		mutex_unlock(&dp->lock);		return 0;	}	clk_enable(dp->clock);	s5p_dp_exit_psr(dp);	s5p_dp_set_fifo_reset(dp);	s5p_dp_reset_macro_onoff(dp, 1);	s5p_dp_set_analog_power_down(dp, ANALOG_TOTAL, 0);	if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {		while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {			timeout_loop++;			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {				dev_err(dp->dev, "failed to get pll lock status/n");				ret = -ETIMEDOUT;				goto err_exit;			}			udelay(10);		}	}	ndelay(600);	s5p_dp_clear_fifo_reset(dp);	s5p_dp_reset_macro_onoff(dp, 0);	s5p_dp_reset_serdes_fifo(dp);	/* Set sink to D0 (Normal operation) mode. */	s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,		DPCD_SET_POWER_STATE_D0);	s5p_dp_set_link_train_for_psr(dp, dp->video_info->lane_count,		dp->video_info->link_rate);	s5p_dp_set_idle_en(dp);	timeout_loop = 0;	for (;;) {		timeout_loop++;		if (s5p_dp_get_psr_status(dp) == PSR_STATUS_INACTIVE)			break;		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {			dev_err(dp->dev, "DP: Timeout of PSR inactive/n");			ret = -ETIMEDOUT;			goto err_exit;		}		usleep_range(100, 110);	}	s5p_dp_set_force_stream_valid(dp);	timeout_loop = 0;	for (;;) {		timeout_loop++;		if (s5p_dp_is_video_stream_on(dp) == 0)			break;		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {			dev_err(dp->dev, "Timeout of video streamclk ok/n");			ret = -ETIMEDOUT;			goto err_exit;		}		usleep_range(1000, 1100);	}	timeout_loop = 0;	for (;;) {		timeout_loop++;		s5p_dp_read_byte_from_dpcd(dp,			DPCD_ADDR_SINK_PSR_STATUS,			&data);		if (data == SINK_PSR_INACTIVE_STATE || data == 4) {			break;		}		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {			dev_err(dp->dev, "LCD: Timeout of Sink PSR inactive/n");			ret = -ETIMEDOUT;			goto err_exit;		}		usleep_range(100, 110);//.........这里部分代码省略.........

static int s5p_dp_psr_enter(struct s5p_dp_device *dp){	struct platform_device *pdev;	struct s5p_dp_platdata *pdata;	int timeout_loop = 0;	struct fb_event event;	int ret = 0;	u8 data;	pdev = to_platform_device(dp->dev);	pdata = pdev->dev.platform_data;	mutex_lock(&dp->lock);	dev_dbg(dp->dev, "%s +/n", __func__);	if (dp->psr_enter_state == PSR_ENTER_DONE) {		dev_info(dp->dev, "%s: Already edP PSR_ENTER state/n", __func__);		goto err_exit;	}	if (dp->psr_exit_state == PSR_PRE_EXIT) {		dev_info(dp->dev, "%s: edP does not need to PSR_ENTER/n", __func__);		goto err_exit;	}	dp->psr_enter_state = PSR_PRE_ENTER;	s5p_dp_enable_psr(dp);	for (;;) {		timeout_loop++;		if (s5p_dp_get_psr_status(dp) == PSR_STATUS_ACTIVE)			break;		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {			dev_err(dp->dev, "DP: Timeout of PSR active/n");			ret = -ETIMEDOUT;			dp->psr_enter_state = PSR_NONE;			dp->psr_error_count++;			goto err_exit;		}		mdelay(1);	}	mdelay(2);	dev_dbg(dp->dev, "PSR ENTER DP timeout_loop: %d/n", timeout_loop);	s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_SINK_PSR_STATUS, &data);	if (data == 0)		dev_info(dp->dev, "%s: SINK_PSR_STATUS = 0x%02X/n",			__func__, data);	s5p_dp_set_analog_power_down(dp, ANALOG_TOTAL, 1);	clk_disable(dp->clock);	fb_notifier_call_chain(FB_EVENT_PSR_DONE, &event);	dp->psr_enter_state = PSR_ENTER_DONE;err_exit:	dev_dbg(dp->dev, "%s -/n", __func__);	mutex_unlock(&dp->lock);	return ret;}

static int broadcast_tdmb_fc8080_probe(struct spi_device *spi){	int rc;	if(spi == NULL)	{		printk("broadcast_fc8080_probe spi is NULL, so spi can not be set/n");		return -1;	}	fc8080_ctrl_info.TdmbPowerOnState = FALSE;	fc8080_ctrl_info.spi_ptr 				= spi;	fc8080_ctrl_info.spi_ptr->mode 			= SPI_MODE_0;	fc8080_ctrl_info.spi_ptr->bits_per_word 	= 8;	fc8080_ctrl_info.spi_ptr->max_speed_hz 	= (15000*1000);#ifdef FEATURE_DMB_USE_BUS_SCALE	fc8080_ctrl_info.pdev = to_platform_device(&spi->dev);	fc8080_ctrl_info.bus_scale_pdata = msm_bus_cl_get_pdata(fc8080_ctrl_info.pdev);	fc8080_ctrl_info.bus_scale_client_id = msm_bus_scale_register_client(fc8080_ctrl_info.bus_scale_pdata);#endif	// Once I have a spi_device structure I can do a transfer anytime	rc = spi_setup(spi);	printk("broadcast_tdmb_fc8080_probe spi_setup=%d/n", rc);	bbm_com_hostif_select(NULL, 1);#ifdef FEATURE_DMB_USE_XO	fc8080_ctrl_info.clk = clk_get(&fc8080_ctrl_info.spi_ptr->dev, "xo");	if (IS_ERR(fc8080_ctrl_info.clk)) {		rc = PTR_ERR(fc8080_ctrl_info.clk);		dev_err(&fc8080_ctrl_info.spi_ptr->dev, "could not get clock/n");		return rc;	}	/* We enable/disable the clock only to assure it works */	rc = clk_prepare_enable(fc8080_ctrl_info.clk);	if (rc) {		dev_err(&fc8080_ctrl_info.spi_ptr->dev, "could not enable clock/n");		return rc;	}	clk_disable_unprepare(fc8080_ctrl_info.clk);#endif#ifdef FEATURE_DMB_USE_WORKQUEUE	INIT_WORK(&fc8080_ctrl_info.spi_work, broacast_tdmb_spi_work);	fc8080_ctrl_info.spi_wq = create_singlethread_workqueue("tdmb_spi_wq");	if(fc8080_ctrl_info.spi_wq == NULL){		printk("Failed to setup tdmb spi workqueue /n");		return -ENOMEM;	}#endif	tdmb_configure_gpios();#ifdef FEATURE_DMB_USE_WORKQUEUE	rc = request_irq(spi->irq, broadcast_tdmb_spi_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING,	                   spi->dev.driver->name, &fc8080_ctrl_info);#else	rc = request_threaded_irq(spi->irq, NULL, broadcast_tdmb_spi_event_handler, IRQF_ONESHOT | IRQF_DISABLED | IRQF_TRIGGER_FALLING,	                   spi->dev.driver->name, &fc8080_ctrl_info);#endif	printk("broadcast_tdmb_fc8080_probe request_irq=%d/n", rc);	tdmb_fc8080_interrupt_lock();	mutex_init(&fc8080_ctrl_info.mutex);	wake_lock_init(&fc8080_ctrl_info.wake_lock,  WAKE_LOCK_SUSPEND, dev_name(&spi->dev));	spin_lock_init(&fc8080_ctrl_info.spin_lock);#ifdef FEATURE_DMB_USE_PM_QOS	pm_qos_add_request(&fc8080_ctrl_info.pm_req_list, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);#endif	printk("broadcast_fc8080_probe End/n");	return rc;}

/** * dwc3_otg_init - Initializes otg related registers * @dwc: Pointer to out controller context structure * * Returns 0 on success otherwise negative errno. */int dwc3_otg_init(struct dwc3 *dwc){	u32	reg;	int ret = 0;	struct dwc3_otg *dotg;	dev_dbg(dwc->dev, "dwc3_otg_init/n");	/*	 * GHWPARAMS6[10] bit is SRPSupport.	 * This bit also reflects DWC_USB3_EN_OTG	 */	reg = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);	if (!(reg & DWC3_GHWPARAMS6_SRP_SUPPORT)) {		/*		 * No OTG support in the HW core.		 * We return 0 to indicate no error, since this is acceptable		 * situation, just continue probe the dwc3 driver without otg.		 */		dev_dbg(dwc->dev, "dwc3_otg address space is not supported/n");		return 0;	}	/* Allocate and init otg instance */	dotg = kzalloc(sizeof(struct dwc3_otg), GFP_KERNEL);	if (!dotg) {		dev_err(dwc->dev, "unable to allocate dwc3_otg/n");		return -ENOMEM;	}	/* DWC3 has separate IRQ line for OTG events (ID/BSV etc.) */	dotg->irq = platform_get_irq_byname(to_platform_device(dwc->dev),								"otg_irq");	if (dotg->irq < 0) {		dev_err(dwc->dev, "%s: missing OTG IRQ/n", __func__);		ret = -ENODEV;		goto err1;	}	dotg->regs = dwc->regs;	dotg->otg.set_peripheral = dwc3_otg_set_peripheral;	dotg->otg.set_host = dwc3_otg_set_host;	/* This reference is used by dwc3 modules for checking otg existance */	dwc->dotg = dotg;	dotg->otg.phy = kzalloc(sizeof(struct usb_phy), GFP_KERNEL);	if (!dotg->otg.phy) {		dev_err(dwc->dev, "unable to allocate dwc3_otg.phy/n");		ret = -ENOMEM;		goto err1;	}	dotg->dwc = dwc;	dotg->otg.phy->otg = &dotg->otg;	dotg->otg.phy->dev = dwc->dev;	dotg->otg.phy->set_power = dwc3_otg_set_power;	dotg->otg.phy->set_suspend = dwc3_otg_set_suspend;	ret = usb_set_transceiver(dotg->otg.phy);	if (ret) {		dev_err(dotg->otg.phy->dev,			"%s: failed to set transceiver, already exists/n",			__func__);		goto err2;	}	dotg->otg.phy->state = OTG_STATE_UNDEFINED;	init_completion(&dotg->dwc3_xcvr_vbus_init);	INIT_DELAYED_WORK(&dotg->sm_work, dwc3_otg_sm_work);	ret = request_irq(dotg->irq, dwc3_otg_interrupt, IRQF_SHARED,				"dwc3_otg", dotg);	if (ret) {		dev_err(dotg->otg.phy->dev, "failed to request irq #%d --> %d/n",				dotg->irq, ret);		goto err3;	}	pm_runtime_get(dwc->dev);	return 0;err3:	cancel_delayed_work_sync(&dotg->sm_work);	usb_set_transceiver(NULL);err2:	kfree(dotg->otg.phy);err1:	dwc->dotg = NULL;	kfree(dotg);//.........这里部分代码省略.........

static int usbhs_omap_remove_child(struct device *dev, void *data){	dev_info(dev, "unregistering/n");	platform_device_unregister(to_platform_device(dev));	return 0;}

/* subdevs */static int pcap_remove_subdev(struct device *dev, void *unused){	platform_device_unregister(to_platform_device(dev));	return 0;}

int gfar_mdio_probe(struct device *dev){	struct platform_device *pdev = to_platform_device(dev);	struct gianfar_mdio_data *pdata;	struct gfar_mii __iomem *regs;	struct mii_bus *new_bus;	struct resource *r;	int err = 0;	if (NULL == dev)		return -EINVAL;	new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);	if (NULL == new_bus)		return -ENOMEM;	new_bus->name = "Gianfar MII Bus",	new_bus->read = &gfar_mdio_read,	new_bus->write = &gfar_mdio_write,	new_bus->reset = &gfar_mdio_reset,	new_bus->id = pdev->id;	pdata = (struct gianfar_mdio_data *)pdev->dev.platform_data;	if (NULL == pdata) {		printk(KERN_ERR "gfar mdio %d: Missing platform data!/n", pdev->id);		return -ENODEV;	}	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);	/* Set the PHY base address */	regs = ioremap(r->start, sizeof (struct gfar_mii));	if (NULL == regs) {		err = -ENOMEM;		goto reg_map_fail;	}	new_bus->priv = (void __force *)regs;	new_bus->irq = pdata->irq;	new_bus->dev = dev;	dev_set_drvdata(dev, new_bus);	err = mdiobus_register(new_bus);	if (0 != err) {		printk (KERN_ERR "%s: Cannot register as MDIO bus/n", 				new_bus->name);		goto bus_register_fail;	}	return 0;bus_register_fail:	iounmap(regs);reg_map_fail:	kfree(new_bus);	return err;}

static inline char *s3c24xx_serial_portname(struct uart_port *port){	return to_platform_device(port->dev)->name;}

static int exynos_dp_bind(struct device *dev, struct device *master, void *data){	struct exynos_dp_device *dp = dev_get_drvdata(dev);	struct platform_device *pdev = to_platform_device(dev);	struct drm_device *drm_dev = data;	struct drm_encoder *encoder = &dp->encoder;	struct resource *res;	unsigned int irq_flags;	int pipe, ret = 0;	dp->dev = &pdev->dev;	dp->dpms_mode = DRM_MODE_DPMS_OFF;	dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);	if (IS_ERR(dp->video_info))		return PTR_ERR(dp->video_info);	dp->phy = devm_phy_get(dp->dev, "dp");	if (IS_ERR(dp->phy)) {		dev_err(dp->dev, "no DP phy configured/n");		ret = PTR_ERR(dp->phy);		if (ret) {			/*			 * phy itself is not enabled, so we can move forward			 * assigning NULL to phy pointer.			 */			if (ret == -ENOSYS || ret == -ENODEV)				dp->phy = NULL;			else				return ret;		}	}	if (!dp->panel && !dp->ptn_bridge) {		ret = exynos_dp_dt_parse_panel(dp);		if (ret)			return ret;	}	dp->clock = devm_clk_get(&pdev->dev, "dp");	if (IS_ERR(dp->clock)) {		dev_err(&pdev->dev, "failed to get clock/n");		return PTR_ERR(dp->clock);	}	clk_prepare_enable(dp->clock);	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	dp->reg_base = devm_ioremap_resource(&pdev->dev, res);	if (IS_ERR(dp->reg_base))		return PTR_ERR(dp->reg_base);	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);	if (gpio_is_valid(dp->hpd_gpio)) {		/*		 * Set up the hotplug GPIO from the device tree as an interrupt.		 * Simply specifying a different interrupt in the device tree		 * doesn't work since we handle hotplug rather differently when		 * using a GPIO.  We also need the actual GPIO specifier so		 * that we can get the current state of the GPIO.		 */		ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,					    "hpd_gpio");		if (ret) {			dev_err(&pdev->dev, "failed to get hpd gpio/n");			return ret;		}		dp->irq = gpio_to_irq(dp->hpd_gpio);		irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;	} else {		dp->hpd_gpio = -ENODEV;		dp->irq = platform_get_irq(pdev, 0);		irq_flags = 0;	}	if (dp->irq == -ENXIO) {		dev_err(&pdev->dev, "failed to get irq/n");		return -ENODEV;	}	INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,			irq_flags, "exynos-dp", dp);	if (ret) {		dev_err(&pdev->dev, "failed to request irq/n");		return ret;	}	disable_irq(dp->irq);	dp->drm_dev = drm_dev;	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,						  EXYNOS_DISPLAY_TYPE_LCD);	if (pipe < 0)		return pipe;	encoder->possible_crtcs = 1 << pipe;//.........这里部分代码省略.........

struct s3c_platform_fb *to_fb_plat(struct device *dev){	struct platform_device *pdev = to_platform_device(dev);	return (struct s3c_platform_fb *)pdev->dev.platform_data;}

static void s3cfb_init_fbinfo(struct s3cfb_global *ctrl, int id){	struct fb_info *fb = ctrl->fb[id];	struct fb_fix_screeninfo *fix = &fb->fix;	struct fb_var_screeninfo *var = &fb->var;	struct s3cfb_window *win = fb->par;	struct s3cfb_alpha *alpha = &win->alpha;	struct s3cfb_lcd *lcd = ctrl->lcd;	struct s3cfb_lcd_timing *timing = &lcd->timing;	memset(win, 0, sizeof(*win));	platform_set_drvdata(to_platform_device(ctrl->dev), ctrl);	strcpy(fix->id, S3CFB_NAME);	win->id = id;	win->path = DATA_PATH_DMA;	win->dma_burst = 16;	alpha->mode = PLANE_BLENDING;	fb->fbops = &s3cfb_ops;	fb->flags = FBINFO_FLAG_DEFAULT;	fb->pseudo_palette = &win->pseudo_pal;#if (CONFIG_FB_S3C_NR_BUFFERS != 1)	fix->xpanstep = 2;	fix->ypanstep = 1;#else	fix->xpanstep = 0;	fix->ypanstep = 0;#endif	fix->type = FB_TYPE_PACKED_PIXELS;	fix->accel = FB_ACCEL_NONE;	fix->visual = FB_VISUAL_TRUECOLOR;	var->xres = lcd->width;	var->yres = lcd->height;#if defined(CONFIG_FB_S3C_VIRTUAL)	var->xres_virtual = CONFIG_FB_S3C_X_VRES;	var->yres_virtual = CONFIG_FB_S3C_Y_VRES * CONFIG_FB_S3C_NR_BUFFERS;#else	var->xres_virtual = var->xres;	var->yres_virtual = var->yres * CONFIG_FB_S3C_NR_BUFFERS;#endif	var->bits_per_pixel = 32;	var->xoffset = 0;	var->yoffset = 0;	var->width = lcd->p_width;	var->height = lcd->p_height;	var->transp.length = 0;	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;	fix->smem_len = fix->line_length * var->yres_virtual;	var->nonstd = 0;	var->activate = FB_ACTIVATE_NOW;	var->vmode = FB_VMODE_NONINTERLACED;	var->hsync_len = timing->h_sw;	var->vsync_len = timing->v_sw;	var->left_margin = timing->h_fp;	var->right_margin = timing->h_bp;	var->upper_margin = timing->v_fp;	var->lower_margin = timing->v_bp;	ctrl->pixclock_hz = lcd->freq * (var->left_margin + var->right_margin +				var->hsync_len + var->xres) *				(var->upper_margin + var->lower_margin +				var->vsync_len + var->yres);	var->pixclock = KHZ2PICOS(ctrl->pixclock_hz / 1000);	dev_dbg(ctrl->dev, "pixclock: %d/n", var->pixclock);	s3cfb_set_bitfield(var);	s3cfb_set_alpha_info(var, win);}

static int zylonite_mci_init(struct device *dev, irqreturn_t (*zylonite_detect_int)(int, void *, struct pt_regs *), void *data){	int err;	struct platform_device *pdev = to_platform_device(dev);	/*	 * setup GPIO for Zylonite MMC controller	 */	if (pdev->id == 0) {		zylonite_enable_mmc1_pins();#ifndef CONFIG_PXA3xx_MMC2		/* set direction of CD/WP to IN */		mhn_gpio_set_direction(MFP_MMC_CD_0_GPIO, GPIO_DIR_IN);		mhn_gpio_set_direction(MFP_MMC_WP_0_N_GPIO, GPIO_DIR_IN);		/* CD is configured to Falling/Rising Edge detect */		mhn_gpio_set_falling_edge_detect(MFP_MMC_CD_0_GPIO, 1);		mhn_gpio_set_rising_edge_detect (MFP_MMC_CD_0_GPIO, 1);		err = request_irq(MMC1_CD0, zylonite_detect_int, 0,				"MMC card detect slot 1", data);		if (err) {			printk(KERN_ERR				"MMC/SD: can't request MMC card detect"				" IRQ for slot 1/n");			return -1;		}		set_irq_type(MMC1_CD0, IRQT_BOTHEDGE);#else		/* set direction of CD/WP to IN */		mhn_gpio_set_direction(MFP_MMC_CD_1_GPIO, GPIO_DIR_IN);		mhn_gpio_set_direction(MFP_MMC_WP_1_N_GPIO, GPIO_DIR_IN);		/* CD is configured to Falling/Rising Edge detect */		mhn_gpio_set_falling_edge_detect(MFP_MMC_CD_1_GPIO, 1);		mhn_gpio_set_rising_edge_detect (MFP_MMC_CD_1_GPIO, 1);		err = request_irq(MMC1_CD1, zylonite_detect_int, 0,				"MMC card detect slot 2", data);		if (err) {			printk(KERN_ERR				"MMC/SD: can't request MMC card detect"				" IRQ for slot 2/n");			return -1;		}		set_irq_type(MMC1_CD1, IRQT_BOTHEDGE);#endif	}#ifdef CONFIG_PXA310_MMC3 /* 3d MMC/SD slot on Monahans LV */	else if (pdev->id == 1) {		zylonite_enable_mmc3_pins();		/* set direction of CD/WP to IN */		mhn_gpio_set_direction(MFP_MMC_CD_3_GPIO, GPIO_DIR_IN);		mhn_gpio_set_direction(MFP_MMC_WP_3_N_GPIO, GPIO_DIR_IN);		/* CD is configured to Falling/Rising Edge detect */		mhn_gpio_set_falling_edge_detect(MFP_MMC_CD_3_GPIO, 1);		mhn_gpio_set_rising_edge_detect (MFP_MMC_CD_3_GPIO, 1);		err = request_irq(MMC1_CD3, zylonite_detect_int, 0,			     "MMC card detect slot 3", data);		if (err) {			printk(KERN_ERR				"MMC/SD: can't request MMC card detect"				"IRQ for slot 3/n");			return -1;		}		set_irq_type(MMC1_CD3, IRQT_BOTHEDGE);	}#endif	return 0;}

static ssize_t max197_show_name(struct device *dev,				struct device_attribute *attr, char *buf){	struct platform_device *pdev = to_platform_device(dev);	return sprintf(buf, "%s/n", pdev->name);}