自学教程：C++ to_radeon_encoder函数代码示例

/* * update the N and CTS parameters for a given pixel clock rate */void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	uint32_t offset = dig->afmt->offset;	WREG32_P(HDMI0_ACR_32_0 + offset,		 HDMI0_ACR_CTS_32(acr.cts_32khz),		 ~HDMI0_ACR_CTS_32_MASK);	WREG32_P(HDMI0_ACR_32_1 + offset,		 HDMI0_ACR_N_32(acr.n_32khz),		 ~HDMI0_ACR_N_32_MASK);	WREG32_P(HDMI0_ACR_44_0 + offset,		 HDMI0_ACR_CTS_44(acr.cts_44_1khz),		 ~HDMI0_ACR_CTS_44_MASK);	WREG32_P(HDMI0_ACR_44_1 + offset,		 HDMI0_ACR_N_44(acr.n_44_1khz),		 ~HDMI0_ACR_N_44_MASK);	WREG32_P(HDMI0_ACR_48_0 + offset,		 HDMI0_ACR_CTS_48(acr.cts_48khz),		 ~HDMI0_ACR_CTS_48_MASK);	WREG32_P(HDMI0_ACR_48_1 + offset,		 HDMI0_ACR_N_48(acr.n_48khz),		 ~HDMI0_ACR_N_48_MASK);}

void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	if (!dig || !dig->afmt)		return;	/* Silent, r600_hdmi_enable will raise WARN for us */	if (enable && dig->afmt->enabled)		return;	if (!enable && !dig->afmt->enabled)		return;	if (!enable && dig->afmt->pin) {		radeon_audio_enable(rdev, dig->afmt->pin, 0);		dig->afmt->pin = NULL;	}	dig->afmt->enabled = enable;	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x/n",		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);}

void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	u32 base_rate = 48000;	if (!dig || !dig->afmt)		return;	/* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.	 * doesn't matter which one you use.  Just use the first one.	 */	/* XXX: properly calculate this */	/* XXX two dtos; generally use dto0 for hdmi */	/* Express [24MHz / target pixel clock] as an exact rational	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator	 */	if (ASIC_IS_DCE3(rdev)) {		/* according to the reg specs, this should DCE3.2 only, but in		 * practice it seems to cover DCE3.0 as well.		 */		WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50);		WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);		WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */	} else {		/* according to the reg specs, this should be DCE2.0 and DCE3.0 */		WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) |		       AUDIO_DTO_MODULE(clock * 100));	}}

/* * build a HDMI Video Info Frame */static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,					   void *buffer, size_t size){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	uint32_t offset = dig->afmt->offset;	uint8_t *frame = buffer + 3;	/* Our header values (type, version, length) should be alright, Intel	 * is using the same. Checksum function also seems to be OK, it works	 * fine for audio infoframe. However calculated value is always lower	 * by 2 in comparison to fglrx. It breaks displaying anything in case	 * of TVs that strictly check the checksum. Hack it manually here to	 * workaround this issue. */	frame[0x0] += 2;	WREG32(HDMI0_AVI_INFO0 + offset,		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));	WREG32(HDMI0_AVI_INFO1 + offset,		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));	WREG32(HDMI0_AVI_INFO2 + offset,		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));	WREG32(HDMI0_AVI_INFO3 + offset,		frame[0xC] | (frame[0xD] << 8));}

/* * enable the HDMI engine */void r600_hdmi_enable(struct drm_encoder *encoder){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	uint32_t offset;	u32 hdmi;	if (ASIC_IS_DCE6(rdev))		return;	/* Silent, r600_hdmi_enable will raise WARN for us */	if (dig->afmt->enabled)		return;	offset = dig->afmt->offset;	/* Older chipsets require setting HDMI and routing manually */	if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {		hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;		switch (radeon_encoder->encoder_id) {		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:			WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,				 ~AVIVO_TMDSA_CNTL_HDMI_EN);			hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);			break;		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:			WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,				 ~AVIVO_LVTMA_CNTL_HDMI_EN);			hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);			break;		case ENCODER_OBJECT_ID_INTERNAL_DDI:			WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN);			hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);			break;		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:			hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);			break;		default:			dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X/n",				radeon_encoder->encoder_id);			break;		}		WREG32(HDMI0_CONTROL + offset, hdmi);	}	if (rdev->irq.installed) {		/* if irq is available use it */		radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);	}	dig->afmt->enabled = true;	DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x/n",		  offset, radeon_encoder->encoder_id);}

/* * test if audio buffer is filled enough to start playing */static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	uint32_t offset = dig->afmt->offset;	return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;}

/** * r600_hdmi_update_audio_settings - Update audio infoframe * * @encoder: drm encoder * * Gets info about current audio stream and updates audio infoframe. */void r600_hdmi_update_audio_settings(struct drm_encoder *encoder){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	struct r600_audio_pin audio = r600_audio_status(rdev);	uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];	struct hdmi_audio_infoframe frame;	uint32_t offset;	uint32_t value;	ssize_t err;	if (!dig->afmt || !dig->afmt->enabled)		return;	offset = dig->afmt->offset;	DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,/n",		 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",		  audio.channels, audio.rate, audio.bits_per_sample);	DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code/n",		  (int)audio.status_bits, (int)audio.category_code);	err = hdmi_audio_infoframe_init(&frame);	if (err < 0) {		DRM_ERROR("failed to setup audio infoframe/n");		return;	}	frame.channels = audio.channels;	err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));	if (err < 0) {		DRM_ERROR("failed to pack audio infoframe/n");		return;	}	value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);	if (value & HDMI0_AUDIO_TEST_EN)		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,		       value & ~HDMI0_AUDIO_TEST_EN);	WREG32_OR(HDMI0_CONTROL + offset,		  HDMI0_ERROR_ACK);	WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,		   ~HDMI0_AUDIO_INFO_SOURCE);	r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,		  HDMI0_AUDIO_INFO_CONT |		  HDMI0_AUDIO_INFO_UPDATE);}

void evergreen_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	uint32_t offset;	if (!dig || !dig->afmt)		return;	offset = dig->afmt->offset;	if (enable) {		struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);		struct radeon_connector *radeon_connector = to_radeon_connector(connector);		struct radeon_connector_atom_dig *dig_connector;		uint32_t val;		if (dig->afmt->enabled)			return;		WREG32(EVERGREEN_DP_SEC_TIMESTAMP + offset, EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));		if (radeon_connector->con_priv) {			dig_connector = radeon_connector->con_priv;			val = RREG32(EVERGREEN_DP_SEC_AUD_N + offset);			val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);			if (dig_connector->dp_clock == 162000)				val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);			else				val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);			WREG32(EVERGREEN_DP_SEC_AUD_N + offset, val);		}		WREG32(EVERGREEN_DP_SEC_CNTL + offset,			EVERGREEN_DP_SEC_ASP_ENABLE |		/* Audio packet transmission */			EVERGREEN_DP_SEC_ATP_ENABLE |		/* Audio timestamp packet transmission */			EVERGREEN_DP_SEC_AIP_ENABLE |		/* Audio infoframe packet transmission */			EVERGREEN_DP_SEC_STREAM_ENABLE);	/* Master enable for secondary stream engine */		radeon_audio_enable(rdev, dig->afmt->pin, 0xf);	} else {		if (!dig->afmt->enabled)			return;		WREG32(EVERGREEN_DP_SEC_CNTL + offset, 0);		radeon_audio_enable(rdev, dig->afmt->pin, 0);	}	dig->afmt->enabled = enable;}

/* * disable the HDMI engine */void r600_hdmi_disable(struct drm_encoder *encoder){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	uint32_t offset;	if (ASIC_IS_DCE6(rdev))		return;	/* Called for ATOM_ENCODER_MODE_HDMI only */	if (!dig || !dig->afmt) {		return;	}	if (!dig->afmt->enabled)		return;	offset = dig->afmt->offset;	DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x/n",		  offset, radeon_encoder->encoder_id);	/* disable irq */	radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);	/* Older chipsets not handled by AtomBIOS */	if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {		switch (radeon_encoder->encoder_id) {		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:			WREG32_P(AVIVO_TMDSA_CNTL, 0,				 ~AVIVO_TMDSA_CNTL_HDMI_EN);			break;		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:			WREG32_P(AVIVO_LVTMA_CNTL, 0,				 ~AVIVO_LVTMA_CNTL_HDMI_EN);			break;		case ENCODER_OBJECT_ID_INTERNAL_DDI:			WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);			break;		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:			break;		default:			dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X/n",				radeon_encoder->encoder_id);			break;		}		WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK);	}	dig->afmt->enabled = false;}

static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info){	struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	u8 tmp;	/* power up the sink */	if (dp_info->dpcd[0] >= 0x11) {		radeon_write_dpcd_reg(dp_info->radeon_connector,				      DP_SET_POWER, DP_SET_POWER_D0);		usleep_range(1000, 2000);	}	/* possibly enable downspread on the sink */	if (dp_info->dpcd[3] & 0x1)		radeon_write_dpcd_reg(dp_info->radeon_connector,				      DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);	else		radeon_write_dpcd_reg(dp_info->radeon_connector,				      DP_DOWNSPREAD_CTRL, 0);	if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&	    (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {		radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);	}	/* set the lane count on the sink */	tmp = dp_info->dp_lane_count;	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))		tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;	radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);	/* set the link rate on the sink */	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);	radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);	/* start training on the source */	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)		atombios_dig_encoder_setup(dp_info->encoder,					   ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);	else		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,					  dp_info->dp_clock, dp_info->enc_id, 0);	/* disable the training pattern on the sink */	radeon_write_dpcd_reg(dp_info->radeon_connector,			      DP_TRAINING_PATTERN_SET,			      DP_TRAINING_PATTERN_DISABLE);	return 0;}

void evergreen_dp_enable(struct drm_encoder *encoder, bool enable){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);	if (!dig || !dig->afmt)		return;	if (enable && drm_detect_monitor_audio(radeon_connector_edid(connector))) {		struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);		struct radeon_connector *radeon_connector = to_radeon_connector(connector);		struct radeon_connector_atom_dig *dig_connector;		uint32_t val;		WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,			  AFMT_AUDIO_SAMPLE_SEND);		WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,		       EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));		if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) {			dig_connector = radeon_connector->con_priv;			val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);			val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);			if (dig_connector->dp_clock == 162000)				val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);			else				val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);			WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);		}		WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,			EVERGREEN_DP_SEC_ASP_ENABLE |		/* Audio packet transmission */			EVERGREEN_DP_SEC_ATP_ENABLE |		/* Audio timestamp packet transmission */			EVERGREEN_DP_SEC_AIP_ENABLE |		/* Audio infoframe packet transmission */			EVERGREEN_DP_SEC_STREAM_ENABLE);	/* Master enable for secondary stream engine */	} else {		WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);		WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,			   ~AFMT_AUDIO_SAMPLE_SEND);	}	dig->afmt->enabled = enable;}

/* * have buffer status changed since last call? */int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder){	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	int status, result;	if (!dig->afmt || !dig->afmt->enabled)		return 0;	status = r600_hdmi_is_audio_buffer_filled(encoder);	result = dig->afmt->last_buffer_filled_status != status;	dig->afmt->last_buffer_filled_status = status;	return result;}

/* * build a Audio Info Frame */static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,					     const void *buffer, size_t size){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	uint32_t offset = dig->afmt->offset;	const u8 *frame = buffer + 3;	WREG32(HDMI0_AUDIO_INFO0 + offset,		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));	WREG32(HDMI0_AUDIO_INFO1 + offset,		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));}

/* * write the audio workaround status to the hardware */static void r600_hdmi_audio_workaround(struct drm_encoder *encoder){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	uint32_t offset = dig->afmt->offset;	bool hdmi_audio_workaround = false; /* FIXME */	u32 value;	if (!hdmi_audio_workaround ||	    r600_hdmi_is_audio_buffer_filled(encoder))		value = 0; /* disable workaround */	else		value = HDMI0_AUDIO_TEST_EN; /* enable workaround */	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,		 value, ~HDMI0_AUDIO_TEST_EN);}

/* * build a HDMI Video Info Frame */void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,				    size_t size){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	uint32_t offset = dig->afmt->offset;	uint8_t *frame = (uint8_t*)buffer + 3;	uint8_t *header = buffer;	WREG32(HDMI0_AVI_INFO0 + offset,		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));	WREG32(HDMI0_AVI_INFO1 + offset,		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));	WREG32(HDMI0_AVI_INFO2 + offset,		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));	WREG32(HDMI0_AVI_INFO3 + offset,		frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));}

void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	if (!dig || !dig->afmt)		return;	if (enable) {		struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);		if (drm_detect_monitor_audio(radeon_connector_edid(connector))) {			WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,			       HDMI_AVI_INFO_SEND | /* enable AVI info frames */			       HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */			       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */			       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */			WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,				  AFMT_AUDIO_SAMPLE_SEND);		} else {			WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,			       HDMI_AVI_INFO_SEND | /* enable AVI info frames */			       HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */			WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,				   ~AFMT_AUDIO_SAMPLE_SEND);		}	} else {		WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,			   ~AFMT_AUDIO_SAMPLE_SEND);		WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);	}	dig->afmt->enabled = enable;	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x/n",		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);}

/* * update settings with current parameters from audio engine */void r600_hdmi_update_audio_settings(struct drm_encoder *encoder){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	struct r600_audio audio = r600_audio_status(rdev);	uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];	struct hdmi_audio_infoframe frame;	uint32_t offset;	uint32_t iec;	ssize_t err;	if (!dig->afmt || !dig->afmt->enabled)		return;	offset = dig->afmt->offset;	DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,/n",		 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",		  audio.channels, audio.rate, audio.bits_per_sample);	DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code/n",		  (int)audio.status_bits, (int)audio.category_code);	iec = 0;	if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)		iec |= 1 << 0;	if (audio.status_bits & AUDIO_STATUS_NONAUDIO)		iec |= 1 << 1;	if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)		iec |= 1 << 2;	if (audio.status_bits & AUDIO_STATUS_EMPHASIS)		iec |= 1 << 3;	iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);	switch (audio.rate) {	case 32000:		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);		break;	case 44100:		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);		break;	case 48000:		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);		break;	case 88200:		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);		break;	case 96000:		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);		break;	case 176400:		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);		break;	case 192000:		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);		break;	}	WREG32(HDMI0_60958_0 + offset, iec);	iec = 0;	switch (audio.bits_per_sample) {	case 16:		iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);		break;	case 20:		iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);		break;	case 24:		iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);		break;	}	if (audio.status_bits & AUDIO_STATUS_V)		iec |= 0x5 << 16;	WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);	err = hdmi_audio_infoframe_init(&frame);	if (err < 0) {		DRM_ERROR("failed to setup audio infoframe/n");		return;	}	frame.channels = audio.channels;	err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));	if (err < 0) {		DRM_ERROR("failed to pack audio infoframe/n");		return;	}	r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));	r600_hdmi_audio_workaround(encoder);}

/* * update the info frames with the data from the current display mode */void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];	struct hdmi_avi_infoframe frame;	uint32_t offset;	ssize_t err;	/* Silent, r600_hdmi_enable will raise WARN for us */	if (!dig->afmt->enabled)		return;	offset = dig->afmt->offset;	r600_audio_set_clock(encoder, mode->clock);	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,	       HDMI0_NULL_SEND); /* send null packets when required */	WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);	if (ASIC_IS_DCE32(rdev)) {		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */		       HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */		WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,		       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */		       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */	} else {		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,		       HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */		       HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */		       HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */	}	WREG32(HDMI0_ACR_PACKET_CONTROL + offset,	       HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */	       HDMI0_ACR_SOURCE); /* select SW CTS value */	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,	       HDMI0_NULL_SEND | /* send null packets when required */	       HDMI0_GC_SEND | /* send general control packets */	       HDMI0_GC_CONT); /* send general control packets every frame */	/* TODO: HDMI0_AUDIO_INFO_UPDATE */	WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,	       HDMI0_AVI_INFO_SEND | /* enable AVI info frames */	       HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */	       HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */	       HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */	WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,	       HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */	       HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */	WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);	if (err < 0) {		DRM_ERROR("failed to setup AVI infoframe: %zd/n", err);		return;	}	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));	if (err < 0) {		DRM_ERROR("failed to pack AVI infoframe: %zd/n", err);		return;	}	r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));	r600_hdmi_update_ACR(encoder, mode->clock);	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */	WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);	WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);	WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);	WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);	r600_hdmi_audio_workaround(encoder);}

void radeon_dp_link_train(struct drm_encoder *encoder,			  struct drm_connector *connector){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig;	struct radeon_connector *radeon_connector;	struct radeon_connector_atom_dig *dig_connector;	struct radeon_dp_link_train_info dp_info;	int index;	u8 tmp, frev, crev;	if (!radeon_encoder->enc_priv)		return;	dig = radeon_encoder->enc_priv;	radeon_connector = to_radeon_connector(connector);	if (!radeon_connector->con_priv)		return;	dig_connector = radeon_connector->con_priv;	if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&	    (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))		return;	/* DPEncoderService newer than 1.1 can't program properly the	 * training pattern. When facing such version use the	 * DIGXEncoderControl (X== 1 | 2)	 */	dp_info.use_dpencoder = true;	index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);	if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {		if (crev > 1) {			dp_info.use_dpencoder = false;		}	}	dp_info.enc_id = 0;	if (dig->dig_encoder)		dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;	else		dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;	if (dig->linkb)		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;	else		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;	tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);	if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))		dp_info.tp3_supported = true;	else		dp_info.tp3_supported = false;	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);	dp_info.rdev = rdev;	dp_info.encoder = encoder;	dp_info.connector = connector;	dp_info.radeon_connector = radeon_connector;	dp_info.dp_lane_count = dig_connector->dp_lane_count;	dp_info.dp_clock = dig_connector->dp_clock;	if (radeon_dp_link_train_init(&dp_info))		goto done;	if (radeon_dp_link_train_cr(&dp_info))		goto done;	if (radeon_dp_link_train_ce(&dp_info))		goto done;done:	if (radeon_dp_link_train_finish(&dp_info))		return;}

/* * enable the HDMI engine */void r600_hdmi_enable(struct drm_encoder *encoder, bool enable){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	u32 hdmi = HDMI0_ERROR_ACK;	if (!dig || !dig->afmt)		return;	/* Silent, r600_hdmi_enable will raise WARN for us */	if (enable && dig->afmt->enabled)		return;	if (!enable && !dig->afmt->enabled)		return;	/* Older chipsets require setting HDMI and routing manually */	if (!ASIC_IS_DCE3(rdev)) {		if (enable)			hdmi |= HDMI0_ENABLE;		switch (radeon_encoder->encoder_id) {		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:			if (enable) {				WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);				hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);			} else {				WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);			}			break;		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:			if (enable) {				WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);				hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);			} else {				WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);			}			break;		case ENCODER_OBJECT_ID_INTERNAL_DDI:			if (enable) {				WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);				hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);			} else {				WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);			}			break;		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:			if (enable)				hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);			break;		default:			dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X/n",				radeon_encoder->encoder_id);			break;		}		WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);	}	if (rdev->irq.installed) {		/* if irq is available use it */		/* XXX: shouldn't need this on any asics.  Double check DCE2/3 */		if (enable)			radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);		else			radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);	}	dig->afmt->enabled = enable;	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x/n",		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);}

/* * update the info frames with the data from the current display mode */void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];	struct hdmi_avi_infoframe frame;	uint32_t offset;	uint32_t acr_ctl;	ssize_t err;	if (!dig || !dig->afmt)		return;	/* Silent, r600_hdmi_enable will raise WARN for us */	if (!dig->afmt->enabled)		return;	offset = dig->afmt->offset;	/* disable audio prior to setting up hw */	dig->afmt->pin = r600_audio_get_pin(rdev);	r600_audio_enable(rdev, dig->afmt->pin, false);	r600_audio_set_dto(encoder, mode->clock);	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,		 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */		 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */		 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */		 HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */		 ~(HDMI0_AUDIO_SAMPLE_SEND |		   HDMI0_AUDIO_DELAY_EN_MASK |		   HDMI0_AUDIO_PACKETS_PER_LINE_MASK |		   HDMI0_60958_CS_UPDATE));	/* DCE 3.0 uses register that's normally for CRC_CONTROL */	acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :				       HDMI0_ACR_PACKET_CONTROL;	WREG32_P(acr_ctl + offset,		 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */		 HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */		 ~(HDMI0_ACR_SOURCE |		   HDMI0_ACR_AUTO_SEND));	WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,		  HDMI0_NULL_SEND | /* send null packets when required */		  HDMI0_GC_SEND | /* send general control packets */		  HDMI0_GC_CONT); /* send general control packets every frame */	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,		  HDMI0_AVI_INFO_SEND | /* enable AVI info frames */		  HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */		  HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */		  HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */	WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,		 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */		 HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */		 ~(HDMI0_AVI_INFO_LINE_MASK |		   HDMI0_AUDIO_INFO_LINE_MASK));	WREG32_AND(HDMI0_GC + offset,		   ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);	if (err < 0) {		DRM_ERROR("failed to setup AVI infoframe: %zd/n", err);		return;	}	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));	if (err < 0) {		DRM_ERROR("failed to pack AVI infoframe: %zd/n", err);		return;	}	r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));	/* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */	WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,		   ~(HDMI0_GENERIC0_SEND |		     HDMI0_GENERIC0_CONT |		     HDMI0_GENERIC0_UPDATE |		     HDMI0_GENERIC1_SEND |		     HDMI0_GENERIC1_CONT |		     HDMI0_GENERIC0_LINE_MASK |		     HDMI0_GENERIC1_LINE_MASK));	r600_hdmi_update_ACR(encoder, mode->clock);	WREG32_P(HDMI0_60958_0 + offset,		 HDMI0_60958_CS_CHANNEL_NUMBER_L(1),		 ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |		   HDMI0_60958_CS_CLOCK_ACCURACY_MASK));//.........这里部分代码省略.........

void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock){	struct drm_device *dev = encoder->dev;	struct radeon_device *rdev = dev->dev_private;	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;	u32 base_rate = 24000;	u32 max_ratio = clock / base_rate;	u32 dto_phase;	u32 dto_modulo = clock;	u32 wallclock_ratio;	u32 dto_cntl;	if (!dig || !dig->afmt)		return;	if (max_ratio >= 8) {		dto_phase = 192 * 1000;		wallclock_ratio = 3;	} else if (max_ratio >= 4) {		dto_phase = 96 * 1000;		wallclock_ratio = 2;	} else if (max_ratio >= 2) {		dto_phase = 48 * 1000;		wallclock_ratio = 1;	} else {		dto_phase = 24 * 1000;		wallclock_ratio = 0;	}	/* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.	 * doesn't matter which one you use.  Just use the first one.	 */	/* XXX two dtos; generally use dto0 for hdmi */	/* Express [24MHz / target pixel clock] as an exact rational	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator	 */	if (ASIC_IS_DCE32(rdev)) {		if (dig->dig_encoder == 0) {			dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;			dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);			WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);			WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);			WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);			WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */		} else {			dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;			dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);			WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);			WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);			WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);			WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */		}	} else {		/* according to the reg specs, this should DCE3.2 only, but in		 * practice it seems to cover DCE2.0/3.0/3.1 as well.		 */		if (dig->dig_encoder == 0) {			WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);			WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);			WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */		} else {			WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);			WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);			WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */		}	}}