自学教程：C++ uart_barrier函数代码示例

static intoct16550_delay (struct uart_bas *bas){	int divisor;	u_char lcr;        static int delay = 0;        if (!delay_changed) return delay;        delay_changed = 0;	lcr = uart_getreg(bas, REG_LCR);	uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);	uart_barrier(bas);	divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);	uart_barrier(bas);	uart_setreg(bas, REG_LCR, lcr);	uart_barrier(bas);		if(!bas->rclk)		return 10; /* return an approx delay value */	/* 1/10th the time to transmit 1 character (estimate). */	if (divisor <= 134)		return (16000000 * divisor / bas->rclk);	return (16000 * divisor / (bas->rclk / 1000));}

/* * Write the current transmit buffer to the TX FIFO.  */static intmsm_bus_transmit(struct uart_softc *sc){	struct msm_uart_softc *u = (struct msm_uart_softc *)sc;	struct uart_bas *bas = &sc->sc_bas;	int i;	uart_lock(sc->sc_hwmtx);	/* Write some data */	for (i = 0; i < sc->sc_txdatasz; i++) {		/* Write TX data */		msm_putc(bas, sc->sc_txbuf[i]);		uart_barrier(bas);	}	/* TX FIFO is empty now, enable TX_READY interrupt */	u->ier |= UART_DM_TX_READY;	SETREG(bas, UART_DM_IMR, u->ier);	uart_barrier(bas);	/*	 * Inform upper layer that it is transmitting data to hardware,	 * this will be cleared when TXIDLE interrupt occurs.	 */	sc->sc_txbusy = 1;	uart_unlock(sc->sc_hwmtx);	return (0);}

static intmsm_bus_ipend(struct uart_softc *sc){	struct msm_uart_softc *u = (struct msm_uart_softc *)sc;	struct uart_bas *bas = &sc->sc_bas;	uint32_t isr;	int ipend;	uart_lock(sc->sc_hwmtx);	/* Get ISR status */	isr = GETREG(bas, UART_DM_MISR);	ipend = 0;	/* Uart RX starting, notify upper layer */	if (isr & UART_DM_RXLEV) {		u->ier &= ~UART_DM_RXLEV;		SETREG(bas, UART_DM_IMR, u->ier);		uart_barrier(bas);		ipend |= SER_INT_RXREADY;	}	/* Stale RX interrupt */	if (isr & UART_DM_RXSTALE) {		/* Disable and reset it */		SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_DISABLE);		SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);		uart_barrier(bas);		ipend |= SER_INT_RXREADY;	}	/* TX READY interrupt */	if (isr & UART_DM_TX_READY) {		/* Clear  TX Ready */		SETREG(bas, UART_DM_CR, UART_DM_CLEAR_TX_READY);		/* Disable TX_READY */		u->ier &= ~UART_DM_TX_READY;		SETREG(bas, UART_DM_IMR, u->ier);		uart_barrier(bas);		if (sc->sc_txbusy != 0)			ipend |= SER_INT_TXIDLE;	}	if (isr & UART_DM_TXLEV) {		/* TX FIFO is empty */		u->ier &= ~UART_DM_TXLEV;		SETREG(bas, UART_DM_IMR, u->ier);		uart_barrier(bas);		if (sc->sc_txbusy != 0)			ipend |= SER_INT_TXIDLE;	}	uart_unlock(sc->sc_hwmtx);	return (ipend);}

static intz8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,    int parity, uint8_t *tpcp){	int divisor;	uint8_t mpm, rpc, tpc;	rpc = RPC_RXE;	mpm = MPM_CM16;	tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS));	if (databits >= 8) {		rpc |= RPC_RB8;		tpc |= TPC_TB8;	} else if (databits == 7) {		rpc |= RPC_RB7;		tpc |= TPC_TB7;	} else if (databits == 6) {		rpc |= RPC_RB6;		tpc |= TPC_TB6;	} else {		rpc |= RPC_RB5;		tpc |= TPC_TB5;	}	mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1;	switch (parity) {	case UART_PARITY_EVEN:	mpm |= MPM_PE | MPM_EVEN; break;	case UART_PARITY_NONE:	break;	case UART_PARITY_ODD:	mpm |= MPM_PE; break;	default:		return (EINVAL);	}	if (baudrate > 0) {		divisor = z8530_divisor(bas->rclk, baudrate);		if (divisor == -1)			return (EINVAL);	} else		divisor = -1;	uart_setmreg(bas, WR_MCB2, UART_PCLK);	uart_barrier(bas);	if (divisor >= 0) {		uart_setmreg(bas, WR_TCL, divisor & 0xff);		uart_barrier(bas);		uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);		uart_barrier(bas);	}

static intsa1110_bus_transmit(struct uart_softc *sc){	int i;#if 0	int sr = uart_getreg(&sc->sc_bas, SACOM_SR0);	while (!(uart_getreg(&sc->sc_bas, SACOM_CR3) & CR3_TIE))		uart_setreg(&sc->sc_bas, SACOM_CR3,		    uart_getreg(&sc->sc_bas, SACOM_CR3) | CR3_TIE);    #endif	sc->sc_txbusy = 1;	uart_setreg(&sc->sc_bas, SACOM_CR3, uart_getreg(&sc->sc_bas, SACOM_CR3)	    | CR3_TIE);    	for (i = 0; i < sc->sc_txdatasz; i++) {		while (!(uart_getreg(&sc->sc_bas, SACOM_SR1) & SR1_TNF));		uart_setreg(&sc->sc_bas, SACOM_DR, sc->sc_txbuf[i]);		uart_barrier(&sc->sc_bas);	}#if 0	sr = uart_getreg(&sc->sc_bas, SACOM_SR0);#endif	return (0);}

static intmsm_bus_receive(struct uart_softc *sc){	struct msm_uart_softc *u = (struct msm_uart_softc *)sc;	struct uart_bas *bas;	int c;	bas = &sc->sc_bas;	uart_lock(sc->sc_hwmtx);	/* Initialize Receive Path and interrupt */	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);	SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_ENABLE);	u->ier |= UART_DM_RXLEV;	SETREG(bas, UART_DM_IMR, u->ier);	/* Loop over until we are full, or no data is available */	while (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) {		if (uart_rx_full(sc)) {			/* No space left in input buffer */			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;			break;		}		/* Read RX FIFO */		c = uart_getreg(bas, UART_DM_RF(0));		uart_barrier(bas);		uart_rx_put(sc, c);	}	uart_unlock(sc->sc_hwmtx);	return (0);}

static __inline uint8_tuart_getmreg(struct uart_bas *bas, int reg){	uart_setreg(bas, REG_CTRL, reg);	uart_barrier(bas);	return (uart_getreg(bas, REG_CTRL));}

/* Multiplexed I/O. */static __inline voiduart_setmreg(struct uart_bas *bas, int reg, int val){	uart_setreg(bas, REG_CTRL, reg);	uart_barrier(bas);	uart_setreg(bas, REG_CTRL, val);}

static voidmtk_uart_putc(struct uart_bas *bas, int c){	char chr;	if (!uart_output) return;	chr = c;	while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));	uart_setreg(bas, UART_TX_REG, c);	uart_barrier(bas);	while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));}

static voidmtk_uart_init(struct uart_bas *bas, int baudrate, int databits,    int stopbits, int parity){        /* CLKDIV  = 384000000/ 3/ 16/ br */        /* for 384MHz CLKDIV = 8000000 / baudrate; */        switch (databits) {        case 5:    		databits = UART_LCR_5B;    		break;        case 6:    		databits = UART_LCR_6B;    		break;        case 7:    		databits = UART_LCR_7B;    		break;        case 8:    		databits = UART_LCR_8B;    		break;    	default:    		/* Unsupported */    		return;        }	switch (parity) {	case UART_PARITY_EVEN:	parity = (UART_LCR_PEN|UART_LCR_EVEN); break;	case UART_PARITY_ODD:	parity = (UART_LCR_PEN); break;	case UART_PARITY_NONE:	parity = 0; break;	/* Unsupported */	default:		return;	}	if (bas->rclk && baudrate) {        	uart_setreg(bas, UART_CDDL_REG, bas->rclk/16/baudrate);		uart_barrier(bas);	}        uart_setreg(bas, UART_LCR_REG, databits |				(stopbits==1?0:UART_LCR_STB_15) |       			 	parity);	uart_barrier(bas);}

static voidadm5120_uart_putc(struct uart_bas *bas, int c){	char chr;	chr = c;	while (uart_getreg(bas, UART_FR_REG) & UART_FR_TX_FIFO_FULL)		;	uart_setreg(bas, UART_DR_REG, c);	while (uart_getreg(bas, UART_FR_REG) & UART_FR_BUSY)		;	uart_barrier(bas);}

static voidmsm_bus_ungrab(struct uart_softc *sc){	struct msm_uart_softc *u = (struct msm_uart_softc *)sc;	struct uart_bas *bas = &sc->sc_bas;	/*	 * Restore previous interrupt mask	 */	uart_lock(sc->sc_hwmtx);	SETREG(bas, UART_DM_IMR, u->ier);	uart_barrier(bas);	uart_unlock(sc->sc_hwmtx);}

static voidmsm_bus_grab(struct uart_softc *sc){	struct uart_bas *bas = &sc->sc_bas;	/*	 * XXX: Turn off all interrupts to enter polling mode. Leave the	 * saved mask alone. We'll restore whatever it was in ungrab.	 */	uart_lock(sc->sc_hwmtx);	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);	SETREG(bas, UART_DM_IMR, 0);	uart_barrier(bas);	uart_unlock(sc->sc_hwmtx);}

/* * Clear pending interrupts. THRE is cleared by reading IIR. Data * that may have been received gets lost here. */static voidoct16550_clrint (struct uart_bas *bas){	uint8_t iir;	iir = uart_getreg(bas, REG_IIR);	while ((iir & IIR_NOPEND) == 0) {		iir &= IIR_IMASK;		if (iir == IIR_RLS)			(void)uart_getreg(bas, REG_LSR);		else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)			(void)uart_getreg(bas, REG_DATA);		else if (iir == IIR_MLSC)			(void)uart_getreg(bas, REG_MSR);                else if (iir == IIR_BUSY)                    	(void) uart_getreg(bas, REG_USR);		uart_barrier(bas);		iir = uart_getreg(bas, REG_IIR);	}}

static intjz4780_bus_attach(struct uart_softc *sc){    struct ns8250_softc *ns8250;    struct uart_bas *bas;    int rv;    ns8250 = (struct ns8250_softc *)sc;    bas = &sc->sc_bas;    rv = ns8250_bus_attach(sc);    if (rv != 0)        return (0);    /* Configure uart to use extra IER_RXTMOUT bit */    ns8250->ier_rxbits = IER_RXTMOUT | IER_EMSC | IER_ERLS | IER_ERXRDY;    ns8250->ier_mask = ~(ns8250->ier_rxbits);    ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;    ns8250->ier |= ns8250->ier_rxbits;    uart_setreg(bas, REG_IER, ns8250->ier);    uart_barrier(bas);    return (0);}

static intexynos4210_bus_transmit(struct uart_softc *sc){	int i;	int reg;	uart_lock(sc->sc_hwmtx);	for (i = 0; i < sc->sc_txdatasz; i++) {		exynos4210_putc(&sc->sc_bas, sc->sc_txbuf[i]);		uart_barrier(&sc->sc_bas);	}	sc->sc_txbusy = 1;	uart_unlock(sc->sc_hwmtx);	/* unmask TX interrupt */	reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTM);	reg &= ~(1 << 2);	bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTM, reg);	return (0);}

static intmsm_uart_param(struct uart_bas *bas, int baudrate, int databits,    int stopbits, int parity){	int ulcon;	ulcon = 0;	switch (databits) {	case 5:		ulcon |= (UART_DM_5_BPS << 4);		break;	case 6:		ulcon |= (UART_DM_6_BPS << 4);		break;	case 7:		ulcon |= (UART_DM_7_BPS << 4);		break;	case 8:		ulcon |= (UART_DM_8_BPS << 4);		break;	default:		return (EINVAL);	}	switch (parity) {	case UART_PARITY_NONE:		ulcon |= UART_DM_NO_PARITY;		break;	case UART_PARITY_ODD:		ulcon |= UART_DM_ODD_PARITY;		break;	case UART_PARITY_EVEN:		ulcon |= UART_DM_EVEN_PARITY;		break;	case UART_PARITY_SPACE:		ulcon |= UART_DM_SPACE_PARITY;		break;	case UART_PARITY_MARK:	default:		return (EINVAL);	}	switch (stopbits) {	case 1:		ulcon |= (UART_DM_SBL_1 << 2);		break;	case 2:		ulcon |= (UART_DM_SBL_2 << 2);		break;	default:		return (EINVAL);	}	uart_setreg(bas, UART_DM_MR2, ulcon);	/* Set 115200 for both TX and RX. */;	uart_setreg(bas, UART_DM_CSR, UART_DM_CSR_115200);	uart_barrier(bas);	return (0);}

static voidmsm_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,    int parity){	if (bas->rclk == 0)		bas->rclk = DEF_CLK;	KASSERT(bas->rclk != 0, ("msm_init: Invalid rclk"));	/* Set default parameters */	msm_uart_param(bas, baudrate, databits, stopbits, parity);	/*	 * Configure UART mode registers MR1 and MR2.	 * Hardware flow control isn't supported.	 */	uart_setreg(bas, UART_DM_MR1, 0x0);	/* Reset interrupt mask register. */	uart_setreg(bas, UART_DM_IMR, 0);	/*	 * Configure Tx and Rx watermarks configuration registers.	 * TX watermark value is set to 0 - interrupt is generated when	 * FIFO level is less than or equal to 0.	 */	uart_setreg(bas, UART_DM_TFWR, UART_DM_TFW_VALUE);	/* Set RX watermark value */	uart_setreg(bas, UART_DM_RFWR, UART_DM_RFW_VALUE);	/*	 * Configure Interrupt Programming Register.	 * Set initial Stale timeout value.	 */	uart_setreg(bas, UART_DM_IPR, UART_DM_STALE_TIMEOUT_LSB);	/* Disable IRDA mode */	uart_setreg(bas, UART_DM_IRDA, 0x0);	/*	 * Configure and enable sim interface if required.	 * Configure hunt character value in HCR register.	 * Keep it in reset state.	 */	uart_setreg(bas, UART_DM_HCR, 0x0);	/* Issue soft reset command */	SETREG(bas, UART_DM_CR, UART_DM_RESET_TX);	SETREG(bas, UART_DM_CR, UART_DM_RESET_RX);	SETREG(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);	SETREG(bas, UART_DM_CR, UART_DM_RESET_BREAK_INT);	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);	/* Enable/Disable Rx/Tx DM interfaces */	/* Disable Data Mover for now. */	uart_setreg(bas, UART_DM_DMEN, 0x0);	/* Enable transmitter and receiver */	uart_setreg(bas, UART_DM_CR, UART_DM_CR_RX_ENABLE);	uart_setreg(bas, UART_DM_CR, UART_DM_CR_TX_ENABLE);	uart_barrier(bas);}