自学教程：C++ uart_getreg函数代码示例

static voidmsm_putc(struct uart_bas *bas, int c){	int limit;	/*	 * Write to NO_CHARS_FOR_TX register the number of characters	 * to be transmitted. However, before writing TX_FIFO must	 * be empty as indicated by TX_READY interrupt in IMR register	 */	/*	 * Check if transmit FIFO is empty.	 * If not wait for TX_READY interrupt.	 */	limit = 1000;	if (!(uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXEMT)) {		while ((uart_getreg(bas, UART_DM_ISR) & UART_DM_TX_READY) == 0		    && --limit)			DELAY(4);	}	/* FIFO is ready, write number of characters to be written */	uart_setreg(bas, UART_DM_NO_CHARS_FOR_TX, 1);	/* Wait till TX FIFO has space */	while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXRDY) == 0)		DELAY(4);	/* TX FIFO has space. Write char */	SETREG(bas, UART_DM_TF(0), (c & 0xff));}

static intmsm_bus_receive(struct uart_softc *sc){	struct msm_uart_softc *u = (struct msm_uart_softc *)sc;	struct uart_bas *bas;	int c;	bas = &sc->sc_bas;	uart_lock(sc->sc_hwmtx);	/* Initialize Receive Path and interrupt */	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);	SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_ENABLE);	u->ier |= UART_DM_RXLEV;	SETREG(bas, UART_DM_IMR, u->ier);	/* Loop over until we are full, or no data is available */	while (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) {		if (uart_rx_full(sc)) {			/* No space left in input buffer */			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;			break;		}		/* Read RX FIFO */		c = uart_getreg(bas, UART_DM_RF(0));		uart_barrier(bas);		uart_rx_put(sc, c);	}	uart_unlock(sc->sc_hwmtx);	return (0);}

static intoct16550_delay (struct uart_bas *bas){	int divisor;	u_char lcr;        static int delay = 0;        if (!delay_changed) return delay;        delay_changed = 0;	lcr = uart_getreg(bas, REG_LCR);	uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);	uart_barrier(bas);	divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);	uart_barrier(bas);	uart_setreg(bas, REG_LCR, lcr);	uart_barrier(bas);		if(!bas->rclk)		return 10; /* return an approx delay value */	/* 1/10th the time to transmit 1 character (estimate). */	if (divisor <= 134)		return (16000000 * divisor / bas->rclk);	return (16000 * divisor / (bas->rclk / 1000));}

static voidmtk_uart_putc(struct uart_bas *bas, int c){	char chr;	if (!uart_output) return;	chr = c;	while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));	uart_setreg(bas, UART_TX_REG, c);	uart_barrier(bas);	while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));}

static voidadm5120_uart_putc(struct uart_bas *bas, int c){	char chr;	chr = c;	while (uart_getreg(bas, UART_FR_REG) & UART_FR_TX_FIFO_FULL)		;	uart_setreg(bas, UART_DR_REG, c);	while (uart_getreg(bas, UART_FR_REG) & UART_FR_BUSY)		;	uart_barrier(bas);}

static intmtk_uart_rxready(struct uart_bas *bas){	if (uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)		return (1);	return (0);}

static intexynos4210_rxready(struct uart_bas *bas){	return ((uart_getreg(bas, SSCOM_UTRSTAT) & UTRSTAT_RXREADY) ==	    UTRSTAT_RXREADY);}

static __inline uint8_tuart_getmreg(struct uart_bas *bas, int reg){	uart_setreg(bas, REG_CTRL, reg);	uart_barrier(bas);	return (uart_getreg(bas, REG_CTRL));}

static intmsm_rxready(struct uart_bas *bas){	/* Wait for a character to come ready */	return ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) ==	    UART_DM_SR_RXRDY);}

static intadm5120_uart_rxready(struct uart_bas *bas){	if (uart_getreg(bas, UART_FR_REG) & UART_FR_RX_FIFO_EMPTY)		return (0);	return (1);}

static intsa1110_getc(struct uart_bas *bas, struct mtx *mtx){	int c;	while (!(uart_getreg(bas, SACOM_SR1) & SR1_RNE)) {		u_int32_t sr0;		sr0 = uart_getreg(bas, SACOM_SR0);		if (ISSET(sr0, SR0_RBB))			uart_setreg(bas, SACOM_SR0, SR0_RBB);		if (ISSET(sr0, SR0_REB))			uart_setreg(bas, SACOM_SR0, SR0_REB);	}	c = uart_getreg(bas, SACOM_DR);	c &= 0xff;	return (c);}

static intadm5120_uart_getc(struct uart_bas *bas, struct mtx *hwmtx){	int c;	uart_lock(hwmtx);	while (uart_getreg(bas, UART_FR_REG) & UART_FR_RX_FIFO_EMPTY) {		uart_unlock(hwmtx);		DELAY(10);		uart_lock(hwmtx);	}	c = uart_getreg(bas, UART_DR_REG);	uart_unlock(hwmtx);	return (c);}

static intmtk_uart_getc(struct uart_bas *bas, struct mtx *hwmtx){	int c;	uart_lock(hwmtx);	while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)) {		uart_unlock(hwmtx);		DELAY(10);		uart_lock(hwmtx);	}	c = uart_getreg(bas, UART_RX_REG);	uart_unlock(hwmtx);	return (c);}

static intrt305x_uart_rxready(struct uart_bas *bas){#ifdef notyet	if (uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)		return (1);	return (0);#else	return (1);#endif}

static intsa1110_bus_receive(struct uart_softc *sc){	#if 0	while (!(uart_getreg(&sc->sc_bas, SACOM_SR1) & SR1_RNE)) {		u_int32_t sr0;		sr0 = uart_getreg(&sc->sc_bas, SACOM_SR0);		if (ISSET(sr0, SR0_RBB))			uart_setreg(&sc->sc_bas, SACOM_SR0, SR0_RBB);		if (ISSET(sr0, SR0_REB))			uart_setreg(&sc->sc_bas, SACOM_SR0, SR0_REB);	}#endif		uart_setreg(&sc->sc_bas, SACOM_CR3, uart_getreg(&sc->sc_bas, SACOM_CR3)	    | CR3_RIE);	uart_rx_put(sc, uart_getreg(&sc->sc_bas, SACOM_DR));	return (0);}

static intexynos4210_bus_receive(struct uart_softc *sc){	struct uart_bas *bas;	bas = &sc->sc_bas;	while (bus_space_read_4(bas->bst, bas->bsh,		SSCOM_UFSTAT) & UFSTAT_RXCOUNT)		uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH));	return (0);}

static intsa1110_bus_transmit(struct uart_softc *sc){	int i;#if 0	int sr = uart_getreg(&sc->sc_bas, SACOM_SR0);	while (!(uart_getreg(&sc->sc_bas, SACOM_CR3) & CR3_TIE))		uart_setreg(&sc->sc_bas, SACOM_CR3,		    uart_getreg(&sc->sc_bas, SACOM_CR3) | CR3_TIE);    #endif	sc->sc_txbusy = 1;	uart_setreg(&sc->sc_bas, SACOM_CR3, uart_getreg(&sc->sc_bas, SACOM_CR3)	    | CR3_TIE);    	for (i = 0; i < sc->sc_txdatasz; i++) {		while (!(uart_getreg(&sc->sc_bas, SACOM_SR1) & SR1_TNF));		uart_setreg(&sc->sc_bas, SACOM_DR, sc->sc_txbuf[i]);		uart_barrier(&sc->sc_bas);	}#if 0	sr = uart_getreg(&sc->sc_bas, SACOM_SR0);#endif	return (0);}

static intmsm_getc(struct uart_bas *bas, struct mtx *mtx){	int c;	uart_lock(mtx);	/* Wait for a character to come ready */	while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) !=	    UART_DM_SR_RXRDY)		DELAY(4);	/* Check for Overrun error. If so reset Error Status */	if (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_UART_OVERRUN)		uart_setreg(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);	/* Read char */	c = uart_getreg(bas, UART_DM_RF(0));	uart_unlock(mtx);	return (c);}

static voidsa1110_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,    int parity){	int brd;		if (bas->rclk == 0)		bas->rclk = DEFAULT_RCLK;	while (uart_getreg(bas, SACOM_SR1) & SR1_TBY);	uart_setreg(bas, SACOM_CR3, 0);	brd = SACOMSPEED(baudrate);	uart_setreg(bas, SACOM_CR1, brd >> 8);	uart_setreg(bas, SACOM_CR2, brd & 0xff);	uart_setreg(bas, SACOM_CR3, CR3_RXE | CR3_TXE);}

static intti8250_bus_probe(struct uart_softc *sc){	int status;	int devid;	clk_ident_t clkid;	pcell_t prop;	phandle_t node;	/*	 * Get the device id from FDT.  If it's not there we can't turn on the	 * right clocks, so bail, unless we're doing unit 0.  We assume that's	 * the serial console, whose clock isn't controllable anyway, and we	 * sure don't want to break the console because of a config error.	 */	node = ofw_bus_get_node(sc->sc_dev);	if ((OF_getprop(node, "uart-device-id", &prop, sizeof(prop))) <= 0) {		device_printf(sc->sc_dev, 		    "missing uart-device-id attribute in FDT/n");		if (device_get_unit(sc->sc_dev) != 0)			return (ENXIO);		devid = 0;	} else		devid = fdt32_to_cpu(prop);	/* Enable clocks for this device.  We can't continue if that fails.  */	clkid = UART0_CLK + devid;	if ((status = ti_prcm_clk_enable(clkid)) != 0)		return (status);	/*	 * Set the hardware to disabled mode, do a full device reset, then set	 * it to uart mode.  Most devices will be reset-and-disabled already,	 * but you never know what a bootloader might have done.	 */	uart_setreg(&sc->sc_bas, MDR1_REG, MDR1_MODE_DISABLE);	uart_setreg(&sc->sc_bas, SYSCC_REG, SYSCC_SOFTRESET);	while (uart_getreg(&sc->sc_bas, SYSS_REG) & SYSS_STATUS_RESETDONE)		continue;	uart_setreg(&sc->sc_bas, MDR1_REG, MDR1_MODE_UART);	status = ns8250_bus_probe(sc); 	if (status == 0)		device_set_desc(sc->sc_dev, "TI UART (16550 compatible)");	return (status);}

static intjz4780_bus_attach(struct uart_softc *sc){    struct ns8250_softc *ns8250;    struct uart_bas *bas;    int rv;    ns8250 = (struct ns8250_softc *)sc;    bas = &sc->sc_bas;    rv = ns8250_bus_attach(sc);    if (rv != 0)        return (0);    /* Configure uart to use extra IER_RXTMOUT bit */    ns8250->ier_rxbits = IER_RXTMOUT | IER_EMSC | IER_ERLS | IER_ERXRDY;    ns8250->ier_mask = ~(ns8250->ier_rxbits);    ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;    ns8250->ier |= ns8250->ier_rxbits;    uart_setreg(bas, REG_IER, ns8250->ier);    uart_barrier(bas);    return (0);}