自学教程：C++ uart_setreg函数代码示例

static intoct16550_delay (struct uart_bas *bas){	int divisor;	u_char lcr;        static int delay = 0;        if (!delay_changed) return delay;        delay_changed = 0;	lcr = uart_getreg(bas, REG_LCR);	uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);	uart_barrier(bas);	divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);	uart_barrier(bas);	uart_setreg(bas, REG_LCR, lcr);	uart_barrier(bas);		if(!bas->rclk)		return 10; /* return an approx delay value */	/* 1/10th the time to transmit 1 character (estimate). */	if (divisor <= 134)		return (16000000 * divisor / bas->rclk);	return (16000 * divisor / (bas->rclk / 1000));}

static intsa1110_bus_transmit(struct uart_softc *sc){	int i;#if 0	int sr = uart_getreg(&sc->sc_bas, SACOM_SR0);	while (!(uart_getreg(&sc->sc_bas, SACOM_CR3) & CR3_TIE))		uart_setreg(&sc->sc_bas, SACOM_CR3,		    uart_getreg(&sc->sc_bas, SACOM_CR3) | CR3_TIE);    #endif	sc->sc_txbusy = 1;	uart_setreg(&sc->sc_bas, SACOM_CR3, uart_getreg(&sc->sc_bas, SACOM_CR3)	    | CR3_TIE);    	for (i = 0; i < sc->sc_txdatasz; i++) {		while (!(uart_getreg(&sc->sc_bas, SACOM_SR1) & SR1_TNF));		uart_setreg(&sc->sc_bas, SACOM_DR, sc->sc_txbuf[i]);		uart_barrier(&sc->sc_bas);	}#if 0	sr = uart_getreg(&sc->sc_bas, SACOM_SR0);#endif	return (0);}

/* Multiplexed I/O. */static __inline voiduart_setmreg(struct uart_bas *bas, int reg, int val){	uart_setreg(bas, REG_CTRL, reg);	uart_barrier(bas);	uart_setreg(bas, REG_CTRL, val);}

static voidsa1110_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,    int parity){	int brd;		if (bas->rclk == 0)		bas->rclk = DEFAULT_RCLK;	while (uart_getreg(bas, SACOM_SR1) & SR1_TBY);	uart_setreg(bas, SACOM_CR3, 0);	brd = SACOMSPEED(baudrate);	uart_setreg(bas, SACOM_CR1, brd >> 8);	uart_setreg(bas, SACOM_CR2, brd & 0xff);	uart_setreg(bas, SACOM_CR3, CR3_RXE | CR3_TXE);}

static voidmsm_putc(struct uart_bas *bas, int c){	int limit;	/*	 * Write to NO_CHARS_FOR_TX register the number of characters	 * to be transmitted. However, before writing TX_FIFO must	 * be empty as indicated by TX_READY interrupt in IMR register	 */	/*	 * Check if transmit FIFO is empty.	 * If not wait for TX_READY interrupt.	 */	limit = 1000;	if (!(uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXEMT)) {		while ((uart_getreg(bas, UART_DM_ISR) & UART_DM_TX_READY) == 0		    && --limit)			DELAY(4);	}	/* FIFO is ready, write number of characters to be written */	uart_setreg(bas, UART_DM_NO_CHARS_FOR_TX, 1);	/* Wait till TX FIFO has space */	while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXRDY) == 0)		DELAY(4);	/* TX FIFO has space. Write char */	SETREG(bas, UART_DM_TF(0), (c & 0xff));}

static intti8250_bus_probe(struct uart_softc *sc){	int status;	int devid;	clk_ident_t clkid;	pcell_t prop;	phandle_t node;	/*	 * Get the device id from FDT.  If it's not there we can't turn on the	 * right clocks, so bail, unless we're doing unit 0.  We assume that's	 * the serial console, whose clock isn't controllable anyway, and we	 * sure don't want to break the console because of a config error.	 */	node = ofw_bus_get_node(sc->sc_dev);	if ((OF_getprop(node, "uart-device-id", &prop, sizeof(prop))) <= 0) {		device_printf(sc->sc_dev, 		    "missing uart-device-id attribute in FDT/n");		if (device_get_unit(sc->sc_dev) != 0)			return (ENXIO);		devid = 0;	} else		devid = fdt32_to_cpu(prop);	/* Enable clocks for this device.  We can't continue if that fails.  */	clkid = UART0_CLK + devid;	if ((status = ti_prcm_clk_enable(clkid)) != 0)		return (status);	/*	 * Set the hardware to disabled mode, do a full device reset, then set	 * it to uart mode.  Most devices will be reset-and-disabled already,	 * but you never know what a bootloader might have done.	 */	uart_setreg(&sc->sc_bas, MDR1_REG, MDR1_MODE_DISABLE);	uart_setreg(&sc->sc_bas, SYSCC_REG, SYSCC_SOFTRESET);	while (uart_getreg(&sc->sc_bas, SYSS_REG) & SYSS_STATUS_RESETDONE)		continue;	uart_setreg(&sc->sc_bas, MDR1_REG, MDR1_MODE_UART);	status = ns8250_bus_probe(sc); 	if (status == 0)		device_set_desc(sc->sc_dev, "TI UART (16550 compatible)");	return (status);}

static __inline uint8_tuart_getmreg(struct uart_bas *bas, int reg){	uart_setreg(bas, REG_CTRL, reg);	uart_barrier(bas);	return (uart_getreg(bas, REG_CTRL));}

static intsa1110_getc(struct uart_bas *bas, struct mtx *mtx){	int c;	while (!(uart_getreg(bas, SACOM_SR1) & SR1_RNE)) {		u_int32_t sr0;		sr0 = uart_getreg(bas, SACOM_SR0);		if (ISSET(sr0, SR0_RBB))			uart_setreg(bas, SACOM_SR0, SR0_RBB);		if (ISSET(sr0, SR0_REB))			uart_setreg(bas, SACOM_SR0, SR0_REB);	}	c = uart_getreg(bas, SACOM_DR);	c &= 0xff;	return (c);}

static intsa1110_bus_param(struct uart_softc *sc, int baudrate, int databits,    int stopbits, int parity){	int brd;		if (baudrate > 0) {		brd = SACOMSPEED(baudrate);		uart_setreg(&sc->sc_bas, SACOM_CR1, brd >> 8);		uart_setreg(&sc->sc_bas, SACOM_CR2, brd & 0xff);	}

static voidmtk_uart_putc(struct uart_bas *bas, int c){	char chr;	if (!uart_output) return;	chr = c;	while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));	uart_setreg(bas, UART_TX_REG, c);	uart_barrier(bas);	while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));}

static voidmtk_uart_init(struct uart_bas *bas, int baudrate, int databits,    int stopbits, int parity){        /* CLKDIV  = 384000000/ 3/ 16/ br */        /* for 384MHz CLKDIV = 8000000 / baudrate; */        switch (databits) {        case 5:    		databits = UART_LCR_5B;    		break;        case 6:    		databits = UART_LCR_6B;    		break;        case 7:    		databits = UART_LCR_7B;    		break;        case 8:    		databits = UART_LCR_8B;    		break;    	default:    		/* Unsupported */    		return;        }	switch (parity) {	case UART_PARITY_EVEN:	parity = (UART_LCR_PEN|UART_LCR_EVEN); break;	case UART_PARITY_ODD:	parity = (UART_LCR_PEN); break;	case UART_PARITY_NONE:	parity = 0; break;	/* Unsupported */	default:		return;	}	if (bas->rclk && baudrate) {        	uart_setreg(bas, UART_CDDL_REG, bas->rclk/16/baudrate);		uart_barrier(bas);	}        uart_setreg(bas, UART_LCR_REG, databits |				(stopbits==1?0:UART_LCR_STB_15) |       			 	parity);	uart_barrier(bas);}

static voidadm5120_uart_putc(struct uart_bas *bas, int c){	char chr;	chr = c;	while (uart_getreg(bas, UART_FR_REG) & UART_FR_TX_FIFO_FULL)		;	uart_setreg(bas, UART_DR_REG, c);	while (uart_getreg(bas, UART_FR_REG) & UART_FR_BUSY)		;	uart_barrier(bas);}

static intsa1110_bus_receive(struct uart_softc *sc){	#if 0	while (!(uart_getreg(&sc->sc_bas, SACOM_SR1) & SR1_RNE)) {		u_int32_t sr0;		sr0 = uart_getreg(&sc->sc_bas, SACOM_SR0);		if (ISSET(sr0, SR0_RBB))			uart_setreg(&sc->sc_bas, SACOM_SR0, SR0_RBB);		if (ISSET(sr0, SR0_REB))			uart_setreg(&sc->sc_bas, SACOM_SR0, SR0_REB);	}#endif		uart_setreg(&sc->sc_bas, SACOM_CR3, uart_getreg(&sc->sc_bas, SACOM_CR3)	    | CR3_RIE);	uart_rx_put(sc, uart_getreg(&sc->sc_bas, SACOM_DR));	return (0);}

static intmsm_bus_attach(struct uart_softc *sc){	struct msm_uart_softc *u = (struct msm_uart_softc *)sc;	struct uart_bas *bas = &sc->sc_bas;	sc->sc_hwiflow = 0;	sc->sc_hwoflow = 0;	/* Set TX_READY, TXLEV, RXLEV, RXSTALE */	u->ier = UART_DM_IMR_ENABLED;	/* Configure Interrupt Mask register IMR */	uart_setreg(bas, UART_DM_IMR, u->ier);	return (0);}

static intmsm_getc(struct uart_bas *bas, struct mtx *mtx){	int c;	uart_lock(mtx);	/* Wait for a character to come ready */	while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) !=	    UART_DM_SR_RXRDY)		DELAY(4);	/* Check for Overrun error. If so reset Error Status */	if (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_UART_OVERRUN)		uart_setreg(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);	/* Read char */	c = uart_getreg(bas, UART_DM_RF(0));	uart_unlock(mtx);	return (c);}

static intjz4780_bus_attach(struct uart_softc *sc){    struct ns8250_softc *ns8250;    struct uart_bas *bas;    int rv;    ns8250 = (struct ns8250_softc *)sc;    bas = &sc->sc_bas;    rv = ns8250_bus_attach(sc);    if (rv != 0)        return (0);    /* Configure uart to use extra IER_RXTMOUT bit */    ns8250->ier_rxbits = IER_RXTMOUT | IER_EMSC | IER_ERLS | IER_ERXRDY;    ns8250->ier_mask = ~(ns8250->ier_rxbits);    ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;    ns8250->ier |= ns8250->ier_rxbits;    uart_setreg(bas, REG_IER, ns8250->ier);    uart_barrier(bas);    return (0);}

static voidmsm_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,    int parity){	if (bas->rclk == 0)		bas->rclk = DEF_CLK;	KASSERT(bas->rclk != 0, ("msm_init: Invalid rclk"));	/* Set default parameters */	msm_uart_param(bas, baudrate, databits, stopbits, parity);	/*	 * Configure UART mode registers MR1 and MR2.	 * Hardware flow control isn't supported.	 */	uart_setreg(bas, UART_DM_MR1, 0x0);	/* Reset interrupt mask register. */	uart_setreg(bas, UART_DM_IMR, 0);	/*	 * Configure Tx and Rx watermarks configuration registers.	 * TX watermark value is set to 0 - interrupt is generated when	 * FIFO level is less than or equal to 0.	 */	uart_setreg(bas, UART_DM_TFWR, UART_DM_TFW_VALUE);	/* Set RX watermark value */	uart_setreg(bas, UART_DM_RFWR, UART_DM_RFW_VALUE);	/*	 * Configure Interrupt Programming Register.	 * Set initial Stale timeout value.	 */	uart_setreg(bas, UART_DM_IPR, UART_DM_STALE_TIMEOUT_LSB);	/* Disable IRDA mode */	uart_setreg(bas, UART_DM_IRDA, 0x0);	/*	 * Configure and enable sim interface if required.	 * Configure hunt character value in HCR register.	 * Keep it in reset state.	 */	uart_setreg(bas, UART_DM_HCR, 0x0);	/* Issue soft reset command */	SETREG(bas, UART_DM_CR, UART_DM_RESET_TX);	SETREG(bas, UART_DM_CR, UART_DM_RESET_RX);	SETREG(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);	SETREG(bas, UART_DM_CR, UART_DM_RESET_BREAK_INT);	SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);	/* Enable/Disable Rx/Tx DM interfaces */	/* Disable Data Mover for now. */	uart_setreg(bas, UART_DM_DMEN, 0x0);	/* Enable transmitter and receiver */	uart_setreg(bas, UART_DM_CR, UART_DM_CR_RX_ENABLE);	uart_setreg(bas, UART_DM_CR, UART_DM_CR_TX_ENABLE);	uart_barrier(bas);}

static voidsa1110_putc(struct uart_bas *bas, int c){	while (!(uart_getreg(bas, SACOM_SR1) & SR1_TNF));	uart_setreg(bas, SACOM_DR, c);}

static intmsm_uart_param(struct uart_bas *bas, int baudrate, int databits,    int stopbits, int parity){	int ulcon;	ulcon = 0;	switch (databits) {	case 5:		ulcon |= (UART_DM_5_BPS << 4);		break;	case 6:		ulcon |= (UART_DM_6_BPS << 4);		break;	case 7:		ulcon |= (UART_DM_7_BPS << 4);		break;	case 8:		ulcon |= (UART_DM_8_BPS << 4);		break;	default:		return (EINVAL);	}	switch (parity) {	case UART_PARITY_NONE:		ulcon |= UART_DM_NO_PARITY;		break;	case UART_PARITY_ODD:		ulcon |= UART_DM_ODD_PARITY;		break;	case UART_PARITY_EVEN:		ulcon |= UART_DM_EVEN_PARITY;		break;	case UART_PARITY_SPACE:		ulcon |= UART_DM_SPACE_PARITY;		break;	case UART_PARITY_MARK:	default:		return (EINVAL);	}	switch (stopbits) {	case 1:		ulcon |= (UART_DM_SBL_1 << 2);		break;	case 2:		ulcon |= (UART_DM_SBL_2 << 2);		break;	default:		return (EINVAL);	}	uart_setreg(bas, UART_DM_MR2, ulcon);	/* Set 115200 for both TX and RX. */;	uart_setreg(bas, UART_DM_CSR, UART_DM_CSR_115200);	uart_barrier(bas);	return (0);}