自学教程：C++ up_enable_irq函数代码示例

/* * Initialise the timer we are going to use. * * We expect that we'll own one of the reduced-function STM32 general * timers, and that we can use channel 1 in compare mode. */static voidhrt_tim_init(void){	/* claim our interrupt vector */	irq_attach(HRT_TIMER_VECTOR, hrt_tim_isr);	/* clock/power on our timer */	modifyreg32(HRT_TIMER_POWER_REG, 0, HRT_TIMER_POWER_BIT);	/* disable and configure the timer */	rCR1 = 0;	rCR2 = 0;	rSMCR = 0;	rDIER = DIER_HRT | DIER_PPM;	rCCER = 0;		/* unlock CCMR* registers */	rCCMR1 = CCMR1_PPM;	rCCMR2 = CCMR2_PPM;	rCCER = CCER_PPM;	rDCR = 0;	/* configure the timer to free-run at 1MHz */	rPSC = (HRT_TIMER_CLOCK / 1000000) - 1;	/* this really only works for whole-MHz clocks */	/* run the full span of the counter */	rARR = 0xffff;	/* set an initial capture a little ways off */	rCCR_HRT = 1000;	/* generate an update event; reloads the counter, all registers */	rEGR = GTIM_EGR_UG;	/* enable the timer */	rCR1 = GTIM_CR1_CEN;	/* enable interrupts */	up_enable_irq(HRT_TIMER_VECTOR);}

int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg){  irqstate_t flags;  int irq;  /* Verify that the button ID is within range */  if ((unsigned)id < NUM_BUTTONS)    {      /* Disable interrupts until we are done */      flags = enter_critical_section();      /* Configure the interrupt.  Either attach and enable the new       * interrupt or disable and detach the old interrupt handler.       */      irq = g_buttonirq[id];      if (irqhandler)        {          /* Attach then enable the new interrupt handler */          (void)irq_attach(irq, irqhandler, arg);          up_enable_irq(irq);        }      else        {          /* Disable then detach the old interrupt handler */          up_disable_irq(irq);          (void)irq_detach(irq);        }      leave_critical_section(flags);    }  return OK;}

void tiva_adc_sse_int_enable(uint8_t adc, uint8_t sse, bool state){  irqstate_t flags;  uintptr_t imreg = TIVA_ADC_IM(adc);  int irq = tiva_adc_getirq(adc, sse);  flags = enter_critical_section();  up_disable_irq(irq);  tiva_adc_sse_clear_int(adc, sse);  if (state == true)    {      modifyreg32(imreg, 0, (1 << sse));    }  else    {      modifyreg32(imreg, (1 << sse), 0);    }  up_enable_irq(irq);  leave_critical_section(flags);}

static int skel_ifup(FAR struct net_driver_s *dev){  FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)dev->d_private;#ifdef CONFIG_NET_IPv4  ndbg("Bringing up: %d.%d.%d.%d/n",       dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);#endif#ifdef CONFIG_NET_IPv6  ndbg("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x/n",       dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],       dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],       dev->d_ipv6addr[6], dev->d_ipv6addr[7]);#endif  /* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */  /* Instantiate the MAC address from priv->sk_dev.d_mac.ether_addr_octet */#ifdef CONFIG_NET_ICMPv6  /* Set up IPv6 multicast address filtering */  skel_ipv6multicast(priv);#endif  /* Set and activate a timer process */  (void)wd_start(priv->sk_txpoll, skeleton_WDDELAY, skel_poll_expiry, 1,                 (wdparm_t)priv);  /* Enable the Ethernet interrupt */  priv->sk_bifup = true;  up_enable_irq(CONFIG_skeleton_IRQ);  return OK;}

/**************************************************************************** * Name: adc_setup * * Description: *   Configure the ADC. This method is called the first time that the ADC *   device is opened.  This will occur when the port is first opened. *   This setup includes configuring and attaching ADC interrupts. *   Interrupts are all disabled upon return. * * Input Parameters: * * Returned Value: ****************************************************************************/static int adc_setup(FAR struct adc_dev_s *dev){	int ret;	FAR struct s5j_dev_s *priv = (FAR struct s5j_dev_s *)dev->ad_priv;	/* Attach the ADC interrupt */	ret = irq_attach(IRQ_ADC, adc_interrupt, priv);	if (ret < 0) {		lldbg("irq_attach failed: %d/n", ret);		return ret;	}	/* Make sure that the ADC device is in the powered up, reset state */	adc_reset(dev);	/*	 * Enable the ADC interrupt, but it will not be generated until we	 * request to start the conversion.	 */	llwdbg("Enable the ADC interrupt: irq=%d/n", IRQ_ADC);	up_enable_irq(IRQ_ADC);	return OK;}

void up_timer_initialize(void){  /* uint32_t to avoid compile time overflow errors */  uint32_t divisor = PIT_DIVISOR;  DEBUGASSERT(divisor <= 0xffff);  /* Attach to the timer interrupt handler */  (void)irq_attach(IRQ0, (xcpt_t)up_timerisr);  /* Send the command byte to configure counter 0 */  outb(PIT_OCW_MODE_SQUARE|PIT_OCW_RL_DATA|PIT_OCW_COUNTER_0, PIT_REG_COMMAND);  /* Set the PIT input frequency divisor */  outb((uint8_t)(divisor & 0xff),  PIT_REG_COUNTER0);  outb((uint8_t)((divisor >> 8) & 0xff), PIT_REG_COUNTER0);  /* And enable IRQ0 */  up_enable_irq(IRQ0);}

/** * Initialise an I2C device */struct i2c_dev_s *up_i2cinitialize(int port){    irqstate_t flags;    int retval;    i2cvdbg("Init I2C port %d/n", port);    /* Only one I2C port on TSB */    if (port > 0)        return NULL;    flags = irqsave();    if (refcount++)        goto out;    retval = tsb_request_pinshare(TSB_PIN_GPIO21 | TSB_PIN_GPIO22);    if (retval) {        lowsyslog("I2C: cannot get ownership of I2C pins/n");        goto err_req_pinshare;    }    sem_init(&g_mutex, 0, 1);    sem_init(&g_wait, 0, 0);    /* enable I2C pins */    tsb_clr_pinshare(TSB_PIN_GPIO21);    tsb_clr_pinshare(TSB_PIN_GPIO22);    /* enable I2C clocks */    tsb_clk_enable(TSB_CLK_I2CP);    tsb_clk_enable(TSB_CLK_I2CS);    /* reset I2C module */    tsb_reset(TSB_RST_I2CP);    tsb_reset(TSB_RST_I2CS);    /* Initialize the I2C controller */    tsb_i2c_init();    /* Allocate a watchdog timer */    g_timeout = wd_create();    DEBUGASSERT(g_timeout != 0);    /* Attach Interrupt Handler */    irq_attach(TSB_IRQ_I2C, i2c_interrupt);    /* Enable Interrupt Handler */    up_enable_irq(TSB_IRQ_I2C);    /* Install our operations */    g_dev.ops = &dev_i2c_ops;out:    irqrestore(flags);    return &g_dev;err_req_pinshare:    refcount--;    irqrestore(flags);    return NULL;}

void up_timer_initialize(void){  uint32_t ticks_per_int;  uint32_t mask_bits = 0;  uint32_t mask_test = 0x80000000;  lpc43_RIT_timer_stop();  lpc43_load_RIT_timer(0);  internal_timer = 0;  /* Set up the IRQ here */  irq_attach(LPC43M4_IRQ_RITIMER, lpc43_RIT_isr);  /* Compute how many seconds per tick we have on the main clock.  If it is   * 204MHz for example, then there should be about 4.90ns per tick   */  sec_per_tick = (double)1.0/(double)LPC43_CCLK;  /* Given an RIT_TIMER_RESOLUTION, compute how many ticks it will take to   * reach that resolution.  For example, if we wanted a 1/4uS timer   * resolution, that would be 250ns resolution.  The timer is an integer   * value, although maybe this should change, but that means   * 250/1000000000*0.00000000490 = 51.02 ticks or 51 ticks, roughly.   * We round up by 1 tick.   */  ticks_per_int = RIT_TIMER_RESOLUTION/(1000000000*sec_per_tick)+1;  /* Now we need to compute the mask that will let us set up to generate an   * interrupt every 1/4uS.  This isn't "tickless" per-se, and probably   * should be implemented differently, however it allows me to create a   * 64 bit nanosecond timer than can "free-run" by being updated every   * RIT_TIMER_RESOLUTION cycles.  I would have implemented the better   * approach, but I didn't have a good way to determine how to manage a   * 32 bit ns timer.  Every 21 seconds the thing rolls [email
C++ up_fullcontextrestore函数代码示例
C++ up函数代码示例