自学教程：C++ upmconfig函数代码示例

/* * Initialize Local Bus */void local_bus_init (void){	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);	sys_info_t sysinfo;	uint clkdiv;	uint lbc_mhz;	uint lcrr = CONFIG_SYS_LBC_LCRR;	get_sys_info (&sysinfo);	clkdiv = lbc->lcrr & LCRR_CLKDIV;	lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */	if (lbc_mhz >= 66)		lcrr &= ~LCRR_DBYP;	/* DLL Enabled */	else		lcrr |= LCRR_DBYP;	/* DLL Bypass */	out_be32 (&lbc->lcrr, lcrr);	asm ("sync;isync;msync");	out_be32 (&lbc->ltesr, 0xffffffff);	/* Clear LBC error interrupts */	out_be32 (&lbc->lteir, 0xffffffff);	/* Enable LBC error interrupts */	out_be32 (&ecm->eedr, 0xffffffff);	/* Clear ecm errors */	out_be32 (&ecm->eeer, 0xffffffff);	/* Enable ecm errors */	/* Init UPMA for FPGA access */	out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */	upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));	/* Init UPMB for Lime controller access */	out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */	upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));}

phys_size_t initdram (int board_type){	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	long int size_b0;	memctl->memc_or2 = CONFIG_SYS_OR2;	memctl->memc_br2 = CONFIG_SYS_BR2;	udelay(100);	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));	memctl->memc_mptpr = MPTPR_PTP_DIV16;	memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X;	/*Do the initialization of the SDRAM*/	/*Start with the precharge cycle*/	memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | /				MCR_MLCF(1) | MCR_MAD(0x5));	/*Then we need two refresh cycles*/	memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X;	memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | /				MCR_MLCF(2) | MCR_MAD(0x30));	/*Mode register programming*/	memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/	memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | /				MCR_MLCF(1) | MCR_MAD(0x1C));	/* That should do it, just enable the periodic refresh in burst of 4*/	memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X;	memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);	size_b0 = 16*1024*1024;	/*	 * No bank 1 or 3	 * invalidate bank	 */	memctl->memc_br1 = 0;	memctl->memc_br3 = 0;	upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));	memctl->memc_mbmr = MBMR_GPL_B4DIS;	memctl->memc_or4 = CONFIG_SYS_OR4;	memctl->memc_br4 = CONFIG_SYS_BR4;	return (size_b0);}

int board_nand_init(struct nand_chip *nand){	static	int	UpmInit = 0;	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;	volatile memctl8260_t *memctl = &immr->im_memctl;	if (hwinf.nand == 0) return -1;	/* Setup the UPM */	if (UpmInit == 0) {		switch (hwinf.busclk_real) {		case 100000000:			upmconfig (UPMB, (uint *) upmTable100,			   sizeof (upmTable100) / sizeof (uint));			break;		case 133333333:			upmconfig (UPMB, (uint *) upmTable133,			   sizeof (upmTable133) / sizeof (uint));			break;		default:			upmconfig (UPMB, (uint *) upmTable67,			   sizeof (upmTable67) / sizeof (uint));			break;		}		UpmInit = 1;	}	/* Setup the memctrl */	memctl->memc_or3 = CONFIG_SYS_NAND_OR;	memctl->memc_br3 = CONFIG_SYS_NAND_BR;	memctl->memc_mbmr = (MxMR_OP_NORM);	nand->ecc.mode = NAND_ECC_SOFT;	nand->cmd_ctrl	 = upmnand_hwcontrol;	nand->read_byte	 = upmnand_read_byte;	nand->dev_ready	 = tqm8272_dev_ready;#ifndef CONFIG_NAND_SPL	nand->write_buf	 = tqm8272_write_buf;	nand->read_buf	 = tqm8272_read_buf;	nand->verify_buf = tqm8272_verify_buf;#endif	/*	 * Select required NAND chip	 */	board_nand_select_device(nand, 0);	return 0;}

phys_size_t initdram (int board_type){	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	/* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */	upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));#ifndef CONFIG_AMX_RAM_EXT	memctl->memc_mptpr = 0x0400; /* divide by 16 */#else	memctl->memc_mptpr = 0x0200;#endif	memctl->memc_mamr = 0x30a21114;	memctl->memc_or2 = 0xffc00800;#ifndef CONFIG_AMX_RAM_EXT	memctl->memc_br2 = 0x81;	return (4 << 20);#else	memctl->memc_or1 = 0xff000800;	memctl->memc_br1 = 0x00000081;	memctl->memc_br2 = 0x01000081;	return (20 << 20);#endif}

phys_size_t initdram (int board_type){	long int msize;	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));	/* Configure SDRAM refresh */	memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */	memctl->memc_mamr = (65 << 24) | CONFIG_SYS_MAMR; /* No refresh */	udelay(100);	/* Run MRS pattern from location 0x36 */	memctl->memc_mar = 0x88;	memctl->memc_mcr = 0x80002236;	udelay(100);	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);	memctl->memc_or1  |= ~(msize - 1);	return msize;}

static int _initsdram(uint base, uint noMbytes){	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));	memctl->memc_mptpr = MPTPR_2BK_4K;	memctl->memc_mbmr  = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */	/* map CS 4 */	memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);	memctl->memc_br4 = SDRAM_BR4VALUE | base;	/* Perform SDRAM initilization */# ifdef UPM_NOP_ADDR    /* not currently in UPM table */	/* step 1: nop */	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |			   MCR_MLCF(0) | UPM_NOP_ADDR;# endif	/* step 2: delay */	udelay(200);# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */	/* step 3: precharge */	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |			   MCR_MLCF(4) | UPM_PRECHARGE_ADDR;# endif	/* step 4: refresh */	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |			   MCR_MLCF(2) | UPM_REFRESH_ADDR;	/*	 * note: for some reason, the UPM values we are using include	 * precharge with MRS	 */	/* step 5: mrs */	memctl->memc_mar = 0x00000088;	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |			   MCR_MLCF(1) | UPM_MRS_ADDR;# ifdef UPM_NOP_ADDR	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |			   MCR_MLCF(0) | UPM_NOP_ADDR;# endif	/*	 * Enable refresh	 */	memctl->memc_mbmr |= MBMR_PTBE;	return 0;}

/* * Initialize SDRAM */long int initdram (int board_type){	volatile immap_t *immr = (immap_t *) CFG_IMMR;	volatile memctl8xx_t *memctl = &immr->im_memctl;	upmconfig (UPMA,		   (uint *) sdram_upm_table,		   sizeof (sdram_upm_table) / sizeof (uint)		);	/*	 * Setup MAMR register	 */	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */	/*	 * Map CS1* to SDRAM bank	 */	memctl->memc_or1 = CFG_OR1;	memctl->memc_br1 = CFG_BR1;	/*	 * Perform SDRAM initialization sequence:	 * 1. Apply at least one NOP command	 * 2. 100 uS delay (JEDEC standard says 200 uS)	 * 3. Issue 4 precharge commands	 * 4. Perform two refresh cycles	 * 5. Program mode register	 *	 * Program SDRAM for standard operation, sequential burst, burst length	 * of 4, CAS latency of 2.	 */	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |		MCR_MLCF (0) | UPMA_NOP_ADDR;	udelay (200);	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |		MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |		MCR_MLCF (2) | UPM_REFRESH_ADDR;	memctl->memc_mar = 0x00000088;	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |		MCR_MLCF (1) | UPMA_MRS_ADDR;	memctl->memc_mar = 0x00000000;	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |		MCR_MLCF (0) | UPMA_NOP_ADDR;	/*	 * Enable refresh	 */	memctl->memc_mamr |= MAMR_PTAE;	return (SDRAM_SIZE);}

intmisc_init_f (void){	volatile immap_t *immap = (immap_t *) CFG_IMMR;	volatile memctl8260_t *memctl = &immap->im_memctl;	printf ("UPMs:  ");	upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);	memctl->memc_mbmr = CFG_MBMR;	upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);	memctl->memc_mcmr = CFG_MCMR;	printf ("configured/n");	return (0);}

void doc_init (void){	volatile immap_t *immap = (immap_t *) CFG_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	upmconfig (UPMB, (uint *) static_table,		   sizeof (static_table) / sizeof (uint));	memctl->memc_mbmr = MAMR_DSA_1_CYCL;	doc_probe (FLASH_BASE1_PRELIM);}

int board_early_init_f(void){	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;	volatile iop8xx_t *ioport = &immap->im_ioport;	volatile cpm8xx_t *cpm = &immap->im_cpm;	volatile memctl8xx_t *memctl = &immap->im_memctl;	/* NAND chip select */#if CONFIG_NETPHONE_VERSION == 1	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);#elif CONFIG_NETPHONE_VERSION == 2	upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);	memctl->memc_mamr = 0;	/* all clear */#endif	/* DSP chip select */	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);#if CONFIG_NETPHONE_VERSION == 1	memctl->memc_br4 &= ~BR_V;#endif	memctl->memc_br5 &= ~BR_V;	memctl->memc_br6 &= ~BR_V;	memctl->memc_br7 &= ~BR_V;	ioport->iop_padat	= PA_GP_OUTVAL;	ioport->iop_paodr	= PA_ODR_VAL;	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;	ioport->iop_papar	= PA_SP_MASK;	cpm->cp_pbdat		= PB_GP_OUTVAL;	cpm->cp_pbodr		= PB_ODR_VAL;	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;	cpm->cp_pbpar		= PB_SP_MASK;	ioport->iop_pcdat	= PC_GP_OUTVAL;	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;	ioport->iop_pcso	= PC_SOVAL;	ioport->iop_pcint	= PC_INTVAL;	ioport->iop_pcpar	= PC_SP_MASK;	cpm->cp_pedat		= PE_GP_OUTVAL;	cpm->cp_peodr		= PE_ODR_VAL;	cpm->cp_pedir		= PE_GP_OUTMASK | PE_SP_DIRVAL;	cpm->cp_pepar		= PE_SP_MASK;	return 0;}

int board_early_init_r(void){	struct km_bec_fpga *base =		(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;#if defined(CONFIG_SUVD3)	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;	fsl_lbc_t *lbc = &immap->im_lbc;	u32 *mxmr = &lbc->mamr;#endif#if defined(CONFIG_MPC8360)	unsigned short	svid;	/*	 * Because of errata in the UCCs, we have to write to the reserved	 * registers to slow the clocks down.	 */	svid =  SVR_REV(mfspr(SVR));	switch (svid) {	case 0x0020:		/*		 * MPC8360ECE.pdf QE_ENET10 table 4:		 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)		 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)		 */		setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);		break;	case 0x0021:		/*		 * MPC8360ECE.pdf QE_ENET10 table 4:		 * IMMR + 0x14AC[24:27] = 1010		 */		clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),			0x00000050, 0x000000a0);		break;	}#endif	/* enable the PHY on the PIGGY */	setbits_8(&base->pgy_eth, 0x01);	/* enable the Unit LED (green) */	setbits_8(&base->oprth, WRL_BOOT);	/* enable Application Buffer */	setbits_8(&base->oprtl, OPRTL_XBUFENA);#if defined(CONFIG_SUVD3)	/* configure UPMA for APP1 */	upmconfig(UPMA, (uint *) upma_table,		sizeof(upma_table) / sizeof(uint));	out_be32(mxmr, CONFIG_SYS_MAMR);#endif	return 0;}

phys_size_t initdram (int board_type){	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	long int size_b0 = 0;	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));	memctl->memc_mptpr = CFG_MPTPR;#if defined (CONFIG_SDRAM_16M)	memctl->memc_mamr = 0x00802114 | CFG_MxMR_PTx;	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */	udelay(1);	memctl->memc_mcr  = 0x80002830;	udelay(1);	memctl->memc_mar  = 0x00000088;	udelay(1);	memctl->memc_mcr  = 0x80002106;	udelay(1);	memctl->memc_or1 =  0xff000a00;	size_b0 = 0x01000000;#elif defined (CONFIG_SDRAM_32M)	memctl->memc_mamr = 0x00904114 | CFG_MxMR_PTx;	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */	udelay(1);	memctl->memc_mcr  = 0x80002830;	udelay(1);	memctl->memc_mar  = 0x00000088;	udelay(1);	memctl->memc_mcr  = 0x80002106;	udelay(1);	memctl->memc_or1 =  0xfe000a00;	size_b0 = 0x02000000;#elif defined (CONFIG_SDRAM_64M)	memctl->memc_mamr = 0x00a04114 | CFG_MxMR_PTx;	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */	udelay(1);	memctl->memc_mcr  = 0x80002830;	udelay(1);	memctl->memc_mar  = 0x00000088;	udelay(1);	memctl->memc_mcr  = 0x80002106;	udelay(1);	memctl->memc_or1 =  0xfc000a00;	size_b0 = 0x04000000;#else#error SDRAM size configuration missing.#endif	memctl->memc_br1 =  0x00000081;	udelay(200);	return (size_b0 );}

phys_size_t initdram (int board_type){	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	long int size9;	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));	/* Refresh clock prescalar */	memctl->memc_mptpr = CONFIG_SYS_MPTPR ;	memctl->memc_mar  = 0x00000088;	/* Map controller banks 1 to the SDRAM bank */	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */	/*Disable Periodic timer A. */	udelay(200);	/* perform SDRAM initializsation sequence */	memctl->memc_mcr  = 0x80002236; /* SDRAM bank 0 - refresh twice */	udelay(1);	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */	/*Enable Periodic timer A */	udelay (1000);	 /* Check Bank 0 Memory Size	  * try 9 column mode	  */	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);	/*	 * Final mapping:	 */	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;	udelay (1000);	return (size9);}

int board_early_init_f(void){	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;	volatile iop8xx_t *ioport = &immap->im_ioport;	volatile cpm8xx_t *cpm = &immap->im_cpm;	volatile memctl8xx_t *memctl = &immap->im_memctl;	(void)ioport;	(void)cpm;#if 1	/* NAND chip select */	upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);	memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);	memctl->memc_mbmr = 0;	/* all clear */#endif	memctl->memc_br5 &= ~BR_V;	memctl->memc_br6 &= ~BR_V;	memctl->memc_br7 &= ~BR_V;#if 1	ioport->iop_padat	= PA_GP_OUTVAL;	ioport->iop_paodr	= PA_ODR_VAL;	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;	ioport->iop_papar	= PA_SP_MASK;	cpm->cp_pbdat		= PB_GP_OUTVAL;	cpm->cp_pbodr		= PB_ODR_VAL;	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;	cpm->cp_pbpar		= PB_SP_MASK;	ioport->iop_pcdat	= PC_GP_OUTVAL;	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;	ioport->iop_pcso	= PC_SOVAL;	ioport->iop_pcint	= PC_INTVAL;	ioport->iop_pcpar	= PC_SP_MASK;	cpm->cp_pedat		= PE_GP_OUTVAL;	cpm->cp_peodr		= PE_ODR_VAL;	cpm->cp_pedir		= PE_GP_OUTMASK | PE_SP_DIRVAL;	cpm->cp_pepar		= PE_SP_MASK;#endif	return 0;}

phys_size_t initdram(int board_type){	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	long int size;	upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));	/*	 * Preliminary prescaler for refresh	 */	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */    /*     * Map controller bank 3 to the SDRAM bank at preliminary address.     */	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & ~MAMR_PTAE;	/* no refresh yet */	udelay(200);	/* perform SDRAM initialisation sequence */	memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C);	/* precharge all			*/	udelay(1);	memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0)		*/	udelay(1);	memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E);	/* exception program (write mar) */	udelay(1);	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */	udelay(1000);	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;	size = SDRAM_MAX_SIZE;	udelay(10000);	return (size);}

/***************************************************************************** * Initialize DRAM controller *****************************************************************************/phys_size_t initdram (int board_type){	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	/*	 * Only initialize memory controller when running from FLASH.	 * When running from RAM, don't touch it.	 */	if ((ulong) initdram & 0xff000000) {		volatile uint *addr1, *addr2;		uint i;		upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl,			   sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));		memctl->memc_mptpr = 0x0200;		memctl->memc_mamr = 0x0ca20330;		memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM;		memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V;		/*		 * Do 8 read accesses to DRAM		 */		addr1 = (volatile uint *) 0;		addr2 = (volatile uint *) 0x00400000;		for (i = 0; i < 8; i++)			in_be32(addr1);		/*		 * Now check whether we got 4MB or 16MB populated		 */		addr1[0] = 0x12345678;		addr1[1] = 0x9abcdef0;		addr2[0] = 0xfeedc0de;		addr2[1] = 0x47110815;		if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) {			/* only 4MB populated */			memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM;		}	}	return -(memctl->memc_or2 & 0xffff0000);}

phys_size_t initdram (int board_type){	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	long int size10;	upmconfig (UPMA, (uint *) sdram_table,		   sizeof (sdram_table) / sizeof (uint));	/* Refresh clock prescalar */	memctl->memc_mptpr = CONFIG_SYS_MPTPR;	memctl->memc_mar = 0x00000000;	/* Map controller banks 1 to the SDRAM bank */	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;	memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */	udelay (200);	/* perform SDRAM initializsation sequence */	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - refresh twice */	udelay (1);	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */	udelay (1000);	/* Check Bank 0 Memory Size	 * try 10 column mode	 */	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,			    SDRAM_MAX_SIZE);	return (size10);}

int checkboard (void){	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);	char *src;	int f;	char *s = getenv("serial#");	puts("Board: Socrates");	if (s != NULL) {		puts(", serial# ");		puts(s);	}	putc('/n');#ifdef CONFIG_PCI	/* Check the PCI_clk sel bit */	if (in_be32(&gur->porpllsr) & (1<<15)) {		src = "SYSCLK";		f = CONFIG_SYS_CLK_FREQ;	} else {		src = "PCI_CLK";		f = CONFIG_PCI_CLK_FREQ;	}	printf ("PCI1:  32 bit, %d MHz (%s)/n",	f/1000000, src);#else	printf ("PCI1:  disabled/n");#endif	/*	 * Initialize local bus.	 */	local_bus_init ();#if defined(CFG_FPGA_BASE)	/* Init UPMA for FPGA access */	upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));#endif	return 0;}

long int initdram (int board_type){	long int msize;	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));	/* Configure SDRAM refresh */	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */	memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */	udelay(200);	/* Run precharge from location 0x15 */	memctl->memc_mar = 0x0;	memctl->memc_mcr = 0x80002115;	udelay(200);	/* Run 8 refresh cycles */	memctl->memc_mcr = 0x80002830;	udelay(200);	/* Run MRS pattern from location 0x16 */	memctl->memc_mar = 0x88;	memctl->memc_mcr = 0x80002116;	udelay(200);	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */	memctl->memc_or1   = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;	memctl->memc_br1   =  CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;	msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);	memctl->memc_or1  |= ~(msize - 1);	return msize;}

/* * Miscellaneous intialization */int misc_init_r (void){	volatile immap_t *immr = (immap_t *) CFG_IMMR;	volatile memctl8xx_t *memctl = &immr->im_memctl;	/*	 * Set up UPMB to handle the Virtex FPGA SelectMap interface	 */	upmconfig (UPMB, (uint *) selectmap_upm_table,		   sizeof (selectmap_upm_table) / sizeof (uint));	memctl->memc_mbmr = 0x0;	config_mpc8xx_ioports (immr);#if (CONFIG_COMMANDS & CFG_CMD_MII)	mii_init ();#endif#if (CONFIG_FPGA)	gen860t_init_fpga ();#endif	return 0;}

long int initdram (int board_type){	volatile immap_t *immap = (immap_t *) CFG_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	long int size_b0, size8, size9;	upmconfig (UPMA, (uint *) sdram_table,		   sizeof (sdram_table) / sizeof (uint));	/*	 * 1 Bank of 64Mbit x 2 devices	 */	memctl->memc_mptpr = CFG_MPTPR_1BK_4K;	memctl->memc_mar = 0x00000088;	/*	 * Map controller SDRAM bank 0	 */	memctl->memc_or4 = CFG_OR4_PRELIM;	memctl->memc_br4 = CFG_BR4_PRELIM;	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */	udelay (200);	/*	 * Perform SDRAM initializsation sequence	 */	memctl->memc_mcr = 0x80008105;	/* SDRAM bank 0 */	udelay (1);	memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;	udelay (200);	memctl->memc_mcr = 0x80008130;	/* SDRAM bank 0 - execute twice */	udelay (1);	memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;	udelay (200);	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */	udelay (1000);	/*	 * Preliminary prescaler for refresh (depends on number of	 * banks): This value is selected for four cycles every 62.4 us	 * with two SDRAM banks or four cycles every 31.2 us with one	 * bank. It will be adjusted after memory sizing.	 */	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;	/* 16: but should be: CFG_MPTPR_1BK_4K */	/*	 * Check Bank 0 Memory Size for re-configuration	 *	 * try 8 column mode	 */	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE4_PRELIM,			   SDRAM_MAX_SIZE);	udelay (1000);	/*	 * try 9 column mode	 */	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE4_PRELIM,			   SDRAM_MAX_SIZE);	if (size8 < size9) {	/* leave configuration at 9 columns     */		size_b0 = size9;/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB/n", size >> 20);	*/	} else {		/* back to 8 columns                    */		size_b0 = size8;		memctl->memc_mamr = CFG_MAMR_8COL;		udelay (500);/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB/n", size >> 20);	*/	}	udelay (1000);	/*	 * Adjust refresh rate depending on SDRAM type, both banks	 * For types > 128 MBit leave it at the current (fast) rate	 */	if ((size_b0 < 0x02000000)) {		/* reduce to 15.6 us (62.4 us / quad) */		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;		udelay (1000);	}	/* SDRAM Bank 0 is bigger - map first       */	memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;	memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;	udelay (10000);	return (size_b0);}

phys_size_t initdram (int board_type){    volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;    volatile memctl8xx_t *memctl = &immap->im_memctl;    long int size8, size9;    long int size_b0 = 0;    unsigned long reg;    upmconfig (UPMA, (uint *) sdram_table,               sizeof (sdram_table) / sizeof (uint));    /*     * Preliminary prescaler for refresh (depends on number of     * banks): This value is selected for four cycles every 62.4 us     * with two SDRAM banks or four cycles every 31.2 us with one     * bank. It will be adjusted after memory sizing.     */    memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;    memctl->memc_mar = 0x00000088;    /*     * Map controller bank 2 to the SDRAM bank at     * preliminary address - these have to be modified after the     * SDRAM size has been determined.     */    memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;    memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;    memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */    udelay (200);    /* perform SDRAM initializsation sequence */    memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */    udelay (200);    memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */    udelay (200);    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */    udelay (1000);    /*     * Check Bank 2 Memory Size for re-configuration     *     * try 8 column mode     */    size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,                       SDRAM_MAX_SIZE);    udelay (1000);    /*     * try 9 column mode     */    size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,                       SDRAM_MAX_SIZE);    if (size8 < size9) {		/* leave configuration at 9 columns */        size_b0 = size9;        /*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB/n", size >> 20);	*/    } else {			/* back to 8 columns            */        size_b0 = size8;        memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;        udelay (500);        /*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB/n", size >> 20);	*/    }    udelay (1000);    /*     * Adjust refresh rate depending on SDRAM type, both banks     * For types > 128 MBit leave it at the current (fast) rate     */    if ((size_b0 < 0x02000000)) {        /* reduce to 15.6 us (62.4 us / quad) */        memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;        udelay (1000);    }    /*     * Final mapping     */    memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;    memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;    /* adjust refresh rate depending on SDRAM type, one bank */    reg = memctl->memc_mptpr;    reg >>= 1;		/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */    memctl->memc_mptpr = reg;    udelay (10000);#ifdef CONFIG_CAN_DRIVER    /* Initialize OR3 / BR3 */    memctl->memc_or3 = CONFIG_SYS_OR3_CAN;		/* switch GPLB_5 to GPLA_5 */    memctl->memc_br3 = CONFIG_SYS_BR3_CAN;//.........这里部分代码省略.........

phys_size_t initdram(int board_type){	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	long int size;	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));	/*	 * Preliminary prescaler for refresh	 */	memctl->memc_mptpr = MPTPR_PTP_DIV8;	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */	/*	 * Map controller bank 3 to the SDRAM bank at preliminary address.	 */	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;	memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */	udelay(200);	/* perform SDRAM initialisation sequence */	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/	udelay(1);	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/	udelay(1);	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/	udelay(1);	memctl->memc_mbmr |= MAMR_PTAE;	/* enable refresh */	udelay(10000);	{		u32 d1, d2;		d1 = 0xAA55AA55;		*(volatile u32 *)0 = d1;		d2 = *(volatile u32 *)0;		if (d1 != d2) {			printf("DRAM fails: wrote 0x%08x read 0x%08x/n", d1, d2);			hang();		}		d1 = 0x55AA55AA;		*(volatile u32 *)0 = d1;		d2 = *(volatile u32 *)0;		if (d1 != d2) {			printf("DRAM fails: wrote 0x%08x read 0x%08x/n", d1, d2);			hang();		}	}	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);	if (size == 0) {		printf("SIZE is zero: LOOP on 0/n");		for (;;) {			*(volatile u32 *)0 = 0;			(void)*(volatile u32 *)0;		}	}	return size;}

phys_size_t initdram (int board_type){	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immr->im_memctl;	/* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */	long int size_b0;	long int size8, size9;	int i;	/*	 * Configure UPMB for SDRAM	 */	upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));	udelay(100);	memctl->memc_mptpr = CONFIG_SYS_MPTPR;	/* burst length=4, burst type=sequential, CAS latency=2 */	memctl->memc_mar = CONFIG_SYS_MAR;	/*	 * Map controller bank 1 to the SDRAM bank at preliminary address.	 */	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;	/* initialize memory address register */	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */	/* mode initialization (offset 5) */	udelay (200);				/* 0x80006105 */	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05);	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */	udelay (1);				/* 0x80006130 */	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);	udelay (1);				/* 0x80006130 */	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);	udelay (1);				/* 0x80006106 */	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06);	memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */	udelay (200);	/* Need at least 10 DRAM accesses to stabilize */	for (i = 0; i < 10; ++i) {		volatile unsigned long *addr =			(volatile unsigned long *) CONFIG_SYS_SDRAM_BASE;		unsigned long val;		val = *(addr + i);		*(addr + i) = val;	}	/*	 * Check Bank 0 Memory Size for re-configuration	 *	 * try 8 column mode	 */	size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);	udelay (1000);	/*	 * try 9 column mode	 */	size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);	if (size8 < size9) {		/* leave configuration at 9 columns */		size_b0 = size9;		memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL | MBMR_PTBE;		udelay (500);	} else {			/* back to 8 columns            */		size_b0 = size8;		memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;		udelay (500);	}	/*	 * Final mapping:	 */	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) |			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;	udelay (1000);	/* initalize the DSP Host Port Interface */	hpi_init();	/* FRAM Setup */	memctl->memc_or4 = CONFIG_SYS_OR4;	memctl->memc_br4 = CONFIG_SYS_BR4;	udelay(1000);	return (size_b0);}

phys_size_t initdram (int board_type){	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	long int size;	upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));	/*	* Prescaler for refresh	*/	memctl->memc_mptpr = 0x0400;	/*	* Map controller bank 2 to the SDRAM address	*/	memctl->memc_or2 = CONFIG_SYS_OR2;	memctl->memc_br2 = CONFIG_SYS_BR2;	udelay(200);	/* perform SDRAM initialization sequence */	memctl->memc_mbmr = CONFIG_SYS_16M_MBMR;	udelay(100);	memctl->memc_mar  = 0x00000088;	memctl->memc_mcr  = 0x80804105;	/* run precharge pattern */	udelay(1);	/* Run two refresh cycles on SDRAM */	memctl->memc_mbmr = 0x18802118;	memctl->memc_mcr  = 0x80804130;	memctl->memc_mbmr = 0x18802114;	memctl->memc_mcr  = 0x80804106;	udelay (1000);#if 0	/*	* Check for 64M SDRAM Memory Size	*/	size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE);	udelay (1000);	/*	* Check for 16M SDRAM Memory Size	*/	if (size != SDRAM_64M_MAX_SIZE) {#endif	size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);	udelay (1000);#if 0	}	memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;#endif	udelay(10000);#if 0	/*	* Also, map other memory to correct position	*/	/*	* Map the 8M Intel Flash device to chip select 1	*/	memctl->memc_or1 = CONFIG_SYS_OR1;	memctl->memc_br1 = CONFIG_SYS_BR1;	/*	* Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg	* to chip select 3	*/	memctl->memc_or3 = CONFIG_SYS_OR3;	memctl->memc_br3 = CONFIG_SYS_BR3;	/*	* Map chip selects 4, 5, 6, & 7 for external expansion connector	*/	memctl->memc_or4 = CONFIG_SYS_OR4;	memctl->memc_br4 = CONFIG_SYS_BR4;	memctl->memc_or5 = CONFIG_SYS_OR5;	memctl->memc_br5 = CONFIG_SYS_BR5;	memctl->memc_or6 = CONFIG_SYS_OR6;	memctl->memc_br6 = CONFIG_SYS_BR6;	memctl->memc_or7 = CONFIG_SYS_OR7;	memctl->memc_br7 = CONFIG_SYS_BR7;#endif	return (size);}

long int initdram (int board_type){	volatile immap_t *immap = (immap_t *) CFG_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	long int size8, size9;	long int size_b0 = 0;	/*	 * This sequence initializes SDRAM chips on ELPT860 board	 */	upmconfig (UPMA, (uint *) init_sdram_table,		   sizeof (init_sdram_table) / sizeof (uint));	memctl->memc_mptpr = 0x0200;	memctl->memc_mamr = 0x18002111;	memctl->memc_mar = 0x00000088;	memctl->memc_mcr = 0x80002000;	/* CS1: SDRAM bank 0 */	upmconfig (UPMA, (uint *) sdram_table,		   sizeof (sdram_table) / sizeof (uint));	/*	 * Preliminary prescaler for refresh (depends on number of	 * banks): This value is selected for four cycles every 62.4 us	 * with two SDRAM banks or four cycles every 31.2 us with one	 * bank. It will be adjusted after memory sizing.	 */	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;	/*	 * The following value is used as an address (i.e. opcode) for	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If	 * the port size is 32bit the SDRAM does NOT "see" the lower two	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for	 * MICRON SDRAMs:	 * ->    0 00 010 0 010	 *       |  |   | |   +- Burst Length = 4	 *       |  |   | +----- Burst Type   = Sequential	 *       |  |   +------- CAS Latency  = 2	 *       |  +----------- Operating Mode = Standard	 *       +-------------- Write Burst Mode = Programmed Burst Length	 */	memctl->memc_mar = 0x00000088;	/*	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at	 * preliminary addresses - these have to be modified after the	 * SDRAM size has been determined.	 */	memctl->memc_or1 = CFG_OR1_PRELIM;	memctl->memc_br1 = CFG_BR1_PRELIM;	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */	udelay (200);	/* perform SDRAM initializsation sequence */	memctl->memc_mcr = 0x80002105;	/* CS1: SDRAM bank 0 */	udelay (1);	memctl->memc_mcr = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */	udelay (1);	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */	udelay (1000);	/*	 * Check Bank 0 Memory Size for re-configuration	 *	 * try 8 column mode	 */	size8 = dram_size (CFG_MAMR_8COL,			   (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);	udelay (1000);	/*	 * try 9 column mode	 */	size9 = dram_size (CFG_MAMR_9COL,			   (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);	if (size8 < size9) {	/* leave configuration at 9 columns       */		size_b0 = size9;		/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB/n", size >> 20); */	} else {		/* back to 8 columns                      */		size_b0 = size8;		memctl->memc_mamr = CFG_MAMR_8COL;		udelay (500);		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB/n", size >> 20); */	}	udelay (1000);	/*	 * Adjust refresh rate depending on SDRAM type, both banks	 * For types > 128 MBit leave it at the current (fast) rate//.........这里部分代码省略.........

int checkboard (void){	unsigned char *s, *e;	unsigned char buf[64];	int i;	i = getenv_r("serial#", buf, sizeof(buf));	s = (i>0) ? buf : NULL;#ifdef CONFIG_QS850	if (!s || strncmp(s, "QS850", 5)) {		puts ("### No HW ID - assuming QS850");#endif#ifdef CONFIG_QS823	if (!s || strncmp(s, "QS823", 5)) {		puts ("### No HW ID - assuming QS823");#endif	} else {		for (e=s; *e; ++e) {		if (*e == ' ')		break;	}	for ( ; s<e; ++s) {		putc (*s);		}	}	putc ('/n');	return (0);}/* ------------------------------------------------------------------------- *//* SDRAM Mode Register Definitions *//* Set SDRAM Burst Length to 4 (010) *//* See Motorola MPC850 User Manual, Page 13-14 */#define SDRAM_BURST_LENGTH      (2)/* Set Wrap Type to Sequential (0) *//* See Motorola MPC850 User Manual, Page 13-14 */#define SDRAM_WRAP_TYPE         (0 << 3)/* Set /CAS Latentcy to 2 clocks */#define SDRAM_CAS_LATENTCY      (2 << 4)/* The Mode Register value must be shifted left by 2, since it is *//* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */#define SDRAM_MODE_REG  ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2)#define UPMA_RUN(loops,index)   (0x80002000 + (loops<<8) + index)/* Please note a value of zero = 16 loops */#define REFRESH_INIT_LOOPS (0)long int initdram (int board_type){	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	long int size;	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));	/*	* Prescaler for refresh	*/	memctl->memc_mptpr = CFG_MPTPR;	/*	* Map controller bank 1 to the SDRAM address	*/	memctl->memc_or1 = CFG_OR1;	memctl->memc_br1 = CFG_BR1;	udelay(1000);	/* perform SDRAM initialization sequence */	memctl->memc_mamr = CFG_16M_MAMR;	udelay(100);	/* Program the SDRAM's Mode Register */	memctl->memc_mar  = SDRAM_MODE_REG;	/* Run the Prechard Pattern at 0x3C */	memctl->memc_mcr  = UPMA_RUN(1,0x3c);	udelay(1);	/* Run the Refresh program residing at MAD index 0x30 */	/* This contains the CBR Refresh command with a loop */	/* The SDRAM must be refreshed at least 2 times */	/* Please note a value of zero = 16 loops */	memctl->memc_mcr  = UPMA_RUN(REFRESH_INIT_LOOPS,0x30);	udelay(1);	/* Run the Exception program residing at MAD index 0x3E */	/* This contains the Write Mode Register command */	/* The Write Mode Register command uses the value written to MAR */	memctl->memc_mcr  = UPMA_RUN(1,0x3e);	udelay (1000);//.........这里部分代码省略.........

long int initdram (int board_type){	volatile immap_t *immap = (immap_t *) CFG_IMMR;	volatile memctl8xx_t *memctl = &immap->im_memctl;	volatile iop8xx_t *iop = &immap->im_ioport;	volatile fec_t *fecp = &immap->im_cpm.cp_fec;	long int size;	upmconfig (UPMA, (uint *) sdram_table,		   sizeof (sdram_table) / sizeof (uint));	/*	 * Preliminary prescaler for refresh (depends on number of	 * banks): This value is selected for four cycles every 62.4 us	 * with two SDRAM banks or four cycles every 31.2 us with one	 * bank. It will be adjusted after memory sizing.	 */	memctl->memc_mptpr = CFG_MPTPR;	memctl->memc_mar = 0x00000088;	/*	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at	 * preliminary addresses - these have to be modified after the	 * SDRAM size has been determined.	 */	memctl->memc_or2 = CFG_OR2_PRELIM;	memctl->memc_br2 = CFG_BR2_PRELIM;	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */	udelay (200);	/* perform SDRAM initializsation sequence */	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */	udelay (1);	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */	udelay (1);	memctl->memc_mcr = 0x80004105;	/* SDRAM precharge */	udelay (1);	memctl->memc_mcr = 0x80004030;	/* SDRAM 16x autorefresh */	udelay (1);	memctl->memc_mcr = 0x80004138;	/* SDRAM upload parameters */	udelay (1);	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */	udelay (1000);	/*	 * Check Bank 0 Memory Size for re-configuration	 *	 */	size = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE_PRELIM,			  SDRAM_MAX_SIZE);	udelay (1000);	memctl->memc_mamr = CFG_MAMR;	udelay (1000);	/*	 * Final mapping	 */	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;	memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);	udelay (10000);	/* prepare pin multiplexing for fast ethernet */	atmLoad ();	fecp->fec_ecntrl = 0x00000004;	/* rev D3 pinmux SET */	iop->iop_pdpar |= 0x0080;	/* set pin as MII_clock */	return (size);}

ulong fpga_control (fpga_t* fpga, int cmd){    volatile immap_t     *immr  = (immap_t *)CONFIG_SYS_IMMR;    volatile memctl8xx_t *memctl = &immr->im_memctl;    switch (cmd) {    case FPGA_INIT_IS_HIGH:	immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */	return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0;    case FPGA_INIT_SET_LOW:	immr->im_ioport.iop_pcdir |=  fpga->init_mask; /* output */	immr->im_ioport.iop_pcdat &= ~fpga->init_mask;	break;    case FPGA_INIT_SET_HIGH:	immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */	immr->im_ioport.iop_pcdat |= fpga->init_mask;	break;    case FPGA_PROG_SET_LOW:	immr->im_ioport.iop_pcdat &= ~fpga->prog_mask;	break;    case FPGA_PROG_SET_HIGH:	immr->im_ioport.iop_pcdat |= fpga->prog_mask;	break;    case FPGA_DONE_IS_HIGH:	return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0;    case FPGA_READ_MODE:	/* disable FPGA in memory controller */	memctl->memc_br4 = 0;	memctl->memc_or4 = PUMA_CONF_OR_READ;	memctl->memc_br4 = PUMA_CONF_BR_READ;	/* (re-) enable CAN drivers */	can_driver_enable ();	break;    case FPGA_LOAD_MODE:	/* disable FPGA in memory controller */	memctl->memc_br4 = 0;	/*	 * We must disable the CAN drivers first because	 * they use UPM B, too.	 */	can_driver_disable ();	/*	 * Configure UPMB for FPGA	 */	upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));	memctl->memc_or4 = PUMA_CONF_OR_LOAD;	memctl->memc_br4 = PUMA_CONF_BR_LOAD;	break;    case FPGA_GET_ID:	return *(volatile ulong *)fpga->conf_base;    case FPGA_INIT_PORTS:	immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */	immr->im_ioport.iop_pcso  &= ~fpga->init_mask;	immr->im_ioport.iop_pcdir &= ~fpga->init_mask;	immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */	immr->im_ioport.iop_pcso  &= ~fpga->prog_mask;	immr->im_ioport.iop_pcdir |=  fpga->prog_mask;	immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */	immr->im_ioport.iop_pcso  &= ~fpga->done_mask;	immr->im_ioport.iop_pcdir &= ~fpga->done_mask;	break;    }    return 0;}