自学教程：C++ util_max_layer函数代码示例

void r600_decompress_depth_textures(struct r600_context *rctx,			       struct r600_samplerview_state *textures){	unsigned i;	unsigned depth_texture_mask = textures->compressed_depthtex_mask;	while (depth_texture_mask) {		struct pipe_sampler_view *view;		struct r600_texture *tex;		i = u_bit_scan(&depth_texture_mask);		view = &textures->views[i]->base;		assert(view);		tex = (struct r600_texture *)view->texture;		assert(tex->is_depth && !tex->is_flushing_texture);		if (rctx->b.chip_class >= EVERGREEN ||		    r600_can_read_depth(tex)) {			r600_blit_decompress_depth_in_place(rctx, tex,						   view->u.tex.first_level, view->u.tex.last_level,						   0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));		} else {			r600_blit_decompress_depth(&rctx->b.b, tex, NULL,						   view->u.tex.first_level, view->u.tex.last_level,						   0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),						   0, u_max_sample(&tex->resource.b.b));		}	}}

static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,						struct pipe_resource *texture,						const struct pipe_surface *surf_tmpl){	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;	struct r600_surface *surface = CALLOC_STRUCT(r600_surface);	unsigned level = surf_tmpl->u.tex.level;	assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));	assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));	assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);	if (surface == NULL)		return NULL;	/* XXX no offset *//*	offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/	pipe_reference_init(&surface->base.reference, 1);	pipe_resource_reference(&surface->base.texture, texture);	surface->base.context = pipe;	surface->base.format = surf_tmpl->format;	surface->base.width = rtex->surface.level[level].npix_x;	surface->base.height = rtex->surface.level[level].npix_y;	surface->base.texture = texture;	surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;	surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;	surface->base.u.tex.level = level;	return &surface->base;}

void r600_decompress_depth_textures(struct r600_context *rctx,                                    struct r600_samplerview_state *textures){    unsigned i;    unsigned depth_texture_mask = textures->compressed_depthtex_mask;    while (depth_texture_mask) {        struct pipe_sampler_view *view;        struct r600_pipe_sampler_view *rview;        struct r600_texture *tex;        i = u_bit_scan(&depth_texture_mask);        view = &textures->views[i]->base;        assert(view);        rview = (struct r600_pipe_sampler_view*)view;        tex = (struct r600_texture *)view->texture;        assert(tex->db_compatible);        if (r600_can_sample_zs(tex, rview->is_stencil_sampler)) {            r600_blit_decompress_depth_in_place(rctx, tex,                                                rview->is_stencil_sampler,                                                view->u.tex.first_level, view->u.tex.last_level,                                                0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));        } else {            r600_blit_decompress_depth(&rctx->b.b, tex, NULL,                                       view->u.tex.first_level, view->u.tex.last_level,                                       0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),                                       0, u_max_sample(&tex->resource.b.b));        }    }}

static bool do_hardware_msaa_resolve(struct pipe_context *ctx,				     const struct pipe_blit_info *info){	struct si_context *sctx = (struct si_context*)ctx;	struct r600_texture *dst = (struct r600_texture*)info->dst.resource;	unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);	unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);	enum pipe_format format = int_to_norm_format(info->dst.format);	unsigned sample_mask = ~0;	/* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and	 * the format is R16G16. Use R16A16, which does work.	 */	if (format == PIPE_FORMAT_R16G16_UNORM)		format = PIPE_FORMAT_R16A16_UNORM;	if (format == PIPE_FORMAT_R16G16_SNORM)		format = PIPE_FORMAT_R16A16_SNORM;	if (info->src.resource->nr_samples > 1 &&	    info->dst.resource->nr_samples <= 1 &&	    util_max_layer(info->src.resource, 0) == 0 &&	    util_max_layer(info->dst.resource, info->dst.level) == 0 &&	    util_is_format_compatible(util_format_description(info->src.format),				      util_format_description(info->dst.format)) &&	    !util_format_is_pure_integer(format) &&	    !util_format_is_depth_or_stencil(format) &&	    !info->scissor_enable &&	    (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&	    dst_width == info->src.resource->width0 &&	    dst_height == info->src.resource->height0 &&	    info->dst.box.x == 0 &&	    info->dst.box.y == 0 &&	    info->dst.box.width == dst_width &&	    info->dst.box.height == dst_height &&	    info->dst.box.depth == 1 &&	    info->src.box.x == 0 &&	    info->src.box.y == 0 &&	    info->src.box.width == dst_width &&	    info->src.box.height == dst_height &&	    info->src.box.depth == 1 &&	    dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&	    !(dst->surface.flags & RADEON_SURF_SCANOUT) &&	    (!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be fast-cleared */	    !dst->dcc_offset) {		si_blitter_begin(ctx, SI_COLOR_RESOLVE |				 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));		util_blitter_custom_resolve_color(sctx->blitter,						  info->dst.resource, info->dst.level,						  info->dst.box.z,						  info->src.resource, info->src.box.z,						  sample_mask, sctx->custom_blend_resolve,						  format);		si_blitter_end(ctx);		return true;	}	return false;}

static bool do_hardware_msaa_resolve(struct pipe_context *ctx,				     const struct pipe_blit_info *info){	struct r600_context *rctx = (struct r600_context*)ctx;	struct r600_texture *dst = (struct r600_texture*)info->dst.resource;	unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);	unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);	enum pipe_format format = int_to_norm_format(info->dst.format);	unsigned sample_mask =		rctx->b.chip_class == CAYMAN ? ~0 :		((1ull << MAX2(1, info->src.resource->nr_samples)) - 1);	if (info->src.resource->nr_samples > 1 &&	    info->dst.resource->nr_samples <= 1 &&	    util_max_layer(info->src.resource, 0) == 0 &&	    util_max_layer(info->dst.resource, info->dst.level) == 0 &&	    info->dst.format == info->src.format &&	    !util_format_is_pure_integer(format) &&	    !util_format_is_depth_or_stencil(format) &&	    !info->scissor_enable &&	    (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&	    dst_width == info->src.resource->width0 &&	    dst_height == info->src.resource->height0 &&	    info->dst.box.x == 0 &&	    info->dst.box.y == 0 &&	    info->dst.box.width == dst_width &&	    info->dst.box.height == dst_height &&	    info->dst.box.depth == 1 &&	    info->src.box.x == 0 &&	    info->src.box.y == 0 &&	    info->src.box.width == dst_width &&	    info->src.box.height == dst_height &&	    info->src.box.depth == 1 &&	    dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&	    (!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) {		r600_blitter_begin(ctx, R600_COLOR_RESOLVE |				   (info->render_condition_enable ? 0 : R600_DISABLE_RENDER_COND));		util_blitter_custom_resolve_color(rctx->blitter,						  info->dst.resource, info->dst.level,						  info->dst.box.z,						  info->src.resource, info->src.box.z,						  sample_mask, rctx->custom_blend_resolve,						  format);		r600_blitter_end(ctx);		return true;	}	return false;}

void WINAPINineBaseTexture9_GenerateMipSubLevels( struct NineBaseTexture9 *This ){    struct pipe_resource *resource = This->base.resource;    unsigned base_level = 0;    unsigned last_level = This->base.info.last_level - This->lod;    unsigned first_layer = 0;    unsigned last_layer;    unsigned filter = This->mipfilter == D3DTEXF_POINT ? PIPE_TEX_FILTER_NEAREST                                                       : PIPE_TEX_FILTER_LINEAR;    DBG("This=%p/n", This);    if (This->base.pool == D3DPOOL_MANAGED)        NineBaseTexture9_UploadSelf(This);    if (!This->dirty_mip)        return;    if (This->lod) {        ERR("AUTOGENMIPMAP if level 0 is not resident not supported yet !/n");        return;    }    if (!This->view[0])        NineBaseTexture9_UpdateSamplerView(This, 0);    last_layer = util_max_layer(This->view[0]->texture, base_level);    util_gen_mipmap(This->pipe, resource,                    resource->format, base_level, last_level,                    first_layer, last_layer, filter);    This->dirty_mip = FALSE;    NineDevice9_RestoreNonCSOState(This->base.base.device, ~0x3);}

static void si_flush_resource(struct pipe_context *ctx,			      struct pipe_resource *res){	struct r600_texture *rtex = (struct r600_texture*)res;	assert(res->target != PIPE_BUFFER);	assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);	/* st/dri calls flush twice per frame (not a bug), this prevents double	 * decompression. */	if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)		return;	if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {		si_blit_decompress_color(ctx, rtex, 0, res->last_level,					 0, util_max_layer(res, 0),					 rtex->dcc_separate_buffer != NULL);	}	/* Always do the analysis even if DCC is disabled at the moment. */	if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {		rtex->separate_dcc_dirty = false;		vi_separate_dcc_process_and_reset_stats(ctx, rtex);	}}

static voidsi_flush_depth_textures(struct si_context *sctx,			struct si_textures_info *textures){	unsigned i;	unsigned mask = textures->depth_texture_mask;	while (mask) {		struct pipe_sampler_view *view;		struct si_sampler_view *sview;		struct r600_texture *tex;		i = u_bit_scan(&mask);		view = textures->views.views[i];		assert(view);		sview = (struct si_sampler_view*)view;		tex = (struct r600_texture *)view->texture;		assert(tex->is_depth && !tex->is_flushing_texture);		si_blit_decompress_zs_in_place(sctx, tex,					       sview->is_stencil_sampler ? PIPE_MASK_S									 : PIPE_MASK_Z,					       view->u.tex.first_level, view->u.tex.last_level,					       0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));	}}

static voidsi_decompress_image_color_textures(struct si_context *sctx,				   struct si_images_info *images){	unsigned i;	unsigned mask = images->compressed_colortex_mask;	while (mask) {		const struct pipe_image_view *view;		struct r600_texture *tex;		i = u_bit_scan(&mask);		view = &images->views[i];		assert(view->resource->target != PIPE_BUFFER);		tex = (struct r600_texture *)view->resource;		if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)			continue;		si_blit_decompress_color(&sctx->b.b, tex,					 view->u.tex.level, view->u.tex.level,					 0, util_max_layer(&tex->resource.b.b, view->u.tex.level),					 false);	}}

static bool can_fast_clear_color(struct pipe_context *ctx){	struct r600_context *rctx = (struct r600_context *)ctx;	struct pipe_framebuffer_state *fb = &rctx->framebuffer.state;	int i;	if (rctx->b.chip_class < EVERGREEN) {		return false;	}	for (i = 0; i < fb->nr_cbufs; i++) {		struct r600_texture *tex = (struct r600_texture *)fb->cbufs[i]->texture;		if (tex->cmask_size == 0) {			return false;		}		/* 128-bit formats are unuspported */		if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {			return false;		}		/* the clear is allowed if all layers are bound */		if (fb->cbufs[i]->u.tex.first_layer != 0 ||		    fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {			return false;		}	}	return true;}

/** * Initialize the pipe_resource descriptor to be of the same size as the box, * which is supposed to hold a subregion of the texture "orig" at the given * mipmap level. */static void r600_init_temp_resource_from_box(struct pipe_resource *res,					     struct pipe_resource *orig,					     const struct pipe_box *box,					     unsigned level, unsigned flags){	memset(res, 0, sizeof(*res));	res->format = orig->format;	res->width0 = box->width;	res->height0 = box->height;	res->depth0 = 1;	res->array_size = 1;	res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;	res->flags = flags;	/* We must set the correct texture target and dimensions for a 3D box. */	if (box->depth > 1 && util_max_layer(orig, level) > 0)		res->target = orig->target;	else		res->target = PIPE_TEXTURE_2D;	switch (res->target) {	case PIPE_TEXTURE_1D_ARRAY:	case PIPE_TEXTURE_2D_ARRAY:	case PIPE_TEXTURE_CUBE_ARRAY:		res->array_size = box->depth;		break;	case PIPE_TEXTURE_3D:		res->depth0 = box->depth;		break;	default:;	}}

void NINE_WINAPINineBaseTexture9_GenerateMipSubLevels( struct NineBaseTexture9 *This ){    unsigned base_level = 0;    unsigned last_level = This->base.info.last_level - This->managed.lod;    unsigned first_layer = 0;    unsigned last_layer;    unsigned filter = This->mipfilter == D3DTEXF_POINT ? PIPE_TEX_FILTER_NEAREST                                                       : PIPE_TEX_FILTER_LINEAR;    DBG("This=%p/n", This);    if (This->base.pool == D3DPOOL_MANAGED)        NineBaseTexture9_UploadSelf(This);    if (!This->dirty_mip)        return;    if (This->managed.lod) {        ERR("AUTOGENMIPMAP if level 0 is not resident not supported yet !/n");        return;    }    if (!This->view[0])        NineBaseTexture9_UpdateSamplerView(This, 0);    last_layer = util_max_layer(This->view[0]->texture, base_level);    nine_context_gen_mipmap(This->base.base.device, (struct NineUnknown *)This,                            This->base.resource,                            base_level, last_level,                            first_layer, last_layer, filter);    This->dirty_mip = FALSE;}

void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,				 struct r600_texture *rtex,				 struct r600_cmask_info *out){	unsigned cmask_tile_width = 8;	unsigned cmask_tile_height = 8;	unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;	unsigned element_bits = 4;	unsigned cmask_cache_bits = 1024;	unsigned num_pipes = rscreen->tiling_info.num_channels;	unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;	unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;	unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;	unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);	unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);	unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;	unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);	unsigned height = align(rtex->surface.npix_y, macro_tile_height);	unsigned base_align = num_pipes * pipe_interleave_bytes;	unsigned slice_bytes =		((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;	assert(macro_tile_width % 128 == 0);	assert(macro_tile_height % 128 == 0);	out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;	out->alignment = MAX2(256, base_align);	out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *		    align(slice_bytes, base_align);}

static voidsi_decompress_sampler_color_textures(struct si_context *sctx,				     struct si_textures_info *textures){	unsigned i;	unsigned mask = textures->compressed_colortex_mask;	while (mask) {		struct pipe_sampler_view *view;		struct r600_texture *tex;		i = u_bit_scan(&mask);		view = textures->views.views[i];		assert(view);		tex = (struct r600_texture *)view->texture;		assert(tex->cmask.size || tex->fmask.size || tex->dcc_offset);		si_blit_decompress_color(&sctx->b.b, tex,					 view->u.tex.first_level, view->u.tex.last_level,					 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),					 false);	}}

static void r600_blit_decompress_depth_in_place(struct r600_context *rctx,                                                struct r600_texture *texture,						bool is_stencil_sampler,                                                unsigned first_level, unsigned last_level,                                                unsigned first_layer, unsigned last_layer){	struct pipe_surface *zsurf, surf_tmpl = {{0}};	unsigned layer, max_layer, checked_last_layer, level;	unsigned *dirty_level_mask;	/* Enable decompression in DB_RENDER_CONTROL */	if (is_stencil_sampler) {		rctx->db_misc_state.flush_stencil_inplace = true;		dirty_level_mask = &texture->stencil_dirty_level_mask;	} else {		rctx->db_misc_state.flush_depth_inplace = true;		dirty_level_mask = &texture->dirty_level_mask;	}	r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);	surf_tmpl.format = texture->resource.b.b.format;	for (level = first_level; level <= last_level; level++) {		if (!(*dirty_level_mask & (1 << level)))			continue;		surf_tmpl.u.tex.level = level;		/* The smaller the mipmap level, the less layers there are		 * as far as 3D textures are concerned. */		max_layer = util_max_layer(&texture->resource.b.b, level);		checked_last_layer = last_layer < max_layer ? last_layer : max_layer;		for (layer = first_layer; layer <= checked_last_layer; layer++) {			surf_tmpl.u.tex.first_layer = layer;			surf_tmpl.u.tex.last_layer = layer;			zsurf = rctx->b.b.create_surface(&rctx->b.b, &texture->resource.b.b, &surf_tmpl);			r600_blitter_begin(&rctx->b.b, R600_DECOMPRESS);			util_blitter_custom_depth_stencil(rctx->blitter, zsurf, NULL, ~0,							  rctx->custom_dsa_flush, 1.0f);			r600_blitter_end(&rctx->b.b);			pipe_surface_reference(&zsurf, NULL);		}		/* The texture will always be dirty if some layers or samples aren't flushed.		 * I don't think this case occurs often though. */		if (first_layer == 0 && last_layer == max_layer) {			*dirty_level_mask &= ~(1 << level);		}	}	/* Disable decompression in DB_RENDER_CONTROL */	rctx->db_misc_state.flush_depth_inplace = false;	rctx->db_misc_state.flush_stencil_inplace = false;	r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);}

static bool do_hardware_msaa_resolve(struct pipe_context *ctx,				     const struct pipe_blit_info *info){	struct si_context *sctx = (struct si_context*)ctx;	struct r600_texture *dst = (struct r600_texture*)info->dst.resource;	unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);	unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);	enum pipe_format format = int_to_norm_format(info->dst.format);	unsigned sample_mask = ~0;	if (info->src.resource->nr_samples > 1 &&	    info->dst.resource->nr_samples <= 1 &&	    util_max_layer(info->src.resource, 0) == 0 &&	    util_max_layer(info->dst.resource, info->dst.level) == 0 &&	    info->dst.format == info->src.format &&	    !util_format_is_pure_integer(format) &&	    !util_format_is_depth_or_stencil(format) &&	    !info->scissor_enable &&	    (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&	    dst_width == info->src.resource->width0 &&	    dst_height == info->src.resource->height0 &&	    info->dst.box.x == 0 &&	    info->dst.box.y == 0 &&	    info->dst.box.width == dst_width &&	    info->dst.box.height == dst_height &&	    info->dst.box.depth == 1 &&	    info->src.box.x == 0 &&	    info->src.box.y == 0 &&	    info->src.box.width == dst_width &&	    info->src.box.height == dst_height &&	    info->src.box.depth == 1 &&	    dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&	    !(dst->surface.flags & RADEON_SURF_SCANOUT)) {		si_blitter_begin(ctx, SI_COLOR_RESOLVE);		util_blitter_custom_resolve_color(sctx->blitter,						  info->dst.resource, info->dst.level,						  info->dst.box.z,						  info->src.resource, info->src.box.z,						  sample_mask, sctx->custom_blend_resolve,						  format);		si_blitter_end(ctx);		return true;	}	return false;}

static void si_blit_decompress_color(struct pipe_context *ctx,		struct r600_texture *rtex,		unsigned first_level, unsigned last_level,		unsigned first_layer, unsigned last_layer,		bool need_dcc_decompress){	struct si_context *sctx = (struct si_context *)ctx;	void* custom_blend;	unsigned layer, checked_last_layer, max_layer;	unsigned level_mask =		u_bit_consecutive(first_level, last_level - first_level + 1);	if (!need_dcc_decompress)		level_mask &= rtex->dirty_level_mask;	if (!level_mask)		return;	if (rtex->dcc_offset && need_dcc_decompress) {		custom_blend = sctx->custom_blend_dcc_decompress;	} else if (rtex->fmask.size) {		custom_blend = sctx->custom_blend_decompress;	} else {		custom_blend = sctx->custom_blend_fastclear;	}	while (level_mask) {		unsigned level = u_bit_scan(&level_mask);		/* The smaller the mipmap level, the less layers there are		 * as far as 3D textures are concerned. */		max_layer = util_max_layer(&rtex->resource.b.b, level);		checked_last_layer = MIN2(last_layer, max_layer);		for (layer = first_layer; layer <= checked_last_layer; layer++) {			struct pipe_surface *cbsurf, surf_tmpl;			surf_tmpl.format = rtex->resource.b.b.format;			surf_tmpl.u.tex.level = level;			surf_tmpl.u.tex.first_layer = layer;			surf_tmpl.u.tex.last_layer = layer;			cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);			si_blitter_begin(ctx, SI_DECOMPRESS);			util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);			si_blitter_end(ctx);			pipe_surface_reference(&cbsurf, NULL);		}		/* The texture will always be dirty if some layers aren't flushed.		 * I don't think this case occurs often though. */		if (first_layer == 0 && last_layer == max_layer) {			rtex->dirty_level_mask &= ~(1 << level);		}	}}

static void si_decompress_dcc(struct pipe_context *ctx,			      struct r600_texture *rtex){	if (!rtex->dcc_offset)		return;	si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,				 0, util_max_layer(&rtex->resource.b.b, 0),				 true);}

static void r600_flush_resource(struct pipe_context *ctx,				struct pipe_resource *res){	struct r600_texture *rtex = (struct r600_texture*)res;	assert(res->target != PIPE_BUFFER);	if (!rtex->is_depth && rtex->cmask.size) {		r600_blit_decompress_color(ctx, rtex, 0, res->last_level,					   0, util_max_layer(res, 0));	}}

struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,						struct pipe_resource *texture,						const struct pipe_surface *templ,						unsigned width, unsigned height){	struct r600_surface *surface = CALLOC_STRUCT(r600_surface);	if (surface == NULL)		return NULL;	assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));	assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));	pipe_reference_init(&surface->base.reference, 1);	pipe_resource_reference(&surface->base.texture, texture);	surface->base.context = pipe;	surface->base.format = templ->format;	surface->base.width = width;	surface->base.height = height;	surface->base.u = templ->u;	return &surface->base;}

static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,				      struct r600_texture *rtex,				      struct r600_cmask_info *out){	unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;	unsigned num_pipes = rscreen->tiling_info.num_channels;	unsigned cl_width, cl_height;	switch (num_pipes) {	case 2:		cl_width = 32;		cl_height = 16;		break;	case 4:		cl_width = 32;		cl_height = 32;		break;	case 8:		cl_width = 64;		cl_height = 32;		break;	case 16: /* Hawaii */		cl_width = 64;		cl_height = 64;		break;	default:		assert(0);		return;	}	unsigned base_align = num_pipes * pipe_interleave_bytes;	unsigned width = align(rtex->surface.npix_x, cl_width*8);	unsigned height = align(rtex->surface.npix_y, cl_height*8);	unsigned slice_elements = (width * height) / (8*8);	/* Each element of CMASK is a nibble. */	unsigned slice_bytes = slice_elements / 2;	out->pitch = width;	out->height = height;	out->xalign = cl_width * 8;	out->yalign = cl_height * 8;	out->slice_tile_max = (width * height) / (128*128);	if (out->slice_tile_max)		out->slice_tile_max -= 1;	out->alignment = MAX2(256, base_align);	out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *		    align(slice_bytes, base_align);}

static void si_blit_decompress_depth_in_place(struct si_context *sctx,                                              struct r600_texture *texture,                                              unsigned first_level, unsigned last_level,                                              unsigned first_layer, unsigned last_layer){	struct pipe_surface *zsurf, surf_tmpl = {{0}};	unsigned layer, max_layer, checked_last_layer, level;	sctx->db_inplace_flush_enabled = true;	si_mark_atom_dirty(sctx, &sctx->db_render_state);	surf_tmpl.format = texture->resource.b.b.format;	for (level = first_level; level <= last_level; level++) {		if (!(texture->dirty_level_mask & (1 << level)))			continue;		surf_tmpl.u.tex.level = level;		/* The smaller the mipmap level, the less layers there are		 * as far as 3D textures are concerned. */		max_layer = util_max_layer(&texture->resource.b.b, level);		checked_last_layer = last_layer < max_layer ? last_layer : max_layer;		for (layer = first_layer; layer <= checked_last_layer; layer++) {			surf_tmpl.u.tex.first_layer = layer;			surf_tmpl.u.tex.last_layer = layer;			zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);			si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);			util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,							  sctx->custom_dsa_flush,							  1.0f);			si_blitter_end(&sctx->b.b);			pipe_surface_reference(&zsurf, NULL);		}		/* The texture will always be dirty if some layers aren't flushed.		 * I don't think this case occurs often though. */		if (first_layer == 0 && last_layer == max_layer) {			texture->dirty_level_mask &= ~(1 << level);		}	}	sctx->db_inplace_flush_enabled = false;	si_mark_atom_dirty(sctx, &sctx->db_render_state);}

static void si_blit_decompress_color(struct pipe_context *ctx,		struct r600_texture *rtex,		unsigned first_level, unsigned last_level,		unsigned first_layer, unsigned last_layer){	struct si_context *sctx = (struct si_context *)ctx;	unsigned layer, level, checked_last_layer, max_layer;	if (!rtex->dirty_level_mask)		return;	for (level = first_level; level <= last_level; level++) {		if (!(rtex->dirty_level_mask & (1 << level)))			continue;		/* The smaller the mipmap level, the less layers there are		 * as far as 3D textures are concerned. */		max_layer = util_max_layer(&rtex->resource.b.b, level);		checked_last_layer = last_layer < max_layer ? last_layer : max_layer;		for (layer = first_layer; layer <= checked_last_layer; layer++) {			struct pipe_surface *cbsurf, surf_tmpl;			surf_tmpl.format = rtex->resource.b.b.format;			surf_tmpl.u.tex.level = level;			surf_tmpl.u.tex.first_layer = layer;			surf_tmpl.u.tex.last_layer = layer;			cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);			si_blitter_begin(ctx, SI_DECOMPRESS);			util_blitter_custom_color(sctx->blitter, cbsurf,				rtex->fmask.size ? sctx->custom_blend_decompress :						   sctx->custom_blend_fastclear);			si_blitter_end(ctx);			pipe_surface_reference(&cbsurf, NULL);		}		/* The texture will always be dirty if some layers aren't flushed.		 * I don't think this case occurs often though. */		if (first_layer == 0 && last_layer == max_layer) {			rtex->dirty_level_mask &= ~(1 << level);		}	}}

void si_flush_depth_textures(struct r600_context *rctx,			     struct r600_textures_info *textures){	unsigned i;	for (i = 0; i < textures->n_views; ++i) {		struct pipe_sampler_view *view;		struct r600_texture *tex;		view = textures->views.views[i];		if (!view) continue;		tex = (struct r600_texture *)view->texture;		if (!tex->is_depth || tex->is_flushing_texture)			continue;		si_blit_decompress_depth_in_place(rctx, tex,						  view->u.tex.first_level, view->u.tex.last_level,						  0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));	}}

void r600_decompress_color_textures(struct r600_context *rctx,				    struct r600_samplerview_state *textures){	unsigned i;	unsigned mask = textures->compressed_colortex_mask;	while (mask) {		struct pipe_sampler_view *view;		struct r600_texture *tex;		i = u_bit_scan(&mask);		view = &textures->views[i]->base;		assert(view);		tex = (struct r600_texture *)view->texture;		assert(tex->cmask.size);		r600_blit_decompress_color(&rctx->b.b, tex,					   view->u.tex.first_level, view->u.tex.last_level,					   0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));	}}

/** * Called via ctx->Driver.GenerateMipmap(). */voidst_generate_mipmap(struct gl_context *ctx, GLenum target,                   struct gl_texture_object *texObj){   struct st_context *st = st_context(ctx);   struct st_texture_object *stObj = st_texture_object(texObj);   struct pipe_resource *pt = st_get_texobj_resource(texObj);   const uint baseLevel = texObj->BaseLevel;   uint lastLevel, first_layer, last_layer;   uint dstLevel;   if (!pt)      return;   /* not sure if this ultimately actually should work,      but we're not supporting multisampled textures yet. */   assert(pt->nr_samples < 2);   /* find expected last mipmap level to generate*/   lastLevel = compute_num_levels(ctx, texObj, target) - 1;   if (lastLevel == 0)      return;   /* The texture isn't in a "complete" state yet so set the expected    * lastLevel here, since it won't get done in st_finalize_texture().    */   stObj->lastLevel = lastLevel;   if (pt->last_level < lastLevel) {      /* The current gallium texture doesn't have space for all the       * mipmap levels we need to generate.  So allocate a new texture.       */      struct pipe_resource *oldTex = stObj->pt;      /* create new texture with space for more levels */      stObj->pt = st_texture_create(st,                                    oldTex->target,                                    oldTex->format,                                    lastLevel,                                    oldTex->width0,                                    oldTex->height0,                                    oldTex->depth0,                                    oldTex->array_size,                                    0,                                    oldTex->bind);      /* This will copy the old texture's base image into the new texture       * which we just allocated.       */      st_finalize_texture(ctx, st->pipe, texObj);      /* release the old tex (will likely be freed too) */      pipe_resource_reference(&oldTex, NULL);      st_texture_release_all_sampler_views(stObj);   }   else {      /* Make sure that the base texture image data is present in the       * texture buffer.       */      st_finalize_texture(ctx, st->pipe, texObj);   }   pt = stObj->pt;   assert(pt->last_level >= lastLevel);   if (pt->target == PIPE_TEXTURE_CUBE) {      first_layer = last_layer = _mesa_tex_target_to_face(target);   }   else {      first_layer = 0;      last_layer = util_max_layer(pt, baseLevel);   }   /* Try to generate the mipmap by rendering/texturing.  If that fails,    * use the software fallback.    */   if (!util_gen_mipmap(st->pipe, pt, pt->format, baseLevel, lastLevel,                        first_layer, last_layer, PIPE_TEX_FILTER_LINEAR)) {      _mesa_generate_mipmap(ctx, target, texObj);   }   /* Fill in the Mesa gl_texture_image fields */   for (dstLevel = baseLevel + 1; dstLevel <= lastLevel; dstLevel++) {      const uint srcLevel = dstLevel - 1;      const struct gl_texture_image *srcImage         = _mesa_get_tex_image(ctx, texObj, target, srcLevel);      struct gl_texture_image *dstImage;      struct st_texture_image *stImage;      uint border = srcImage->Border;      uint dstWidth, dstHeight, dstDepth;      dstWidth = u_minify(pt->width0, dstLevel);      if (texObj->Target == GL_TEXTURE_1D_ARRAY) {         dstHeight = pt->array_size;      }//.........这里部分代码省略.........

/* Common processing for r600_texture_create and r600_texture_from_handle */static struct r600_texture *r600_texture_create_object(struct pipe_screen *screen,			   const struct pipe_resource *base,			   unsigned pitch_in_bytes_override,			   struct pb_buffer *buf,			   struct radeon_surf *surface){	struct r600_texture *rtex;	struct r600_resource *resource;	struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;	rtex = CALLOC_STRUCT(r600_texture);	if (rtex == NULL)		return NULL;	resource = &rtex->resource;	resource->b.b = *base;	resource->b.vtbl = &r600_texture_vtbl;	pipe_reference_init(&resource->b.b.reference, 1);	resource->b.b.screen = screen;	rtex->pitch_override = pitch_in_bytes_override;	/* don't include stencil-only formats which we don't support for rendering */	rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));	rtex->surface = *surface;	if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {		FREE(rtex);		return NULL;	}	/* Tiled depth textures utilize the non-displayable tile order.	 * This must be done after r600_setup_surface.	 * Applies to R600-Cayman. */	rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;	if (rtex->is_depth) {		if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |				     R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&		    !(rscreen->debug_flags & DBG_NO_HYPERZ)) {			r600_texture_allocate_htile(rscreen, rtex);		}	} else {		if (base->nr_samples > 1) {			if (!buf) {				r600_texture_allocate_fmask(rscreen, rtex);				r600_texture_allocate_cmask(rscreen, rtex);				rtex->cmask_buffer = &rtex->resource;			}			if (!rtex->fmask.size || !rtex->cmask.size) {				FREE(rtex);				return NULL;			}		}	}	/* Now create the backing buffer. */	if (!buf) {		if (!r600_init_resource(rscreen, resource, rtex->size,					rtex->surface.bo_alignment, TRUE)) {			FREE(rtex);			return NULL;		}	} else {		resource->buf = buf;		resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);		resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->cs_buf);		resource->domains = rscreen->ws->buffer_get_initial_domain(resource->cs_buf);	}	if (rtex->cmask.size) {		/* Initialize the cmask to 0xCC (= compressed state). */		r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,					 rtex->cmask.offset, rtex->cmask.size,					 0xCCCCCCCC, true);	}	/* Initialize the CMASK base register value. */	rtex->cmask.base_address_reg =		(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;	if (rscreen->debug_flags & DBG_VM) {		fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s/n",			rtex->resource.gpu_address,			rtex->resource.gpu_address + rtex->resource.buf->size,			base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,			base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));	}	if (rscreen->debug_flags & DBG_TEX ||	    (rtex->resource.b.b.last_level > 0 && rscreen->debug_flags & DBG_TEXMIP)) {		printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "		       "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "		       "bpe=%u, nsamples=%u, flags=0x%x, %s/n",		       rtex->surface.npix_x, rtex->surface.npix_y,		       rtex->surface.npix_z, rtex->surface.blk_w,		       rtex->surface.blk_h, rtex->surface.blk_d,		       rtex->surface.array_size, rtex->surface.last_level,//.........这里部分代码省略.........

/** * Create or update the pipe_surface of a FBO renderbuffer. * This is usually called after st_finalize_texture. */voidst_update_renderbuffer_surface(struct st_context *st,                               struct st_renderbuffer *strb){   struct pipe_context *pipe = st->pipe;   struct pipe_resource *resource = strb->texture;   int rtt_width = strb->Base.Width;   int rtt_height = strb->Base.Height;   int rtt_depth = strb->Base.Depth;   /*    * For winsys fbo, it is possible that the renderbuffer is sRGB-capable but    * the format of strb->texture is linear (because we have no control over    * the format).  Check strb->Base.Format instead of strb->texture->format    * to determine if the rb is sRGB-capable.    */   boolean enable_srgb = (st->ctx->Color.sRGBEnabled &&         _mesa_get_format_color_encoding(strb->Base.Format) == GL_SRGB);   enum pipe_format format = (enable_srgb) ?      util_format_srgb(resource->format) :      util_format_linear(resource->format);   unsigned first_layer, last_layer, level;   if (resource->target == PIPE_TEXTURE_1D_ARRAY) {      rtt_depth = rtt_height;      rtt_height = 1;   }   /* find matching mipmap level size */   for (level = 0; level <= resource->last_level; level++) {      if (u_minify(resource->width0, level) == rtt_width &&          u_minify(resource->height0, level) == rtt_height &&          (resource->target != PIPE_TEXTURE_3D ||           u_minify(resource->depth0, level) == rtt_depth)) {         break;      }   }   assert(level <= resource->last_level);   /* determine the layer bounds */   if (strb->rtt_layered) {      first_layer = 0;      last_layer = util_max_layer(strb->texture, level);   }   else {      first_layer =      last_layer = strb->rtt_face + strb->rtt_slice;   }   if (!strb->surface ||       strb->surface->texture->nr_samples != strb->Base.NumSamples ||       strb->surface->format != format ||       strb->surface->texture != resource ||       strb->surface->width != rtt_width ||       strb->surface->height != rtt_height ||       strb->surface->u.tex.level != level ||       strb->surface->u.tex.first_layer != first_layer ||       strb->surface->u.tex.last_layer != last_layer) {      /* create a new pipe_surface */      struct pipe_surface surf_tmpl;      memset(&surf_tmpl, 0, sizeof(surf_tmpl));      surf_tmpl.format = format;      surf_tmpl.u.tex.level = level;      surf_tmpl.u.tex.first_layer = first_layer;      surf_tmpl.u.tex.last_layer = last_layer;      pipe_surface_reference(&strb->surface, NULL);      strb->surface = pipe->create_surface(pipe, resource, &surf_tmpl);   }}

static void r600_clear(struct pipe_context *ctx, unsigned buffers,		       const union pipe_color_union *color,		       double depth, unsigned stencil){	struct r600_context *rctx = (struct r600_context *)ctx;	struct pipe_framebuffer_state *fb = &rctx->framebuffer.state;	if (buffers & PIPE_CLEAR_COLOR && rctx->b.chip_class >= EVERGREEN) {		evergreen_do_fast_color_clear(&rctx->b, fb, &rctx->framebuffer.atom,					      &buffers, color);	}	if (buffers & PIPE_CLEAR_COLOR) {		int i;		/* These buffers cannot use fast clear, make sure to disable expansion. */		for (i = 0; i < fb->nr_cbufs; i++) {			struct r600_texture *tex;			/* If not clearing this buffer, skip. */			if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))				continue;			if (!fb->cbufs[i])				continue;			tex = (struct r600_texture *)fb->cbufs[i]->texture;			if (tex->fmask.size == 0)				tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);		}	}	/* if hyperz enabled just clear hyperz */	if (fb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {		struct r600_texture *rtex;		unsigned level = fb->zsbuf->u.tex.level;		rtex = (struct r600_texture*)fb->zsbuf->texture;		/* We can't use hyperz fast clear if each slice of a texture		 * array are clear to different value. To simplify code just		 * disable fast clear for texture array.		 */		/* Only use htile for first level */		if (rtex->htile_buffer && !level &&		    util_max_layer(&rtex->resource.b.b, level) == 0) {			if (rtex->depth_clear_value != depth) {				rtex->depth_clear_value = depth;				rctx->db_state.atom.dirty = true;			}			rctx->db_misc_state.htile_clear = true;			rctx->db_misc_state.atom.dirty = true;		}	}	r600_blitter_begin(ctx, R600_CLEAR);	util_blitter_clear(rctx->blitter, fb->width, fb->height,			   util_framebuffer_get_num_layers(fb),			   buffers, color, depth, stencil);	r600_blitter_end(ctx);	/* disable fast clear */	if (rctx->db_misc_state.htile_clear) {		rctx->db_misc_state.htile_clear = false;		rctx->db_misc_state.atom.dirty = true;	}}

static void r600_blit_decompress_depth(struct pipe_context *ctx,				       struct r600_texture *texture,				       struct r600_texture *staging,				       unsigned first_level, unsigned last_level,				       unsigned first_layer, unsigned last_layer,				       unsigned first_sample, unsigned last_sample){	struct r600_context *rctx = (struct r600_context *)ctx;	unsigned layer, level, sample, checked_last_layer, max_layer, max_sample;	struct r600_texture *flushed_depth_texture = staging ?			staging : texture->flushed_depth_texture;	const struct util_format_description *desc =		util_format_description(texture->resource.b.b.format);	float depth;	if (!staging && !texture->dirty_level_mask)		return;	max_sample = u_max_sample(&texture->resource.b.b);	/* XXX Decompressing MSAA depth textures is broken on R6xx.	 * There is also a hardlock if CMASK and FMASK are not present.	 * Just skip this until we find out how to fix it. */	if (rctx->b.chip_class == R600 && max_sample > 0) {		texture->dirty_level_mask = 0;		return;	}	if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||	    rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)		depth = 0.0f;	else		depth = 1.0f;	/* Enable decompression in DB_RENDER_CONTROL */	rctx->db_misc_state.flush_depthstencil_through_cb = true;	rctx->db_misc_state.copy_depth = util_format_has_depth(desc);	rctx->db_misc_state.copy_stencil = util_format_has_stencil(desc);	rctx->db_misc_state.copy_sample = first_sample;	rctx->db_misc_state.atom.dirty = true;	for (level = first_level; level <= last_level; level++) {		if (!staging && !(texture->dirty_level_mask & (1 << level)))			continue;		/* The smaller the mipmap level, the less layers there are		 * as far as 3D textures are concerned. */		max_layer = util_max_layer(&texture->resource.b.b, level);		checked_last_layer = last_layer < max_layer ? last_layer : max_layer;		for (layer = first_layer; layer <= checked_last_layer; layer++) {			for (sample = first_sample; sample <= last_sample; sample++) {				struct pipe_surface *zsurf, *cbsurf, surf_tmpl;				if (sample != rctx->db_misc_state.copy_sample) {					rctx->db_misc_state.copy_sample = sample;					rctx->db_misc_state.atom.dirty = true;				}				surf_tmpl.format = texture->resource.b.b.format;				surf_tmpl.u.tex.level = level;				surf_tmpl.u.tex.first_layer = layer;				surf_tmpl.u.tex.last_layer = layer;				zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl);				surf_tmpl.format = flushed_depth_texture->resource.b.b.format;				cbsurf = ctx->create_surface(ctx,						&flushed_depth_texture->resource.b.b, &surf_tmpl);				r600_blitter_begin(ctx, R600_DECOMPRESS);				util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, 1 << sample,								  rctx->custom_dsa_flush, depth);				r600_blitter_end(ctx);				pipe_surface_reference(&zsurf, NULL);				pipe_surface_reference(&cbsurf, NULL);			}		}		/* The texture will always be dirty if some layers or samples aren't flushed.		 * I don't think this case occurs often though. */		if (!staging &&		    first_layer == 0 && last_layer == max_layer &&		    first_sample == 0 && last_sample == max_sample) {			texture->dirty_level_mask &= ~(1 << level);		}	}	/* reenable compression in DB_RENDER_CONTROL */	rctx->db_misc_state.flush_depthstencil_through_cb = false;	rctx->db_misc_state.atom.dirty = true;}