自学教程：C++ vb2_dma_contig_plane_dma_addr函数代码示例

static void mxr_vp_buffer_set(struct mxr_layer *layer,	struct mxr_buffer *buf){	dma_addr_t luma_addr[2] = {0, 0};	dma_addr_t chroma_addr[2] = {0, 0};	if (buf == NULL) {		mxr_reg_vp_buffer(layer->mdev, luma_addr, chroma_addr);		return;	}	luma_addr[0] = vb2_dma_contig_plane_dma_addr(&buf->vb, 0);	if (layer->fmt->num_subframes == 2) {		chroma_addr[0] = vb2_dma_contig_plane_dma_addr(&buf->vb, 1);	} else {		chroma_addr[0] = luma_addr[0] + mxr_get_plane_size(			&layer->fmt->plane[0], layer->geo.src.full_width,			layer->geo.src.full_height);	}	if (layer->fmt->cookie & VP_MODE_MEM_TILED) {		luma_addr[1] = luma_addr[0] + 0x40;		chroma_addr[1] = chroma_addr[0] + 0x40;	} else {		luma_addr[1] = luma_addr[0] + layer->geo.src.full_width;		chroma_addr[1] = chroma_addr[0];	}	mxr_reg_vp_buffer(layer->mdev, luma_addr, chroma_addr);}

static void mxr_vp_buffer_set(struct mxr_layer *layer,	struct mxr_buffer *buf){	dma_addr_t luma_addr[2] = {0, 0};	dma_addr_t chroma_addr[2] = {0, 0};	if (buf == NULL) {		mxr_reg_vp_buffer(layer->mdev, luma_addr, chroma_addr);		return;	}	luma_addr[0] = vb2_dma_contig_plane_dma_addr(&buf->vb, 0);	if (layer->fmt->num_subframes == 2) {		chroma_addr[0] = vb2_dma_contig_plane_dma_addr(&buf->vb, 1);	} else {		/* FIXME: mxr_get_plane_size compute integer division,		 * which is slow and should not be performed in interrupt */		chroma_addr[0] = luma_addr[0] + mxr_get_plane_size(			&layer->fmt->plane[0], layer->geo.src.full_width,			layer->geo.src.full_height);	}	if (layer->fmt->cookie & VP_MODE_MEM_TILED) {		luma_addr[1] = luma_addr[0] + 0x40;		chroma_addr[1] = chroma_addr[0] + 0x40;	} else {		luma_addr[1] = luma_addr[0] + layer->geo.src.full_width;		chroma_addr[1] = chroma_addr[0];	}	mxr_reg_vp_buffer(layer->mdev, luma_addr, chroma_addr);}

static int hva_buf_prepare(struct vb2_buffer *vb){	struct hva_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);	struct device *dev = ctx_to_dev(ctx);	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);	if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {		struct hva_frame *frame = to_hva_frame(vbuf);		if (vbuf->field == V4L2_FIELD_ANY)			vbuf->field = V4L2_FIELD_NONE;		if (vbuf->field != V4L2_FIELD_NONE) {			dev_dbg(dev,				"%s frame[%d] prepare: %d field not supported/n",				ctx->name, vb->index, vbuf->field);			return -EINVAL;		}		if (!frame->prepared) {			/* get memory addresses */			frame->vaddr = vb2_plane_vaddr(&vbuf->vb2_buf, 0);			frame->paddr = vb2_dma_contig_plane_dma_addr(					&vbuf->vb2_buf, 0);			frame->info = ctx->frameinfo;			frame->prepared = true;			dev_dbg(dev,				"%s frame[%d] prepared; virt=%p, phy=%pad/n",				ctx->name, vb->index,				frame->vaddr, &frame->paddr);		}	} else {		struct hva_stream *stream = to_hva_stream(vbuf);		if (!stream->prepared) {			/* get memory addresses */			stream->vaddr = vb2_plane_vaddr(&vbuf->vb2_buf, 0);			stream->paddr = vb2_dma_contig_plane_dma_addr(					&vbuf->vb2_buf, 0);			stream->size = vb2_plane_size(&vbuf->vb2_buf, 0);			stream->prepared = true;			dev_dbg(dev,				"%s stream[%d] prepared; virt=%p, phy=%pad/n",				ctx->name, vb->index,				stream->vaddr, &stream->paddr);		}	}	return 0;}

static void unicam_videobuf_queue(struct vb2_buffer *vb){	struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);	struct unicam_camera_dev *unicam_dev = ici->priv;	struct unicam_camera_buffer *buf = to_unicam_camera_vb(vb);	unsigned long flags;	dprintk("-enter");	dprintk("vb=0x%p vbuf=0x%p pbuf=0x%p size=%lu", vb,		vb2_plane_vaddr(vb, 0), (void *)vb2_dma_contig_plane_dma_addr(vb,									   0),		vb2_get_plane_payload(vb, 0));	spin_lock_irqsave(&unicam_dev->lock, flags);	list_add_tail(&buf->queue, &unicam_dev->capture);	if (!unicam_dev->active) {		unicam_dev->active = vb;		/* use this buffer to trigger capture */		/* Configure HW only is streamon has been done		 * else only update active, HW would be configured		 * by streamon  */		if(unicam_dev->streaming){			unicam_camera_update_buf(unicam_dev);			if (unicam_dev->if_params.if_mode ==				V4L2_SUBDEV_SENSOR_MODE_SERIAL_CSI2)				unicam_camera_capture(unicam_dev);		}	}	spin_unlock_irqrestore(&unicam_dev->lock, flags);	dprintk("-exit");}

static int unicam_videobuf_prepare(struct vb2_buffer *vb){	struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);	int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,						     icd->						     current_fmt->host_fmt);	unsigned long size;	dprintk("-enter");	if (bytes_per_line < 0)		return bytes_per_line;	dprintk("vb=0x%p vbuf=0x%p pbuf=0x%p, size=%lu", vb,		vb2_plane_vaddr(vb, 0), (void *)vb2_dma_contig_plane_dma_addr(vb,									   0),		vb2_get_plane_payload(vb, 0));	size = icd->user_height * bytes_per_line;	if (vb2_plane_size(vb, 0) < size) {		dev_err(icd->dev.parent, "Buffer too small (%lu < %lu)/n",			vb2_plane_size(vb, 0), size);		return -ENOBUFS;	}	vb2_set_plane_payload(vb, 0, size);	dprintk("-exit");	return 0;}

static intdt3155_start_acq(struct dt3155_priv *pd){	struct vb2_buffer *vb = pd->curr_buf;	dma_addr_t dma_addr;	dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);	iowrite32(dma_addr, pd->regs + EVEN_DMA_START);	iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START);	iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE);	iowrite32(img_width, pd->regs + ODD_DMA_STRIDE);	/* enable interrupts, clear all irq flags */	iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |			FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);	iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |		  FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,							pd->regs + CSR1);	wait_i2c_reg(pd->regs);	write_i2c_reg(pd->regs, CONFIG, pd->config);	write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);	write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);	/*  start the board  */	write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);	return 0; /* success  */}

static int isp_video_capture_buffer_prepare(struct vb2_buffer *vb){	struct fimc_isp *isp = vb2_get_drv_priv(vb->vb2_queue);	struct fimc_is_video *video = &isp->video_capture;	int i;	if (video->format == NULL)		return -EINVAL;	for (i = 0; i < video->format->memplanes; i++) {		unsigned long size = video->pixfmt.plane_fmt[i].sizeimage;		if (vb2_plane_size(vb, i) < size) {			v4l2_err(&video->ve.vdev,				 "User buffer too small (%ld < %ld)/n",				 vb2_plane_size(vb, i), size);			return -EINVAL;		}		vb2_set_plane_payload(vb, i, size);	}	/* Check if we get one of the already known buffers. */	if (test_bit(ST_ISP_VID_CAP_BUF_PREP, &isp->state)) {		dma_addr_t dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);		int i;		for (i = 0; i < video->buf_count; i++)			if (video->buffers[i]->dma_addr[0] == dma_addr)				return 0;		return -ENXIO;	}	return 0;}

static void imx7_csi_vb2_buf_done(struct imx7_csi *csi){	struct imx_media_video_dev *vdev = csi->vdev;	struct imx_media_buffer *done, *next;	struct vb2_buffer *vb;	dma_addr_t phys;	done = csi->active_vb2_buf[csi->buf_num];	if (done) {		done->vbuf.field = vdev->fmt.fmt.pix.field;		done->vbuf.sequence = csi->frame_sequence;		vb = &done->vbuf.vb2_buf;		vb->timestamp = ktime_get_ns();		vb2_buffer_done(vb, VB2_BUF_STATE_DONE);	}	csi->frame_sequence++;	/* get next queued buffer */	next = imx_media_capture_device_next_buf(vdev);	if (next) {		phys = vb2_dma_contig_plane_dma_addr(&next->vbuf.vb2_buf, 0);		csi->active_vb2_buf[csi->buf_num] = next;	} else {		phys = csi->underrun_buf.phys;		csi->active_vb2_buf[csi->buf_num] = NULL;	}	imx7_csi_update_buf(csi, phys, csi->buf_num);}

static int bdisp_get_addr(struct bdisp_ctx *ctx, struct vb2_buffer *vb,			  struct bdisp_frame *frame, dma_addr_t *paddr){	if (!vb || !frame)		return -EINVAL;	paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);	if (frame->fmt->nb_planes > 1)		/* UV (NV12) or U (420P) */		paddr[1] = (dma_addr_t)(paddr[0] +				frame->bytesperline * frame->height);	if (frame->fmt->nb_planes > 2)		/* V (420P) */		paddr[2] = (dma_addr_t)(paddr[1] +				(frame->bytesperline * frame->height) / 4);	if (frame->fmt->nb_planes > 3)		dev_dbg(ctx->bdisp_dev->dev, "ignoring some planes/n");	dev_dbg(ctx->bdisp_dev->dev,		"%s plane[0]=%pad plane[1]=%pad plane[2]=%pad/n",		__func__, &paddr[0], &paddr[1], &paddr[2]);	return 0;}

static int dt3155_start_streaming(struct vb2_queue *q, unsigned count){	struct dt3155_priv *pd = vb2_get_drv_priv(q);	struct vb2_buffer *vb = &pd->curr_buf->vb2_buf;	dma_addr_t dma_addr;	pd->sequence = 0;	dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);	iowrite32(dma_addr, pd->regs + EVEN_DMA_START);	iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);	iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);	iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);	/* enable interrupts, clear all irq flags */	iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |			FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);	iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |		  FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,							pd->regs + CSR1);	wait_i2c_reg(pd->regs);	write_i2c_reg(pd->regs, CONFIG, pd->config);	write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);	write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);	/*  start the board  */	write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);	return 0;}

static int isp_video_buffer_prepare(struct vb2_buffer *buf){	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(buf);	struct isp_video_fh *vfh = vb2_get_drv_priv(buf->vb2_queue);	struct isp_buffer *buffer = to_isp_buffer(vbuf);	struct isp_video *video = vfh->video;	dma_addr_t addr;	/* Refuse to prepare the buffer is the video node has registered an	 * error. We don't need to take any lock here as the operation is	 * inherently racy. The authoritative check will be performed in the	 * queue handler, which can't return an error, this check is just a best	 * effort to notify userspace as early as possible.	 */	if (unlikely(video->error))		return -EIO;	addr = vb2_dma_contig_plane_dma_addr(buf, 0);	if (!IS_ALIGNED(addr, 32)) {		dev_dbg(video->isp->dev,			"Buffer address must be aligned to 32 bytes boundary./n");		return -EINVAL;	}	vb2_set_plane_payload(&buffer->vb.vb2_buf, 0,			      vfh->format.fmt.pix.sizeimage);	buffer->dma = addr;	return 0;}

static void mxr_graph_buffer_set(struct mxr_layer *layer,	struct mxr_buffer *buf){	dma_addr_t addr = 0;	if (buf)		addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);	mxr_reg_graph_buffer(layer->mdev, layer->idx, addr);}

static int xvip_dma_buffer_prepare(struct vb2_buffer *vb){	struct xvip_dma *dma = vb2_get_drv_priv(vb->vb2_queue);	struct xvip_dma_buffer *buf = to_xvip_dma_buffer(vb);	buf->dma = dma;	buf->addr = vb2_dma_contig_plane_dma_addr(vb, 0);	buf->length = vb2_plane_size(vb, 0);	buf->bytesused = 0;	return 0;}

static void cleanup_ref_queue(struct s5p_mfc_ctx *ctx){	struct s5p_mfc_buf *mb_entry;	unsigned long mb_y_addr, mb_c_addr;		while (!list_empty(&ctx->ref_queue)) {		mb_entry = list_entry((&ctx->ref_queue)->next,						struct s5p_mfc_buf, list);		mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);		mb_c_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 1);		list_del(&mb_entry->list);		ctx->ref_queue_cnt--;		list_add_tail(&mb_entry->list, &ctx->src_queue);		ctx->src_queue_cnt++;	}	mfc_debug(2, "enc src count: %d, enc ref count: %d/n",		  ctx->src_queue_cnt, ctx->ref_queue_cnt);	INIT_LIST_HEAD(&ctx->ref_queue);	ctx->ref_queue_cnt = 0;}

static void rk3399_vpu_jpeg_enc_set_buffers(struct rockchip_vpu_dev *vpu,					    struct rockchip_vpu_ctx *ctx,					    struct vb2_buffer *src_buf){	struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;	dma_addr_t src[3];	WARN_ON(pix_fmt->num_planes > 3);	vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma,			   VEPU_REG_ADDR_OUTPUT_STREAM);	vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size,			   VEPU_REG_STR_BUF_LIMIT);	if (pix_fmt->num_planes == 1) {		src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);		vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);	} else if (pix_fmt->num_planes == 2) {		src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);		src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);		vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);		vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1);	} else {		src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);		src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);		src[2] = vb2_dma_contig_plane_dma_addr(src_buf, 2);		vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);		vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1);		vepu_write_relaxed(vpu, src[2], VEPU_REG_ADDR_IN_PLANE_2);	}}

static int mtk_venc_encode_header(void *priv){	struct mtk_vcodec_ctx *ctx = priv;	int ret;	struct vb2_v4l2_buffer *src_buf, *dst_buf;	struct mtk_vcodec_mem bs_buf;	struct venc_done_result enc_result;	dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);	if (!dst_buf) {		mtk_v4l2_debug(1, "No dst buffer");		return -EINVAL;	}	bs_buf.va = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);	bs_buf.dma_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);	bs_buf.size = (size_t)dst_buf->vb2_buf.planes[0].length;	mtk_v4l2_debug(1,			"[%d] buf id=%d va=0x%p dma_addr=0x%llx size=%zu",			ctx->id,			dst_buf->vb2_buf.index, bs_buf.va,			(u64)bs_buf.dma_addr,			bs_buf.size);	ret = venc_if_encode(ctx,			VENC_START_OPT_ENCODE_SEQUENCE_HEADER,			NULL, &bs_buf, &enc_result);	if (ret) {		dst_buf->vb2_buf.planes[0].bytesused = 0;		ctx->state = MTK_STATE_ABORT;		v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR);		mtk_v4l2_err("venc_if_encode failed=%d", ret);		return -EINVAL;	}	src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);	if (src_buf) {		dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;		dst_buf->timecode = src_buf->timecode;	} else {		mtk_v4l2_err("No timestamp for the header buffer.");	}	ctx->state = MTK_STATE_HEADER;	dst_buf->vb2_buf.planes[0].bytesused = enc_result.bs_size;	v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);	return 0;}

static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id){	struct dt3155_priv *ipd = dev_id;	struct vb2_buffer *ivb;	dma_addr_t dma_addr;	u32 tmp;	tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);	if (!tmp)		return IRQ_NONE;  /* not our irq */	if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {		iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,							ipd->regs + INT_CSR);		return IRQ_HANDLED; /* start of field irq */	}	tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);	if (tmp) {		iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |						FLD_DN_ODD | FLD_DN_EVEN |						CAP_CONT_EVEN | CAP_CONT_ODD,							ipd->regs + CSR1);		mmiowb();	}	spin_lock(&ipd->lock);	if (ipd->curr_buf && !list_empty(&ipd->dmaq)) {		ipd->curr_buf->vb2_buf.timestamp = ktime_get_ns();		ipd->curr_buf->sequence = ipd->sequence++;		ipd->curr_buf->field = V4L2_FIELD_NONE;		vb2_buffer_done(&ipd->curr_buf->vb2_buf, VB2_BUF_STATE_DONE);		ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);		list_del(&ivb->done_entry);		ipd->curr_buf = to_vb2_v4l2_buffer(ivb);		dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);		iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);		iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START);		iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE);		iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE);		mmiowb();	}	/* enable interrupts, clear all irq flags */	iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |			FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);	spin_unlock(&ipd->lock);	return IRQ_HANDLED;}

static int enc_pre_seq_start(struct s5p_mfc_ctx *ctx){	struct s5p_mfc_dev *dev = ctx->dev;	struct s5p_mfc_buf *dst_mb;	unsigned long dst_addr;	unsigned int dst_size;	unsigned long flags;	spin_lock_irqsave(&dev->irqlock, flags);	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);	dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);	dst_size = vb2_plane_size(dst_mb->b, 0);	s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size);	spin_unlock_irqrestore(&dev->irqlock, flags);	return 0;}

static void isp_video_capture_buffer_queue(struct vb2_buffer *vb){	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);	struct fimc_isp *isp = vb2_get_drv_priv(vb->vb2_queue);	struct fimc_is_video *video = &isp->video_capture;	struct fimc_is *is = fimc_isp_to_is(isp);	struct isp_video_buf *ivb = to_isp_video_buf(vbuf);	unsigned long flags;	unsigned int i;	if (test_bit(ST_ISP_VID_CAP_BUF_PREP, &isp->state)) {		spin_lock_irqsave(&is->slock, flags);		video->buf_mask |= BIT(ivb->index);		spin_unlock_irqrestore(&is->slock, flags);	} else {		unsigned int num_planes = video->format->memplanes;		ivb->index = video->buf_count;		video->buffers[ivb->index] = ivb;		for (i = 0; i < num_planes; i++) {			int buf_index = ivb->index * num_planes + i;			ivb->dma_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);			is->is_p_region->shared[32 + buf_index] =							ivb->dma_addr[i];			isp_dbg(2, &video->ve.vdev,				"dma_buf %pad (%d/%d/%d) addr: %pad/n",				&buf_index, ivb->index, i, vb->index,				&ivb->dma_addr[i]);		}		if (++video->buf_count < video->reqbufs_count)			return;		video->buf_mask = (1UL << video->buf_count) - 1;		set_bit(ST_ISP_VID_CAP_BUF_PREP, &isp->state);	}	if (!test_bit(ST_ISP_VID_CAP_STREAMING, &isp->state))		isp_video_capture_start_streaming(vb->vb2_queue, 0);}

/* The color format (num_comp, num_planes) must be already configured. */int gsc_prepare_addr(struct gsc_ctx *ctx, struct vb2_buffer *vb,			struct gsc_frame *frame, struct gsc_addr *addr){	int ret = 0;	u32 pix_size;	if ((vb == NULL) || (frame == NULL))		return -EINVAL;	pix_size = frame->f_width * frame->f_height;	pr_debug("num_planes= %d, num_comp= %d, pix_size= %d",		frame->fmt->num_planes, frame->fmt->num_comp, pix_size);	addr->y = vb2_dma_contig_plane_dma_addr(vb, 0);	if (frame->fmt->num_planes == 1) {		switch (frame->fmt->num_comp) {		case 1:			addr->cb = 0;			addr->cr = 0;			break;		case 2:			/* decompose Y into Y/Cb */			addr->cb = (dma_addr_t)(addr->y + pix_size);			addr->cr = 0;			break;		case 3:			/* decompose Y into Y/Cb/Cr */			addr->cb = (dma_addr_t)(addr->y + pix_size);			if (GSC_YUV420 == frame->fmt->color)				addr->cr = (dma_addr_t)(addr->cb						+ (pix_size >> 2));			else /* 422 */				addr->cr = (dma_addr_t)(addr->cb						+ (pix_size >> 1));			break;		default:			pr_err("Invalid the number of color planes");			return -EINVAL;		}	} else {

static void solo_fillbuf(struct solo_dev *solo_dev,			 struct vb2_buffer *vb){	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);	dma_addr_t addr;	unsigned int fdma_addr;	int error = -1;	int i;	addr = vb2_dma_contig_plane_dma_addr(vb, 0);	if (!addr)		goto finish_buf;	if (erase_off(solo_dev)) {		void *p = vb2_plane_vaddr(vb, 0);		int image_size = solo_image_size(solo_dev);		for (i = 0; i < image_size; i += 2) {			((u8 *)p)[i] = 0x80;			((u8 *)p)[i + 1] = 0x00;		}		error = 0;	} else {		fdma_addr = SOLO_DISP_EXT_ADDR + (solo_dev->old_write *				(SOLO_HW_BPL * solo_vlines(solo_dev)));		error = solo_p2m_dma_t(solo_dev, 0, addr, fdma_addr,				       solo_bytesperline(solo_dev),				       solo_vlines(solo_dev), SOLO_HW_BPL);	}finish_buf:	if (!error) {		vb2_set_plane_payload(vb, 0,			solo_vlines(solo_dev) * solo_bytesperline(solo_dev));		vbuf->sequence = solo_dev->sequence++;		vb->timestamp = ktime_get_ns();	}	vb2_buffer_done(vb, error ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);}

static int camif_prepare_addr(struct camif_vp *vp, struct vb2_buffer *vb,			      struct camif_addr *paddr){	struct camif_frame *frame = &vp->out_frame;	u32 pix_size;	if (vb == NULL || frame == NULL)		return -EINVAL;	pix_size = frame->rect.width * frame->rect.height;	pr_debug("colplanes: %d, pix_size: %u/n",		 vp->out_fmt->colplanes, pix_size);	paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);	switch (vp->out_fmt->colplanes) {	case 1:		paddr->cb = 0;		paddr->cr = 0;		break;	case 2:		/* decompose Y into Y/Cb */		paddr->cb = (u32)(paddr->y + pix_size);		paddr->cr = 0;		break;	case 3:		paddr->cb = (u32)(paddr->y + pix_size);		/* decompose Y into Y/Cb/Cr */		if (vp->out_fmt->color == IMG_FMT_YCBCR422P)			paddr->cr = (u32)(paddr->cb + (pix_size >> 1));		else /* 420 */			paddr->cr = (u32)(paddr->cb + (pix_size >> 2));		if (vp->out_fmt->color == IMG_FMT_YCRCB420)			swap(paddr->cb, paddr->cr);		break;	default:		return -EINVAL;	}

/* * This function is currently unused, but will be called when the * output/mem2mem device at the IDMAC input pad sends us a new * buffer. It kicks off the IDMAC read channels to bring in the * buffer fields from memory and begin the conversions. */static void __maybe_unused prepare_vdi_in_buffers(struct vdic_priv *priv,						  struct imx_media_buffer *curr){	dma_addr_t prev_phys, curr_phys, next_phys;	struct imx_media_buffer *prev;	struct vb2_buffer *curr_vb, *prev_vb;	u32 fs = priv->field_size;	u32 is = priv->in_stride;	/* current input buffer is now previous */	priv->prev_in_buf = priv->curr_in_buf;	priv->curr_in_buf = curr;	prev = priv->prev_in_buf ? priv->prev_in_buf : curr;	prev_vb = &prev->vbuf.vb2_buf;	curr_vb = &curr->vbuf.vb2_buf;	switch (priv->fieldtype) {	case V4L2_FIELD_SEQ_TB:	case V4L2_FIELD_SEQ_BT:		prev_phys = vb2_dma_contig_plane_dma_addr(prev_vb, 0) + fs;		curr_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0);		next_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0) + fs;		break;	case V4L2_FIELD_INTERLACED_TB:	case V4L2_FIELD_INTERLACED_BT:	case V4L2_FIELD_INTERLACED:		prev_phys = vb2_dma_contig_plane_dma_addr(prev_vb, 0) + is;		curr_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0);		next_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0) + is;		break;	default:		/*		 * can't get here, priv->fieldtype can only be one of		 * the above. This is to quiet smatch errors.		 */		return;	}	ipu_cpmem_set_buffer(priv->vdi_in_ch_p, 0, prev_phys);	ipu_cpmem_set_buffer(priv->vdi_in_ch,   0, curr_phys);	ipu_cpmem_set_buffer(priv->vdi_in_ch_n, 0, next_phys);	ipu_idmac_select_buffer(priv->vdi_in_ch_p, 0);	ipu_idmac_select_buffer(priv->vdi_in_ch, 0);	ipu_idmac_select_buffer(priv->vdi_in_ch_n, 0);}

static int iss_video_buf_prepare(struct vb2_buffer *vb){	struct iss_video_fh *vfh = vb2_get_drv_priv(vb->vb2_queue);	struct iss_buffer *buffer = container_of(vb, struct iss_buffer, vb);	struct iss_video *video = vfh->video;	unsigned long size = vfh->format.fmt.pix.sizeimage;	dma_addr_t addr;	if (vb2_plane_size(vb, 0) < size)		return -ENOBUFS;	addr = vb2_dma_contig_plane_dma_addr(vb, 0);	if (!IS_ALIGNED(addr, 32)) {		dev_dbg(video->iss->dev,			"Buffer address must be aligned to 32 bytes boundary./n");		return -EINVAL;	}	vb2_set_plane_payload(vb, 0, size);	buffer->iss_addr = addr;	return 0;}

static void unicam_videobuf_release(struct vb2_buffer *vb){	struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);	struct unicam_camera_dev *unicam_dev = ici->priv;	struct unicam_camera_buffer *buf = to_unicam_camera_vb(vb);	unsigned long flags;	dprintk("-enter");	dprintk("vb=0x%p vbuf=0x%p pbuf=0x%p size=%lu", vb,		vb2_plane_vaddr(vb, 0), (void *)vb2_dma_contig_plane_dma_addr(vb,									   0),		vb2_get_plane_payload(vb, 0));	spin_lock_irqsave(&unicam_dev->lock, flags);	if (buf->magic == UNICAM_BUF_MAGIC)		list_del_init(&buf->queue);	spin_unlock_irqrestore(&unicam_dev->lock, flags);	dprintk("-exit");}

/* Moves a buffer from the queue to the HW slots */static int rcar_vin_fill_hw_slot(struct rcar_vin_priv *priv){	struct vb2_buffer *vb;	dma_addr_t phys_addr_top;	int slot;	if (list_empty(&priv->capture))		return 0;	/* Find a free HW slot */	slot = rcar_vin_get_free_hw_slot(priv);	if (slot < 0)		return 0;	vb = &list_entry(priv->capture.next, struct rcar_vin_buffer, list)->vb;	list_del_init(to_buf_list(vb));	priv->queue_buf[slot] = vb;	phys_addr_top = vb2_dma_contig_plane_dma_addr(vb, 0);	iowrite32(phys_addr_top, priv->base + VNMB_REG(slot));	return 1;}

static void imx7_csi_setup_vb2_buf(struct imx7_csi *csi){	struct imx_media_video_dev *vdev = csi->vdev;	struct imx_media_buffer *buf;	struct vb2_buffer *vb2_buf;	dma_addr_t phys[2];	int i;	for (i = 0; i < 2; i++) {		buf = imx_media_capture_device_next_buf(vdev);		if (buf) {			csi->active_vb2_buf[i] = buf;			vb2_buf = &buf->vbuf.vb2_buf;			phys[i] = vb2_dma_contig_plane_dma_addr(vb2_buf, 0);		} else {			csi->active_vb2_buf[i] = NULL;			phys[i] = csi->underrun_buf.phys;		}		imx7_csi_update_buf(csi, phys[i], i);	}}