自学教程：C++ vsync_irq_enable函数代码示例

int mdp4_dtv_pipe_commit(int cndx, int wait){	int  i, undx;	int mixer = 0;	struct vsycn_ctrl *vctrl;	struct vsync_update *vp;	struct mdp4_overlay_pipe *pipe;	struct mdp4_overlay_pipe *real_pipe;	unsigned long flags;	int cnt = 0;	vctrl = &vsync_ctrl_db[cndx];	mutex_lock(&vctrl->update_lock);	undx =  vctrl->update_ndx;	vp = &vctrl->vlist[undx];	pipe = vctrl->base_pipe;	mixer = pipe->mixer_num;	mdp4_overlay_iommu_unmap_freelist(mixer);	mdp_update_pm(vctrl->mfd, vctrl->vsync_time);	if (vp->update_cnt == 0) {		mutex_unlock(&vctrl->update_lock);		return 0;	}	vctrl->update_ndx++;	vctrl->update_ndx &= 0x01;	vp->update_cnt = 0;	/* reset */	mutex_unlock(&vctrl->update_lock);	pipe = vp->plist;	for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {		if (pipe->pipe_used) {			cnt++;			real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);			if (real_pipe && real_pipe->pipe_used) {				/* pipe not unset */				mdp4_overlay_vsync_commit(pipe);			}			/* free previous iommu to freelist			* which will be freed at next			* pipe_commit			*/			mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);			pipe->pipe_used = 0; /* clear */		}	}	mdp4_mixer_stage_commit(mixer);	 /* start timing generator & mmu if they are not started yet */	mdp4_overlay_dtv_start();	pipe = vctrl->base_pipe;	spin_lock_irqsave(&vctrl->spin_lock, flags);	if (pipe->ov_blt_addr) {		mdp4_dtv_blt_ov_update(pipe);		pipe->blt_ov_done++;		vsync_irq_enable(INTR_OVERLAY1_DONE, MDP_OVERLAY1_TERM);		mb();		pipe->blt_ov_koff++;		/* kickoff overlay1 engine */		mdp4_stat.kickoff_ov1++;		outpdw(MDP_BASE + 0x0008, 0);	} else {		/* schedule second phase update  at dmap */		INIT_COMPLETION(vctrl->dmae_comp);		vsync_irq_enable(INTR_DMA_E_DONE, MDP_DMA_E_TERM);	}	spin_unlock_irqrestore(&vctrl->spin_lock, flags);	mdp4_stat.overlay_commit[pipe->mixer_num]++;	if (wait)		mdp4_dtv_wait4dmae(0);	return cnt;}

//.........这里部分代码省略.........	mdp4_overlay_iommu_unmap_freelist(mixer);	spin_lock_irqsave(&vctrl->spin_lock, flags);	if (pipe->ov_blt_addr) {		/* Blt */		if (vctrl->blt_wait)			need_dmap_wait = 1;		if (vctrl->ov_koff != vctrl->ov_done) {			INIT_COMPLETION(vctrl->ov_comp);			need_ov_wait = 1;		}	} else {		/* direct out */		if (vctrl->dmap_koff != vctrl->dmap_done) {			INIT_COMPLETION(vctrl->dmap_comp);			pr_debug("%s: wait, ok=%d od=%d dk=%d dd=%d cpu=%d/n",			 __func__, vctrl->ov_koff, vctrl->ov_done,			vctrl->dmap_koff, vctrl->dmap_done, smp_processor_id());			need_dmap_wait = 1;		}	}	spin_unlock_irqrestore(&vctrl->spin_lock, flags);	if (need_dmap_wait) {		pr_debug("%s: wait4dmap/n", __func__);		mdp4_dsi_cmd_wait4dmap(0);	}	if (need_ov_wait) {		pr_debug("%s: wait4ov/n", __func__);		mdp4_dsi_cmd_wait4ov(0);	}	if (pipe->ov_blt_addr) {		if (vctrl->blt_end) {			vctrl->blt_end = 0;			pipe->ov_blt_addr = 0;			pipe->dma_blt_addr =  0;		}	}	if (vctrl->blt_change) {		mdp4_overlayproc_cfg(pipe);		mdp4_overlay_dmap_xy(pipe);		vctrl->blt_change = 0;	}	pipe = vp->plist;	for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {		if (pipe->pipe_used) {			cnt++;			real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);			if (real_pipe && real_pipe->pipe_used) {				/* pipe not unset */				mdp4_overlay_vsync_commit(pipe);			}			/* free previous iommu to freelist			* which will be freed at next			* pipe_commit			*/			mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);			pipe->pipe_used = 0; /* clear */		}	}	/* tx dcs command if had any */	mipi_dsi_cmdlist_commit(1);	mdp4_mixer_stage_commit(mixer);	pipe = vctrl->base_pipe;	spin_lock_irqsave(&vctrl->spin_lock, flags);	if (pipe->ov_blt_addr) {		mdp4_dsi_cmd_blt_ov_update(pipe);		pipe->ov_cnt++;		vctrl->ov_koff++;		INIT_COMPLETION(vctrl->ov_comp);		vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);	} else {		INIT_COMPLETION(vctrl->dmap_comp);		vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);		vctrl->dmap_koff++;	}	pr_debug("%s: kickoff, pid=%d/n", __func__, current->pid);	/* kickoff overlay engine */	mdp4_stat.kickoff_ov0++;	outpdw(MDP_BASE + 0x0004, 0);	mb(); /* make sure kickoff ececuted */	spin_unlock_irqrestore(&vctrl->spin_lock, flags);	mdp4_stat.overlay_commit[pipe->mixer_num]++;	if (wait) {		long long tick;		mdp4_dsi_cmd_wait4vsync(cndx, &tick);	}	return cnt;}

/* * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile * has enough space h * w * 3 * 2 */static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable){	unsigned long flag;	int cndx = 0;	struct vsycn_ctrl *vctrl;	struct mdp4_overlay_pipe *pipe;	vctrl = &vsync_ctrl_db[cndx];	pipe = vctrl->base_pipe;	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);	if (mfd->ov0_wb_buf->write_addr == 0) {		pr_info("%s: no blt_base assigned/n", __func__);		return;	}	spin_lock_irqsave(&vctrl->spin_lock, flag);	if (enable && pipe->ov_blt_addr == 0) {		pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;		pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;		pipe->ov_cnt = 0;		pipe->dmap_cnt = 0;		vctrl->ov_koff = 0;		vctrl->ov_done = 0;		vctrl->blt_free = 0;		mdp4_stat.blt_dsi_video++;		vctrl->blt_change++;	} else if (enable == 0 && pipe->ov_blt_addr) {		pipe->ov_blt_addr = 0;		pipe->dma_blt_addr =  0;		vctrl->blt_free = 4;	/* 4 commits to free wb buf */		vctrl->blt_change++;	}	pr_info("%s: changed=%d enable=%d ov_blt_addr=%x/n", __func__,		vctrl->blt_change, enable, (int)pipe->ov_blt_addr);	if (!vctrl->blt_change) {		spin_unlock_irqrestore(&vctrl->spin_lock, flag);		return;	}	spin_unlock_irqrestore(&vctrl->spin_lock, flag);	if (vctrl->blt_ctrl == OVERLAY_BLT_SWITCH_TG_OFF) {		int tg_enabled;		pr_info("%s: blt enabled by switching TG off/n", __func__);		vctrl->blt_change = 0;		tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;		if (tg_enabled) {			mdp4_dsi_video_wait4vsync(cndx);			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);			mdp4_dsi_video_wait4dmap_done(0);		}		mdp4_overlayproc_cfg(pipe);		mdp4_overlay_dmap_xy(pipe);		if (pipe->ov_blt_addr) {			mdp4_dsi_video_blt_ov_update(pipe);			pipe->ov_cnt++;			/* Prefill one frame */			vsync_irq_enable(INTR_OVERLAY0_DONE,						MDP_OVERLAY0_TERM);			/* kickoff overlay0 engine */			mdp4_stat.kickoff_ov0++;			vctrl->ov_koff++;	/* make up for prefill */			outpdw(MDP_BASE + 0x0004, 0);		}		if (tg_enabled) {			/*			 * need wait for more than 1 ms to			 * make sure lanes' fifo is empty and			 * lanes in stop state befroe reset			 * controller			 */			usleep(2000);			mipi_dsi_sw_reset();			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);		}	}}

static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable){	unsigned long flag;	int cndx = 0;	struct vsycn_ctrl *vctrl;	struct mdp4_overlay_pipe *pipe;	vctrl = &vsync_ctrl_db[cndx];	pipe = vctrl->base_pipe;	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);	if (mfd->ov0_wb_buf->write_addr == 0) {		pr_info("%s: no blt_base assigned/n", __func__);		return;	}	spin_lock_irqsave(&vctrl->spin_lock, flag);	if (enable && pipe->ov_blt_addr == 0) {		pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;		pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;		pipe->ov_cnt = 0;		pipe->dmap_cnt = 0;		vctrl->ov_koff = 0;		vctrl->ov_done = 0;		vctrl->blt_free = 0;		mdp4_stat.blt_dsi_video++;		vctrl->blt_change++;	} else if (enable == 0 && pipe->ov_blt_addr) {		pipe->ov_blt_addr = 0;		pipe->dma_blt_addr =  0;		vctrl->blt_free = 4;			vctrl->blt_change++;	}	pr_info("%s: changed=%d enable=%d ov_blt_addr=%x/n", __func__,		vctrl->blt_change, enable, (int)pipe->ov_blt_addr);	if (!vctrl->blt_change) {		spin_unlock_irqrestore(&vctrl->spin_lock, flag);		return;	}	spin_unlock_irqrestore(&vctrl->spin_lock, flag);	if (mdp_ov0_blt_ctl == MDP4_BLT_SWITCH_TG_OFF) {		int tg_enabled;		pr_debug("%s: blt enabled by switching TG off/n", __func__);		tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;		if (tg_enabled) {			mdp4_dsi_video_wait4dmap_done(0);			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);			msleep(20);		}		mdp4_overlayproc_cfg(pipe);		mdp4_overlay_dmap_xy(pipe);		if (tg_enabled) {			if (pipe->ov_blt_addr) {				spin_lock_irqsave(&vctrl->spin_lock, flag);				pipe->ov_cnt++;				vctrl->ov_koff++;								mdp4_stat.kickoff_ov0++;				INIT_COMPLETION(vctrl->ov_comp);				vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);				outpdw(MDP_BASE + 0x0004, 0);				spin_unlock_irqrestore(&vctrl->spin_lock, flag);				mdp4_dsi_video_wait4ov(0);			}			mipi_dsi_sw_reset();			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);		}		vctrl->blt_change = 0;	}}

int mdp4_dsi_video_pipe_commit(int cndx, int wait){	int  i, undx;	int mixer = 0;	struct vsycn_ctrl *vctrl;	struct vsync_update *vp;	struct mdp4_overlay_pipe *pipe;	struct mdp4_overlay_pipe *real_pipe;	unsigned long flags;	int cnt = 0;	vctrl = &vsync_ctrl_db[cndx];	mutex_lock(&vctrl->update_lock);	undx =  vctrl->update_ndx;	vp = &vctrl->vlist[undx];	pipe = vctrl->base_pipe;	mixer = pipe->mixer_num;	if (vp->update_cnt == 0) {		mutex_unlock(&vctrl->update_lock);		return cnt;	}	vctrl->update_ndx++;	vctrl->update_ndx &= 0x01;	vp->update_cnt = 0;     	if (vctrl->blt_free) {		vctrl->blt_free--;		if (vctrl->blt_free == 0)			mdp4_free_writeback_buf(vctrl->mfd, mixer);	}	mutex_unlock(&vctrl->update_lock);		mdp4_overlay_iommu_unmap_freelist(mixer);	spin_lock_irqsave(&vctrl->spin_lock, flags);	if (vctrl->ov_koff != vctrl->ov_done) {		spin_unlock_irqrestore(&vctrl->spin_lock, flags);		pr_err("%s: Error, frame dropped %d %d/n", __func__,				vctrl->ov_koff, vctrl->ov_done);		return 0;	}	spin_unlock_irqrestore(&vctrl->spin_lock, flags);	if (vctrl->blt_change) {		pipe = vctrl->base_pipe;		spin_lock_irqsave(&vctrl->spin_lock, flags);		INIT_COMPLETION(vctrl->dmap_comp);		INIT_COMPLETION(vctrl->ov_comp);		vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);		spin_unlock_irqrestore(&vctrl->spin_lock, flags);		mdp4_dsi_video_wait4dmap(0);		if (pipe->ov_blt_addr)			mdp4_dsi_video_wait4ov(0);	}	pipe = vp->plist;	for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {		if (pipe->pipe_used) {			cnt++;			real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);			if (real_pipe && real_pipe->pipe_used) {								mdp4_overlay_vsync_commit(pipe);			}			mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);			pipe->pipe_used = 0; 		}	}	mdp4_mixer_stage_commit(mixer);	pipe = vctrl->base_pipe;	spin_lock_irqsave(&vctrl->spin_lock, flags);	if (pipe->ov_blt_addr) {		mdp4_dsi_video_blt_ov_update(pipe);		pipe->ov_cnt++;		INIT_COMPLETION(vctrl->ov_comp);		vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);		mb();		vctrl->ov_koff++;				mdp4_stat.kickoff_ov0++;		outpdw(MDP_BASE + 0x0004, 0);	} else {				INIT_COMPLETION(vctrl->dmap_comp);		vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);	}	spin_unlock_irqrestore(&vctrl->spin_lock, flags);	mdp4_stat.overlay_commit[pipe->mixer_num]++;	if (wait) {		if (pipe->ov_blt_addr)			mdp4_dsi_video_wait4ov(cndx);//.........这里部分代码省略.........

void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd){	int cndx = 0;	struct vsycn_ctrl *vctrl;	struct mdp4_overlay_pipe *pipe;	unsigned long flags;	int clk_set_on = 0;	vctrl = &vsync_ctrl_db[cndx];	if (!mfd->panel_power_on)		return;	pipe = vctrl->base_pipe;	if (pipe == NULL) {		pr_err("%s: NO base pipe/n", __func__);		return;	}	mutex_lock(&vctrl->update_lock);	if (atomic_read(&vctrl->suspend)) {		mutex_unlock(&vctrl->update_lock);		pr_warning("[DISP] %s: suspended, no more pan display/n", __func__);		return;	}	spin_lock_irqsave(&vctrl->spin_lock, flags);	vctrl->pan_display++;	vctrl->clk_control = 0;	if (vctrl->clk_enabled == 0) {		clk_set_on = 1;		vctrl->clk_enabled = 1;		vctrl->expire_tick = VSYNC_EXPIRE_TICK;	} else if (vctrl->expire_tick && vctrl->expire_tick < VSYNC_EXPIRE_TICK) {		vctrl->expire_tick = VSYNC_EXPIRE_TICK;	}	spin_unlock_irqrestore(&vctrl->spin_lock, flags);	if (clk_set_on) {		pr_debug("%s: SET_CLK_ON/n", __func__);		mipi_dsi_clk_cfg(1, 0);		mdp_clk_ctrl(1);		vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);	}	mutex_unlock(&vctrl->update_lock);	if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {		mdp4_mipi_vsync_enable(mfd, pipe, 0);		mdp4_overlay_setup_pipe_addr(mfd, pipe);		mdp4_dsi_cmd_pipe_queue(0, pipe);	}	mdp4_overlay_mdp_perf_upd(mfd, 1);	mutex_lock(&mfd->dma->ov_mutex);	mdp4_dsi_cmd_pipe_commit();	mdp4_overlay_mdp_perf_upd(mfd, 0);	mutex_unlock(&mfd->dma->ov_mutex);}