自学教程：C++ wait_all_core0_started函数代码示例

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	struct sys_info *sysinfo = &sysinfo_car;	u32 bsp_apicid = 0, val;	msr_t msr;	timestamp_init(timestamp_get());	timestamp_add_now(TS_START_ROMSTAGE);	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		/* mov bsp to bus 0xff when > 8 nodes */		set_bsp_node_CHtExtNodeCfgEn();		enumerate_ht_chain();		bcm5785_enable_lpc();		pc87417_enable_dev(RTC_DEV); /* Enable RTC */	}	post_code(0x30);	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV	val = cpuid_eax(1);	printk(BIOS_DEBUG, "BSP Family_Model: %08x/n", val);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid = %02x/n", bsp_apicid);	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx/n", cpu_init_detectedx);	/* Setup sysinfo defaults */	set_sysinfo_in_ram(0);	update_microcode(val);	post_code(0x33);	cpuSetAMDMSR(0);	post_code(0x34);	amd_ht_init(sysinfo);	post_code(0x35);	/* Setup nodes PCI space and start core 0 AP init. */	finalize_node_setup(sysinfo);	post_code(0x36);	/* wait for all the APs core0 started by finalize_node_setup. */	/* FIXME: A bunch of cores are going to start output to serial at once.	 * It would be nice to fixup prink spinlocks for ROM XIP mode.	 * I think it could be done by putting the spinlock flag in the cache	 * of the BSP located right after sysinfo.	 */	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	/* Core0 on each node is configured. Now setup any additional cores. */	printk(BIOS_DEBUG, "start_other_cores()/n");	start_other_cores(bsp_apicid);	post_code(0x37);	wait_all_other_cores_started(bsp_apicid);#endif#if CONFIG_SET_FIDVID	msr = rdmsr(0xc0010071);	printk(BIOS_DEBUG, "/nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);	/* FIXME: The sb fid change may survive the warm reset and only	 * need to be done once.*/	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);	post_code(0x39);	if (!warm_reset_detect(0)) {                    // BSP is node 0		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);	} else {		init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0	}	post_code(0x3A);	/* show final fid and vid */	msr = rdmsr(0xc0010071);	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);#endif	init_timer();//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	struct sys_info *sysinfo = &sysinfo_car;	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };	u32 bsp_apicid = 0, val;	msr_t msr;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		/* mov bsp to bus 0xff when > 8 nodes */		set_bsp_node_CHtExtNodeCfgEn();		enumerate_ht_chain();		sb7xx_51xx_pci_port80();	}	post_code(0x30);	if (bist == 0) {		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */		/* All cores run this but the BSP(node0,core0) is the only core that returns. */	}	post_code(0x32);	enable_rs780_dev8();	sb7xx_51xx_lpc_init();	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	ite_kill_watchdog(GPIO_DEV);	console_init();//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	// Load MPB	val = cpuid_eax(1);	printk(BIOS_DEBUG, "BSP Family_Model: %08x /n", val);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid = %02x /n", bsp_apicid);	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx /n", cpu_init_detectedx);	/* Setup sysinfo defaults */	set_sysinfo_in_ram(0);	update_microcode(val);	post_code(0x33);	cpuSetAMDMSR();	post_code(0x34);	amd_ht_init(sysinfo);	post_code(0x35);	/* Setup nodes PCI space and start core 0 AP init. */	finalize_node_setup(sysinfo);	/* Setup any mainboard PCI settings etc. */	setup_mb_resource_map();	post_code(0x36);	/* wait for all the APs core0 started by finalize_node_setup. */	/* FIXME: A bunch of cores are going to start output to serial at once.	   It would be nice to fixup prink spinlocks for ROM XIP mode.	   I think it could be done by putting the spinlock flag in the cache	   of the BSP located right after sysinfo.	 */	wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS	/* Core0 on each node is configured. Now setup any additional cores. */	printk(BIOS_DEBUG, "start_other_cores()/n");	start_other_cores();	post_code(0x37);	wait_all_other_cores_started(bsp_apicid); #endif	post_code(0x38);	/* run _early_setup before soft-reset. */	rs780_early_setup();	sb7xx_51xx_early_setup(); #if CONFIG_SET_FIDVID	msr = rdmsr(0xc0010071);	printk(BIOS_DEBUG, "/nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x /n", msr.hi, msr.lo);	/* FIXME: The sb fid change may survive the warm reset and only	   need to be done once.*/	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);	post_code(0x39);	if (!warm_reset_detect(0)) {			// BSP is node 0		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);	} else {//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr [] = {		DIMM0, DIMM2, 0, 0,		DIMM1, DIMM3, 0, 0,#if CONFIG_MAX_PHYSICAL_CPUS > 1		DIMM4, DIMM6, 0, 0,		DIMM5, DIMM7, 0, 0,#endif	};        int needs_reset;        unsigned bsp_apicid = 0, nodes;        struct mem_controller ctrl[8];        if (bist == 0)                bsp_apicid = init_cpus(cpu_init_detectedx);	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);	/* Halt if there was a built in self test failure */	report_bist_failure(bist);        setup_khepri_resource_map();#if 0        dump_pci_device(PCI_DEV(0, 0x18, 0));	dump_pci_device(PCI_DEV(0, 0x19, 0));#endif	needs_reset = setup_coherent_ht_domain();        wait_all_core0_started();#if CONFIG_LOGICAL_CPUS        // It is said that we should start core1 after all core0 launched        start_other_cores();        wait_all_other_cores_started(bsp_apicid);#endif        needs_reset |= ht_setup_chains_x();       	if (needs_reset) {               	print_info("ht reset -/n");               	soft_reset();       	}        allow_all_aps_stop(bsp_apicid);        nodes = get_nodes();        //It's the time to set ctrl now;        fill_mem_ctrl(nodes, ctrl, spd_addr);        enable_smbus();        memreset_setup();        sdram_initialize(nodes, ctrl);#if 0	dump_pci_devices();#endif	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	struct sys_info *sysinfo = &sysinfo_car;	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };	u32 bsp_apicid = 0, val;	msr_t msr;	timestamp_init(timestamp_get());	timestamp_add_now(TS_START_ROMSTAGE);	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		/* mov bsp to bus 0xff when > 8 nodes */		set_bsp_node_CHtExtNodeCfgEn();		enumerate_ht_chain();		/*enable port80 decoding and southbridge poweron init */		sb_Poweron_Init();	}	post_code(0x30);	if (bist == 0) {		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */		/* All cores run this but the BSP(node0,core0) is the only core that returns. */	}	post_code(0x32);	enable_rs780_dev8();	sb800_clk_output_48Mhz();	w83627hf_set_clksel_48(CLK_DEV);	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	printk(BIOS_DEBUG, "/n");	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	/* Load MPB */	val = cpuid_eax(1);	printk(BIOS_DEBUG, "BSP Family_Model: %08x/n", val);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid = %02x/n", bsp_apicid);	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx/n", cpu_init_detectedx);	/* Setup sysinfo defaults */	set_sysinfo_in_ram(0);	update_microcode(val);	post_code(0x33);	cpuSetAMDMSR(0);	post_code(0x34);	amd_ht_init(sysinfo);	post_code(0x35);	/* Setup nodes PCI space and start core 0 AP init. */	finalize_node_setup(sysinfo);	/* Setup any mainboard PCI settings etc. */	setup_mb_resource_map();	post_code(0x36);	/* wait for all the APs core0 started by finalize_node_setup. */	/* FIXME: A bunch of cores are going to start output to serial at once.	   It would be nice to fixup prink spinlocks for ROM XIP mode.	   I think it could be done by putting the spinlock flag in the cache	   of the BSP located right after sysinfo.	 */	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	/* Core0 on each node is configured. Now setup any additional cores. */	printk(BIOS_DEBUG, "start_other_cores()/n");	start_other_cores(bsp_apicid);	post_code(0x37);	wait_all_other_cores_started(bsp_apicid);#endif	post_code(0x38);	/* run _early_setup before soft-reset. */	rs780_early_setup();#if CONFIG_SET_FIDVID	msr = rdmsr(0xc0010071);	printk(BIOS_DEBUG, "/nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);	post_code(0x39);	if (!warm_reset_detect(0)) {			/* BSP is node 0 */		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);	} else {		init_fidvid_stage2(bsp_apicid, 0);	/* BSP is node 0 */	}//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr [] = {		// Node 0		DIMM0, DIMM2, 0, 0,		DIMM1, DIMM3, 0, 0,		// Node 1		DIMM4, DIMM6, 0, 0,		DIMM5, DIMM7, 0, 0,	};        struct sys_info *sysinfo = &sysinfo_car;        int needs_reset = 0;        unsigned bsp_apicid = 0;        if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		sio_setup();        }        if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);#if 0	uint8_t tmp = 0;	pnp_enter_ext_func_mode(SERIAL_DEV);	/* The following line will set CLKIN to 24 MHz, external */	pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);	tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);	/* Is serial flash enabled? Then enable writing to serial flash. */	if (tmp & 0x0e) {		pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);		pnp_set_logical_device(GPIO_DEV);		/* Set Serial Flash interface to 0x0820 */		pnp_write_config(GPIO_DEV, 0x64, 0x08);		pnp_write_config(GPIO_DEV, 0x65, 0x20);	} 	it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);	pnp_exit_ext_func_mode(SERIAL_DEV);#endif	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);        setup_mb_resource_map();        console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("/n");        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram        setup_coherent_ht_domain(); // routing table and start other core0        wait_all_core0_started();#if CONFIG_LOGICAL_CPUS        // It is said that we should start core1 after all core0 launched        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,         * So here need to make sure last core0 is started, esp for two way system,         * (there may be apic id conflicts in that case)         */        start_other_cores();        wait_all_other_cores_started(bsp_apicid);#endif        /* it will set up chains and store link pair for optimization later */        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn#if CONFIG_SET_FIDVID        {                msr_t msr;                msr=rdmsr(0xc0010042);                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("/n");        }        enable_fid_change();        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);        init_fidvid_bsp(bsp_apicid);        // show final fid and vid        {                msr_t msr;                msr=rdmsr(0xc0010042);                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("/n");        }#endif	init_timer(); // Need to use TMICT to synconize FID/VID        needs_reset |= optimize_link_coherent_ht();        needs_reset |= optimize_link_incoherent_ht(sysinfo);        needs_reset |= mcp55_early_setup_x();        // fidvid change will issue one LDTSTOP and the HT change will be effective too        if (needs_reset) {                print_info("ht reset -/n");              	soft_reset();//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr [] = {		// Node 0		DIMM0, DIMM2, 0, 0,		DIMM1, DIMM3, 0, 0,		// Node 1		DIMM4, DIMM6, 0, 0,		DIMM5, DIMM7, 0, 0,	};	struct sys_info *sysinfo = &sysinfo_car;	int needs_reset = 0;	unsigned bsp_apicid = 0;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		sio_setup();	}	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	setup_mb_resource_map();	dme1737_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid=%02x/n", bsp_apicid);	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram	setup_coherent_ht_domain(); // routing table and start other core0	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	// It is said that we should start core1 after all core0 launched	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,	 * So here need to make sure last core0 is started, esp for two way system,	 * (there may be apic id conflicts in that case)	 */	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	/* it will set up chains and store link pair for optimization later */	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn#if CONFIG_SET_FIDVID	{		msr_t msr;		msr=rdmsr(0xc0010042);		printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x/n", msr.hi, msr.lo);	}	enable_fid_change();	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);	init_fidvid_bsp(bsp_apicid);	// show final fid and vid	{		msr_t msr;		msr=rdmsr(0xc0010042);		printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x/n", msr.hi, msr.lo);	}#endif	init_timer(); /* Need to use TMICT to synchronize FID/VID. */	needs_reset |= optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);	needs_reset |= mcp55_early_setup_x();	/* mask NMI from constantly-asserted-on-this-board SERR# */	outb((inb(NMI_SC) & 0x0f) | PCI_SERR_EN, NMI_SC);	// fidvid change will issue one LDTSTOP and the HT change will be effective too	if (needs_reset) {		printk(BIOS_INFO, "ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	//It's the time to set ctrl in sysinfo now;	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);	enable_smbus();	/* all ap stopped? */	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);	post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const u16 spd_addr [] = {		DIMM0, DIMM2, 0, 0,		DIMM1, DIMM3, 0, 0,		DIMM4, DIMM6, 0, 0,		DIMM5, DIMM7, 0, 0,	};	int needs_reset;	unsigned bsp_apicid = 0, nodes;	struct mem_controller ctrl[8];	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		sio_setup();	}	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx);	lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	sio_gpio_setup();	setup_mb_resource_map();	needs_reset = setup_coherent_ht_domain();	wait_all_core0_started();	// It is said that we should start core1 after all core0 launched	start_other_cores();	wait_all_other_cores_started(bsp_apicid);	needs_reset |= ht_setup_chains_x();	needs_reset |= ck804_early_setup_x();	if (needs_reset) {		printk(BIOS_INFO, "ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	nodes = get_nodes();	//It's the time to set ctrl now;	fill_mem_ctrl(nodes, ctrl, spd_addr);	enable_smbus();	memreset_setup();	sdram_initialize(nodes, ctrl);	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };	int needs_reset = 0;	u32 bsp_apicid = 0;	msr_t msr;	struct cpuid_result cpuid1;	struct sys_info *sysinfo = &sysinfo_car;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		/* sb600_lpc_port80(); */		sb600_pci_port80();	}	if (bist == 0) {		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	}	enable_rs690_dev8(); // enable CFG access to Dev8, which is the SB P2P Bridge	sb600_lpc_init();#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)	check_cmos();  // rebooting in case of corrupted cmos !!!!!#endif	/* it8712f_enable_serial does not use its 1st parameter. */	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);	it8712f_kill_watchdog();	console_init();#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1)	check_cmos();  // rebooting in case of corrupted cmos !!!!!#endif	post_code(0x03);	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	__DEBUG__("bsp_apicid=0x%x/n", bsp_apicid);	setup_sitemp_resource_map();	setup_coherent_ht_domain();#if CONFIG_LOGICAL_CPUS	/* It is said that we should start core1 after all core0 launched */	wait_all_core0_started();	start_other_cores();#endif	wait_all_aps_started(bsp_apicid);	ht_setup_chains_x(sysinfo);	/* run _early_setup before soft-reset. */	rs690_early_setup();	sb600_early_setup();	post_code(0x04);	/* Check to see if processor is capable of changing FIDVID  */	/* otherwise it will throw a GP# when reading FIDVID_STATUS */	cpuid1 = cpuid(0x80000007);	if( (cpuid1.edx & 0x6) == 0x6 ) {		/* Read FIDVID_STATUS */		msr=rdmsr(0xc0010042);		__DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x/n", msr.hi, msr.lo);		enable_fid_change();		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);		init_fidvid_bsp(bsp_apicid);		/* show final fid and vid */		msr=rdmsr(0xc0010042);		__DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x/n", msr.hi, msr.lo);	} else {		__DEBUG__("Changing FIDVID not supported/n");	}	post_code(0x05);	needs_reset = optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);	rs690_htinit();	__DEBUG__("needs_reset=0x%x/n", needs_reset);	post_code(0x06);	if (needs_reset) {		__INFO__("ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	/* It's the time to set ctrl now; */	__DEBUG__("sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p/n",		     sysinfo->nodes, sysinfo->ctrl, spd_addr);//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr[] = {			// first node                        DIMM0, DIMM2, 0, 0,                        DIMM1, DIMM3, 0, 0,			// second node                        DIMM4, DIMM6, 0, 0,                        DIMM5, DIMM7, 0, 0,	};	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);        int needs_reset;        unsigned bsp_apicid = 0;        if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);        console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);        setup_default_resource_map();	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("/n");#if CONFIG_MEM_TRAIN_SEQ == 1        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram#endif	setup_coherent_ht_domain(); // routing table and start other core0	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS==1        // It is said that we should start core1 after all core0 launched	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,	 * So here need to make sure last core0 is started, esp for two way system,	 * (there may be apic id conflicts in that case)	 */        start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	/* it will set up chains and store link pair for optimization later */        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn#if CONFIG_SET_FIDVID        {                msr_t msr;	        msr=rdmsr(0xc0010042);                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("/n");        }	enable_fid_change();	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);        init_fidvid_bsp(bsp_apicid);        // show final fid and vid        {                msr_t msr;               	msr=rdmsr(0xc0010042);               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("/n");        }#endif	needs_reset = optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);        // fidvid change will issue one LDTSTOP and the HT change will be effective too        if (needs_reset) {                print_info("ht reset -/n");                soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);        }	allow_all_aps_stop(bsp_apicid);        //It's the time to set ctrl in sysinfo now;	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);	enable_smbus();#if 0	dump_smbus_registers();#endif	memreset_setup();	//do we need apci timer, tsc...., only debug need it for better output        /* all ap stopped? */        init_timer(); // Need to use TMICT to synconize FID/VID	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);#if 0        dump_pci_devices();#endif        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr [] = {		DIMM0, 0, 0, 0,		DIMM1, 0, 0, 0,	};	int needs_reset;	unsigned bsp_apicid = 0, nodes;	struct mem_controller ctrl[8];	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		sio_setup();	}	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx);//	post_code(0x32);	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);#if 0	dump_pci_device(PCI_DEV(0, 0x18, 0));#endif	needs_reset = setup_coherent_ht_domain();	wait_all_core0_started();	// It is said that we should start core1 after all core0 launched	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#if CONFIG_SET_FIDVID	/* Check to see if processor is capable of changing FIDVID  */	/* otherwise it will throw a GP# when reading FIDVID_STATUS */	if ((cpuid_edx(0x80000007) & 0x6) == 0x6) {		msr_t msr;		/* Read FIDVID_STATUS */		msr = rdmsr(0xc0010042);		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x/n", msr.hi, msr.lo);		enable_fid_change();		init_fidvid_bsp(bsp_apicid);		msr = rdmsr(0xc0010042);		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x/n", msr.hi, msr.lo);	}#endif	needs_reset |= ht_setup_chains_x();	needs_reset |= ck804_early_setup_x();	if (needs_reset) {		printk(BIOS_INFO, "ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	nodes = get_nodes();	//It's the time to set ctrl now;	fill_mem_ctrl(nodes, ctrl, spd_addr);	enable_smbus();#if 0	dump_spd_registers(&cpu[0]);	dump_smbus_registers();#endif	memreset_setup();	sdram_initialize(nodes, ctrl);#if 0	print_pci_devices();	dump_pci_devices();#endif	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr[] = {		// Node 0		RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,		RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,		// node 1		RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,		RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,	};	unsigned bsp_apicid = 0;	int needs_reset;	struct sys_info *sysinfo = &sysinfo_car;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		sio_setup();	}	if (bist == 0) {		//init_cpus(cpu_init_detectedx);		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	}	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	setup_ms9282_resource_map();	setup_coherent_ht_domain();	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	// It is said that we should start core1 after all core0 launched	start_other_cores();	//wait_all_other_cores_started(bsp_apicid);#endif	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn	init_timer(); /* Need to use TMICT to synchronize FID/VID. */	needs_reset = optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);	needs_reset |= mcp55_early_setup_x();	if (needs_reset) {		printk(BIOS_INFO, "ht reset -/n");		soft_reset();	}	//It's the time to set ctrl now;	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);	enable_smbus();	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const u16 spd_addr[] = {		DIMM0, DIMM1, 0, 0,		0, 0, 0, 0,		0, 0, 0, 0,		0, 0, 0, 0,	};	int needs_reset;	unsigned bsp_apicid = 0, nodes;	struct mem_controller ctrl[8];	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		sio_setup();	}	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx);	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	needs_reset = setup_coherent_ht_domain();	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	// It is said that we should start core1 after all core0 launched	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	needs_reset |= ht_setup_chains_x();	needs_reset |= ck804_early_setup_x();	if (needs_reset) {		print_info("ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	nodes = get_nodes();	//It's the time to set ctrl now;	fill_mem_ctrl(nodes, ctrl, spd_addr);	enable_smbus();	ms7135_set_nf4_voltage();	ms7135_set_ram_voltage();#if CONFIG_DEBUG_SMBUS	dump_spd_registers(&ctrl[0]);	dump_smbus_registers();#endif	sdram_initialize(nodes, ctrl);	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr [] = {		(0xa<<3)|0, (0xa<<3)|2, 0, 0,		(0xa<<3)|1, (0xa<<3)|3, 0, 0,#if CONFIG_MAX_PHYSICAL_CPUS > 1		(0xa<<3)|4, (0xa<<3)|6, 0, 0,		(0xa<<3)|5, (0xa<<3)|7, 0, 0,#endif	};	int needs_reset;	unsigned bsp_apicid = 0;	struct mem_controller ctrl[8];	unsigned nodes;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		sio_setup();		/* Setup the ck804 */		ck804_enable_rom();	}	if (bist == 0) {		bsp_apicid = init_cpus(cpu_init_detectedx);	}//	post_code(0x32); 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	uart_init();	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	setup_s2891_resource_map();#if 0	dump_pci_device(PCI_DEV(0, 0x18, 0));	dump_pci_device(PCI_DEV(0, 0x19, 0));#endif	needs_reset = setup_coherent_ht_domain();	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS==1	// It is said that we should start core1 after all core0 launched	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	needs_reset |= ht_setup_chains_x();	needs_reset |= ck804_early_setup_x();	if (needs_reset) {		printk(BIOS_INFO, "ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	nodes = get_nodes();	//It's the time to set ctrl now;	fill_mem_ctrl(nodes, ctrl, spd_addr);	enable_smbus();#if 0	dump_spd_registers(&cpu[0]);#endif#if 0	dump_smbus_registers();#endif	memreset_setup();	sdram_initialize(nodes, ctrl);#if 0	print_pci_devices();#endif#if 0	dump_pci_devices();#endif	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr [] = {                        RC0|DIMM0, RC0|DIMM2, 0, 0,                        RC0|DIMM1, RC0|DIMM3, 0, 0,#if CONFIG_MAX_PHYSICAL_CPUS > 1                        RC1|DIMM0, RC1|DIMM2, 0, 0,                        RC1|DIMM1, RC1|DIMM3, 0, 0,#endif#if CONFIG_MAX_PHYSICAL_CPUS > 2                        RC2|DIMM0, RC2|DIMM2, 0, 0,                        RC2|DIMM1, RC2|DIMM3, 0, 0,                        RC3|DIMM0, RC3|DIMM2, 0, 0,                        RC3|DIMM1, RC3|DIMM3, 0, 0,#endif	};        int needs_reset;        unsigned bsp_apicid = 0, nodes;        struct mem_controller ctrl[8];        if (bist == 0)                bsp_apicid = init_cpus(cpu_init_detectedx); 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);        console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);        setup_s4882_resource_map();	needs_reset = setup_coherent_ht_domain();        wait_all_core0_started();#if CONFIG_LOGICAL_CPUS==1        // It is said that we should start core1 after all core0 launched        start_other_cores();        wait_all_other_cores_started(bsp_apicid);#endif	// automatically set that for you, but you might meet tight space        needs_reset |= ht_setup_chains_x();       	if (needs_reset) {               	print_info("ht reset -/n");               	soft_reset();       	}        allow_all_aps_stop(bsp_apicid);        nodes = get_nodes();        //It's the time to set ctrl now;        fill_mem_ctrl(nodes, ctrl, spd_addr);	enable_smbus();	memreset_setup();	sdram_initialize(nodes, ctrl);	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr[] = {		// Node 0		DIMM0, DIMM2, 0, 0,		DIMM1, DIMM3, 0, 0,		// Node 1		DIMM4, DIMM6, 0, 0,		DIMM5, DIMM7, 0, 0,	};	unsigned bsp_apicid = 0;	int needs_reset = 0;	struct sys_info *sysinfo = &sysinfo_car;	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	it8712f_kill_watchdog();	it8712f_enable_3vsbsw();	console_init();	enable_rom_decode();	printk(BIOS_INFO, "now booting... /n");	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	/* Halt if there was a built in self test failure. */	report_bist_failure(bist);	setup_default_resource_map();	setup_coherent_ht_domain();	wait_all_core0_started();	printk(BIOS_INFO, "now booting... All core 0 started/n");#if CONFIG_LOGICAL_CPUS	/* It is said that we should start core1 after all core0 launched. */	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	init_timer();	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */	needs_reset = optimize_link_coherent_ht();	print_debug_hex8(needs_reset);	needs_reset |= optimize_link_incoherent_ht(sysinfo);	print_debug_hex8(needs_reset);	needs_reset |= k8t890_early_setup_ht();	print_debug_hex8(needs_reset);	vt8237_early_network_init(NULL);	vt8237_early_spi_init();	if (needs_reset) {		printk(BIOS_DEBUG, "ht reset -/n");		soft_reset();		printk(BIOS_DEBUG, "FAILED!/n");	}	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */	/* allow LDT STOP asserts */	vt8237_sb_enable_fid_vid();	enable_fid_change();	print_debug("after enable_fid_change/n");	init_fidvid_bsp(bsp_apicid);	/* Stop the APs so we can start them later in init. */	allow_all_aps_stop(bsp_apicid);	/* It's the time to set ctrl now. */	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);	enable_smbus();	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr[] = {		DIMM0, DIMM2, 0, 0,		DIMM1, DIMM3, 0, 0,#if CONFIG_MAX_PHYSICAL_CPUS > 1		DIMM4, DIMM6, 0, 0,		DIMM5, DIMM7, 0, 0,#endif	};	int needs_reset;	unsigned nodes, bsp_apicid = 0;	struct mem_controller ctrl[8];	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		sio_setup();	}	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx);	it8712f_24mhz_clkin();	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);#if 0	dump_pci_device(PCI_DEV(0, 0x18, 0));#endif	needs_reset = setup_coherent_ht_domain();	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	/* It is said that we should start core1 after all core0 launched. */	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	needs_reset |= ht_setup_chains_x();	needs_reset |= ck804_early_setup_x();	if (needs_reset) {		print_info("ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	nodes = get_nodes();	/* It's the time to set ctrl now. */	fill_mem_ctrl(nodes, ctrl, spd_addr);	enable_smbus();#if 0	dump_spd_registers(&ctrl[0]);	dump_smbus_registers();#endif	sdram_initialize(nodes, ctrl);#if 0	print_pci_devices();	dump_pci_devices();#endif	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };	int needs_reset = 0;	u32 bsp_apicid = 0;	msr_t msr;	struct cpuid_result cpuid1;	struct sys_info *sysinfo = &sysinfo_car;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		/* sb600_lpc_port80(); */		sb600_pci_port80();	}	technexion_post_code_init();	technexion_post_code(LED_MESSAGE_START);	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	enable_rs690_dev8();	sb600_lpc_init();	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	ite_kill_watchdog(GPIO_DEV);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	printk(BIOS_DEBUG, "bsp_apicid=0x%x/n", bsp_apicid);	setup_tim5690_resource_map();	setup_coherent_ht_domain();#if CONFIG_LOGICAL_CPUS	/* It is said that we should start core1 after all core0 launched */	wait_all_core0_started();	start_other_cores();#endif	wait_all_aps_started(bsp_apicid);	ht_setup_chains_x(sysinfo);	/* run _early_setup before soft-reset. */	rs690_early_setup();	sb600_early_setup();	/* Check to see if processor is capable of changing FIDVID  */	/* otherwise it will throw a GP# when reading FIDVID_STATUS */	cpuid1 = cpuid(0x80000007);	if ((cpuid1.edx & 0x6) == 0x6) {		/* Read FIDVID_STATUS */		msr=rdmsr(0xc0010042);		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x/n", msr.hi, msr.lo);		enable_fid_change();		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);		init_fidvid_bsp(bsp_apicid);		/* show final fid and vid */		msr=rdmsr(0xc0010042);		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x/n", msr.hi, msr.lo);	} else {		printk(BIOS_DEBUG, "Changing FIDVID not supported/n");	}	needs_reset = optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);	rs690_htinit();	printk(BIOS_DEBUG, "needs_reset=0x%x/n", needs_reset);	if (needs_reset) {		printk(BIOS_INFO, "ht reset -/n");		soft_reset();	}	speaker_init(255);	speaker_on_nodelay();	allow_all_aps_stop(bsp_apicid);	/* It's the time to set ctrl now; */	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p/n",		     sysinfo->nodes, sysinfo->ctrl, spd_addr);	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);	technexion_post_code(LED_MESSAGE_RAM);	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);	speaker_off_nodelay();	rs690_before_pci_init();	sb600_before_pci_init();//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr[] = {		// Node 0		DIMM0, DIMM2, 0, 0,		DIMM1, DIMM3, 0, 0,		// Node 1		DIMM4, DIMM6, 0, 0,		DIMM5, DIMM7, 0, 0,	};	struct sys_info *sysinfo = &sysinfo_car;	int needs_reset = 0;	unsigned bsp_apicid = 0;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0. */		/* Allow the HT devices to be found. */		enumerate_ht_chain();		sio_setup();	}	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	/* FIXME: This should be part of the Super I/O code/config. */	pnp_enter_ext_func_mode(SERIAL_DEV);	/* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */	pnp_write_config(SERIAL_DEV, 0x24, 0);	w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);	pnp_exit_ext_func_mode(SERIAL_DEV);	setup_mb_resource_map();	console_init();	report_bist_failure(bist); /* Halt upon BIST failure. */	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	print_debug("bsp_apicid=");	print_debug_hex8(bsp_apicid);	print_debug("/n");#if CONFIG_MEM_TRAIN_SEQ == 1	/* In BSP so could hold all AP until sysinfo is in RAM. */	set_sysinfo_in_ram(0);#endif	setup_coherent_ht_domain(); /* Routing table and start other core0. */	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	/* It is said that we should start core1 after all core0 launched	 * becase optimize_link_coherent_ht is moved out from	 * setup_coherent_ht_domain, so here need to make sure last core0 is	 * started, esp for two way system (there may be APIC ID conflicts in	 * that case).	 */	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	/* Set up chains and store link pair for optimization later. */	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */#if CONFIG_SET_FIDVID	{		msr_t msr = rdmsr(0xc0010042);		print_debug("begin msr fid, vid ");		print_debug_hex32(msr.hi);		print_debug_hex32(msr.lo);		print_debug("/n");	}	enable_fid_change();	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);	init_fidvid_bsp(bsp_apicid);	{		msr_t msr = rdmsr(0xc0010042);		print_debug("end   msr fid, vid ");		print_debug_hex32(msr.hi);		print_debug_hex32(msr.lo);		print_debug("/n");	}#endif	init_timer(); /* Need to use TMICT to synconize FID/VID. */	needs_reset |= optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);	needs_reset |= mcp55_early_setup_x();	/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */	if (needs_reset) {		print_info("ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	/* It's the time to set ctrl in sysinfo now. */	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);	enable_smbus();//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr[] = {		// first node		DIMM0, DIMM2, 0, 0,		DIMM1, DIMM3, 0, 0,		// second node		DIMM4, DIMM6, 0, 0,		DIMM5, DIMM7, 0, 0,	};	struct sys_info *sysinfo = &sysinfo_car;	int needs_reset;	unsigned bsp_apicid = 0;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		bcm5785_enable_lpc();		pc87417_enable_dev(RTC_DEV); /* Enable RTC */	}	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);//	setup_early_ipmi_serial();	pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid=%02x/n", bsp_apicid);#if CONFIG_MEM_TRAIN_SEQ == 1	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram#endif	setup_coherent_ht_domain();	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	// It is said that we should start core1 after all core0 launched	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,	 * So here need to make sure last core0 is started, esp for two way system,	 * (there may be apic id conflicts in that case)	*/	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	/* it will set up chains and store link pair for optimization later */	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn	bcm5785_early_setup();#if CONFIG_SET_FIDVID	{		msr_t msr;		msr=rdmsr(0xc0010042);		printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x/n", msr.hi, msr.lo);	}	enable_fid_change();	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);	init_fidvid_bsp(bsp_apicid);	// show final fid and vid	{		msr_t msr;		msr=rdmsr(0xc0010042);		printk(BIOS_DEBUG, "end msr fid, vid %08x %08x/n", msr.hi, msr.lo);	}#endif	needs_reset = optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);	// fidvid change will issue one LDTSTOP and the HT change will be effective too	if (needs_reset) {		printk(BIOS_INFO, "ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	//It's the time to set ctrl in sysinfo now;	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);	enable_smbus();	//do we need apci timer, tsc...., only debug need it for better output	/* all ap stopped? */	// init_timer(); // Need to use TMICT to synconize FID/VID	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr[] = {		// Node 0		DIMM0, DIMM2, 0, 0,		0, 0, 0, 0,		// Node 1		DIMM1, DIMM3, 0, 0,		0, 0, 0, 0,	};	unsigned bsp_apicid = 0;	int needs_reset = 0;	struct sys_info *sysinfo = &sysinfo_car;	sio_init();	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	enable_rom_decode();	print_info("now booting... fallback/n");	/* Is this a CPU only reset? Or is this a secondary CPU? */	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0. */		/* Allow the HT devices to be found. */		enumerate_ht_chain();	}	// FIXME why is this executed again? --->	sio_init();	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	enable_rom_decode();	// <--- FIXME why is this executed again?	print_info("now booting... real_main/n");	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	/* Halt if there was a built in self test failure. */	report_bist_failure(bist);	setup_default_resource_map();	setup_coherent_ht_domain();	wait_all_core0_started();	print_info("now booting... Core0 started/n");#if CONFIG_LOGICAL_CPUS	/* It is said that we should start core1 after all core0 launched. */	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	init_timer();	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */	needs_reset = optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);	needs_reset |= k8t890_early_setup_ht();	if (needs_reset) {		print_debug("ht reset -/n");		soft_reset();	}	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */	enable_fid_change();	init_fidvid_bsp(bsp_apicid);	/* Stop the APs so we can start them later in init. */	allow_all_aps_stop(bsp_apicid);	/* It's the time to set ctrl now. */	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);	enable_smbus();	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);	post_cache_as_ram();}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	struct sys_info *sysinfo = &sysinfo_car;	u32 bsp_apicid = 0, val, wants_reset;	msr_t msr;	timestamp_init(timestamp_get());	timestamp_add_now(TS_START_ROMSTAGE);	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		set_bsp_node_CHtExtNodeCfgEn();		enumerate_ht_chain();		sio_setup();	}	post_code(0x30);	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	post_code(0x32);	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	if (CONFIG_MAX_PHYSICAL_CPUS != 2)		printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!/n", CONFIG_MAX_PHYSICAL_CPUS);	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	val = cpuid_eax(1);	printk(BIOS_DEBUG, "BSP Family_Model: %08x/n", val);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid = %02x/n", bsp_apicid);	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx/n", cpu_init_detectedx);	/* Setup sysinfo defaults */	set_sysinfo_in_ram(0);	update_microcode(val);	post_code(0x33);	cpuSetAMDMSR(0);	post_code(0x34);	amd_ht_init(sysinfo);	post_code(0x35);	/* Setup nodes PCI space and start core 0 AP init. */	finalize_node_setup(sysinfo);	/* Setup any mainboard PCI settings etc. */	setup_mb_resource_map();	post_code(0x36);	/* wait for all the APs core0 started by finalize_node_setup. */	/* FIXME: A bunch of cores are going to start output to serial at once.	 * It would be nice to fix up prink spinlocks for ROM XIP mode.	 * I think it could be done by putting the spinlock flag in the cache	 * of the BSP located right after sysinfo.	 */	wait_all_core0_started();	if (IS_ENABLED(CONFIG_SET_FIDVID)) {		msr = rdmsr(0xc0010071);		printk(BIOS_DEBUG, "/nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);		post_code(0x39);		if (!warm_reset_detect(0)) {			// BSP is node 0			init_fidvid_bsp(bsp_apicid, sysinfo->nodes);		} else {			init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0		}		post_code(0x3A);		/* show final fid and vid */		msr = rdmsr(0xc0010071);		printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);	}	if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {		/* Core0 on each node is configured. Now setup any additional cores. */		printk(BIOS_DEBUG, "start_other_cores()/n");		start_other_cores(bsp_apicid);		post_code(0x37);		wait_all_other_cores_started(bsp_apicid);	}	printk(BIOS_DEBUG, "set_ck804_base_unit_id()/n");	ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID);	post_code(0x38);//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };	int needs_reset = 0;	u32 bsp_apicid = 0;	msr_t msr;	struct cpuid_result cpuid1;	struct sys_info *sysinfo = &sysinfo_car;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		sb600_lpc_port80();		/* sb600_pci_port80(); */	}	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	enable_rs690_dev8();	sb600_lpc_init();	/* Pistachio used a FPGA to enable serial debug instead of a SIO	 * and it doesn't require any special setup. */	console_init();	post_code(0x03);	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	printk(BIOS_DEBUG, "bsp_apicid=0x%x/n", bsp_apicid);	setup_pistachio_resource_map();	setup_coherent_ht_domain();#if CONFIG_LOGICAL_CPUS	/* It is said that we should start core1 after all core0 launched */	wait_all_core0_started();	start_other_cores();#endif	wait_all_aps_started(bsp_apicid);	/* it will set up chains and store link pair for optimization later,	 * it will init sblnk and sbbusn, nodes, sbdn */	ht_setup_chains_x(sysinfo);	/* run _early_setup before soft-reset. */	rs690_early_setup();	sb600_early_setup();	post_code(0x04);	/* Check to see if processor is capable of changing FIDVID  */	/* otherwise it will throw a GP# when reading FIDVID_STATUS */	cpuid1 = cpuid(0x80000007);	if ((cpuid1.edx & 0x6) == 0x6) {		/* Read FIDVID_STATUS */		msr=rdmsr(0xc0010042);		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x/n", msr.hi, msr.lo);		enable_fid_change();		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);		init_fidvid_bsp(bsp_apicid);		/* show final fid and vid */		msr=rdmsr(0xc0010042);		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x/n", msr.hi, msr.lo);	} else {		printk(BIOS_DEBUG, "Changing FIDVID not supported/n");	}	post_code(0x05);	needs_reset = optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);	rs690_htinit();	printk(BIOS_DEBUG, "needs_reset=0x%x/n", needs_reset);	post_code(0x06);	if (needs_reset) {		print_info("ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	/* It's the time to set ctrl now; */	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p/n",		     sysinfo->nodes, sysinfo->ctrl, spd_addr);	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);	post_code(0x07);	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);	post_code(0x08);//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){/* The SPD is being read from the CPU1 (marked CPU2 on the board) and we   don't know how to switch the SMBus to decode the CPU0 SPDs. So, The   memory on each CPU must be an exact match. */	static const uint16_t spd_addr[] = {		// Node 0		RC0 | DIMM0, RC0 | DIMM2,		RC0 | DIMM4, RC0 | DIMM6,		RC0 | DIMM1, RC0 | DIMM3,		RC0 | DIMM5, RC0 | DIMM7,		// Node 1		RC1 | DIMM0, RC1 | DIMM2,		RC1 | DIMM4, RC1 | DIMM6,		RC1 | DIMM1, RC1 | DIMM3,		RC1 | DIMM5, RC1 | DIMM7,	};	struct sys_info *sysinfo = &sysinfo_car;	int needs_reset = 0;	unsigned bsp_apicid = 0;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		sio_setup();	}	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	w83627hf_set_clksel_48(DUMMY_DEV);	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	setup_mb_resource_map();	printk(BIOS_DEBUG, "bsp_apicid=%02x/n", bsp_apicid);	set_sysinfo_in_ram(0);	// in BSP so could hold all ap until sysinfo is in ram#if CONFIG_DEBUG_SMBUS	dump_smbus_registers();#endif	setup_coherent_ht_domain();	// routing table and start other core0	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	// It is said that we should start core1 after all core0 launched	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,	 * So here need to make sure last core0 is started, esp for two way system,	 * (there may be apic id conflicts in that case)	 */	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	/* it will set up chains and store link pair for optimization later */	ht_setup_chains_x(sysinfo);	// it will init sblnk and sbbusn, nodes, sbdn#if CONFIG_SET_FIDVID	{		msr_t msr;		msr = rdmsr(0xc0010042);		printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x/n", msr.hi, msr.lo);	}	enable_fid_change();	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);	init_fidvid_bsp(bsp_apicid);	// show final fid and vid	{		msr_t msr;		msr = rdmsr(0xc0010042);		printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x/n", msr.hi, msr.lo);	}#endif	init_timer(); /* Need to use TMICT to synchronize FID/VID. */	needs_reset |= optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);	needs_reset |= mcp55_early_setup_x();	// fidvid change will issue one LDTSTOP and the HT change will be effective too	if (needs_reset) {		printk(BIOS_INFO, "ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	//It's the time to set ctrl in sysinfo now;	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){       static const uint16_t spd_addr[] = {                      //first node                       RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,                       RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,                       //second node                       RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,                       RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,       };	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +		CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);        int needs_reset;        unsigned bsp_apicid = 0;        if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		enumerate_ht_chain();		bcm5785_enable_lpc();		//enable RTC		pc87417_enable_dev(RTC_DEV);        }        if (bist == 0)               bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);        pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);        console_init();//     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);       /* Halt if there was a built in self test failure */       report_bist_failure(bist);       printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);       setup_ms9185_resource_map();#if 0       dump_pci_device(PCI_DEV(0, 0x18, 0));       dump_pci_device(PCI_DEV(0, 0x19, 0));#endif       print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("/n");       setup_coherent_ht_domain();       wait_all_core0_started();#if CONFIG_LOGICAL_CPUS==1        // It is said that we should start core1 after all core0 launched       /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,        * So here need to make sure last core0 is started, esp for two way system,        * (there may be apic id conflicts in that case)        */        start_other_cores();//bx_a010-     wait_all_other_cores_started(bsp_apicid);#endif       /* it will set up chains and store link pair for optimization later */       ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn       bcm5785_early_setup();#if 0       //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.        needs_reset = optimize_link_coherent_ht();        needs_reset |= optimize_link_incoherent_ht(sysinfo);#endif#if CONFIG_SET_FIDVID        {                msr_t msr;                msr=rdmsr(0xc0010042);                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("/n");        }        enable_fid_change();        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);        init_fidvid_bsp(bsp_apicid);        // show final fid and vid        {                msr_t msr;                msr=rdmsr(0xc0010042);                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("/n");        }#endif#if 1       needs_reset = optimize_link_coherent_ht();       needs_reset |= optimize_link_incoherent_ht(sysinfo);        // fidvid change will issue one LDTSTOP and the HT change will be effective too        if (needs_reset) {                print_info("ht reset -/n");                soft_reset();        }#endif       allow_all_aps_stop(bsp_apicid);//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const uint16_t spd_addr[] = {			//first node                        RC0|DIMM0, RC0|DIMM2, 0, 0,                        RC0|DIMM1, RC0|DIMM3, 0, 0,#if CONFIG_MAX_PHYSICAL_CPUS > 1			//second node                        RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,                        RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,#endif#if CONFIG_MAX_PHYSICAL_CPUS > 2                        // third node                        RC2|DIMM0, RC2|DIMM2, 0, 0,                        RC2|DIMM1, RC2|DIMM3, 0, 0,                        // four node                        RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,                        RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,#endif	};	struct sys_info *sysinfo = &sysinfo_car;        int needs_reset;        unsigned bsp_apicid = 0;#if CONFIG_SET_FIDVID	struct cpuid_result cpuid1;#endif        if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);        setup_mb_resource_map();#if 0        dump_pci_device(PCI_DEV(0, 0x18, 0));	dump_pci_device(PCI_DEV(0, 0x19, 0));#endif	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("/n");        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram	setup_coherent_ht_domain(); // routing table and start other core0	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS        // It is said that we should start core1 after all core0 launched	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,	 * So here need to make sure last core0 is started, esp for two way system,	 * (there may be apic id conflicts in that case)	 */        start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	/* it will set up chains and store link pair for optimization later */        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn#if 0	//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.        needs_reset = optimize_link_coherent_ht();        needs_reset |= optimize_link_incoherent_ht(sysinfo);#endif#if CONFIG_SET_FIDVID	/* Check to see if processor is capable of changing FIDVID  */	/* otherwise it will throw a GP# when reading FIDVID_STATUS */	cpuid1 = cpuid(0x80000007);	if ((cpuid1.edx & 0x6) == 0x6) {        {		/* Read FIDVID_STATUS */                msr_t msr;                msr=rdmsr(0xc0010042);                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("/n");        }	enable_fid_change();	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);        init_fidvid_bsp(bsp_apicid);        // show final fid and vid        {                msr_t msr;                msr=rdmsr(0xc0010042);                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("/n");        }	} else {		print_debug("Changing FIDVID not supported/n");	}//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	static const u16 spd_addr[] = {		DIMM0, DIMM2, 0, 0,	/* Channel A (DIMM_A1, DIMM_A2) */		DIMM1, DIMM3, 0, 0,	/* Channel B (DIMM_B1, DIMM_B2) */	};	struct sys_info *sysinfo = &sysinfo_car;	int needs_reset = 0;	unsigned bsp_apicid = 0;	if (!cpu_init_detectedx && boot_cpu()) {		/* Allow the HT devices to be found. */		enumerate_ht_chain();		sio_setup();	}	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	setup_mb_resource_map();	report_bist_failure(bist);	console_init();	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo, sysinfo + 1);	printk(BIOS_DEBUG, "bsp_apicid=0x%02x/n", bsp_apicid);	/* In BSP so could hold all AP until sysinfo is in RAM. */	set_sysinfo_in_ram(0);	setup_coherent_ht_domain(); /* Routing table and start other core0. */	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	/*	 * It is said that we should start core1 after all core0 launched	 * becase optimize_link_coherent_ht is moved out from	 * setup_coherent_ht_domain, so here need to make sure last core0 is	 * started, esp for two way system (there may be APIC ID conflicts in	 * that case).	 */	start_other_cores();	wait_all_other_cores_started(bsp_apicid);#endif	/* Set up chains and store link pair for optimization later. */	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */	/* TODO: FIDVID */	init_timer(); /* Need to use TMICT to synchronize FID/VID. */	needs_reset |= optimize_link_coherent_ht();	needs_reset |= optimize_link_incoherent_ht(sysinfo);	needs_reset |= mcp55_early_setup_x();	/*	 * FIDVID change will issue one LDTSTOP and the HT change will be	 * effective too.	 */	if (needs_reset) {		printk(BIOS_INFO, "ht reset -/n");		soft_reset();	}	allow_all_aps_stop(bsp_apicid);	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);	enable_smbus();	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);	/* BSP switch stack to RAM and copy sysinfo RAM now. */	post_cache_as_ram();}