自学教程：C++ wait_on_value函数代码示例

static void configure_abe_dpll(u32 clk_index){	struct dpll_param *dpll_param_p;	/* Select sys_clk as ref clk for ABE dpll */	sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);	/* Unlock the ABE dpll */	sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);	/* Program ABE DPLL */	dpll_param_p = &abe_dpll_param[clk_index];	/* Disable autoidle */	sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0);	sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n);	/* Force DPLL CLKOUTHIF to stay enabled */	sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500);	sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2);	sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1);	/* Force DPLL CLKOUTHIF to stay enabled */	sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100);	sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3);	sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1);	/* Lock the abe dpll */	sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY);}

static void iva_init_36xx(u32 sil_index, u32 clk_index){	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;	dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();	/* Moving to the right sysclk */	ptr += clk_index;	/* IVA DPLL */	/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */	sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);	wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */	sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);	/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */	sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);	/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */	sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);	/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */	sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);	wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);}

static void configure_iva_dpll(u32 clk_index){	dpll_param *dpll_param_p;	/* Unlock the IVA dpll */	sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY);	/* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */	sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1);	/* Program IVA DPLL */	dpll_param_p = &iva_dpll_param[clk_index];	sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */	/* Set M,N,M4,M5 */	sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n);	sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4);	sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5);	/* Lock the iva dpll */	sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY);	return;}

static void configure_mpu_dpll(u32 clk_index){	dpll_param *dpll_param_p;	/* Unlock the MPU dpll */	sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY);	/* Program MPU DPLL */	dpll_param_p = &mpu_dpll_param[clk_index];	sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */	/* Set M,N,M2 values */	sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n);	sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2);	sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1);	/* Lock the mpu dpll */	sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY);	return;}

static void configure_per_dpll(u32 clk_index){	dpll_param *dpll_param_p;	/* Unlock the PER dpll */	sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY);	/* Program PER DPLL */	dpll_param_p = &per_dpll_param[clk_index];	/* Disable autoidle */	sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0);	sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n);	sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2);	sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3);	sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4);	sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5);	sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6);	sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7);	/* Lock the per dpll */	sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY);	return;}

static void configure_usb_dpll(u32 clk_index){	dpll_param *dpll_param_p;	/* Select the 60Mhz clock 480/8 = 60*/	sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1);	/* Unlock the USB dpll */	sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY);	/* Program USB DPLL */	dpll_param_p = &usb_dpll_param[clk_index];	/* Disable autoidle */	sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0);	sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n);	/* Force DPLL CLKOUT to stay active */	sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100);	sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2);	/* Lock the usb dpll */	sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY);	/* force enable the CLKDCOLDO clock */	sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100);	return;}

static int isolate_io(u32 isolate){	if (isolate) {		clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ,				SDCARD_PWRDNZ);		clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ,				SDCARD_BIAS_PWRDNZ);	}	/* Override control on ISOCLKIN signal to IO pad ring. */	clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,			PMCTRL_ISOCLK_OVERRIDE_CTRL);	if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK,			   (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))		return ERR_DEISOLATE_IO << isolate;	/* Isolate/Deisolate IO */	clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK,			isolate << CTRL_ISOLATE_SHIFT);	/* Dummy read to add delay t > 10ns */	readl((*ctrl)->ctrl_core_sma_sw_0);	/* Return control on ISOCLKIN to hardware */	clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,			PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL);	if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK,			   0 << PMCTRL_ISOCLK_STATUS_SHIFT,			   (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))		return ERR_DEISOLATE_IO << isolate;	return 0;}

/* to remove warning about unused function; will be deleted in decruft patch */static void configure_core_dpll(int clk_index){	struct dpll_param *dpll_param_p;	/* Get the sysclk speed from cm_sys_clksel	 * Set it to 38.4 MHz, in case ROM code is bypassed	 */	if (!clk_index)		return;	/* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */	sr32(CM_CLKSEL_CORE, 0, 32, 0x110);	/* Unlock the CORE dpll */	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);	/* Program Core DPLL */	switch (omap_revision()) {	case OMAP4430_ES1_0:		dpll_param_p = &core_dpll_param_l3_190[clk_index];		break;	case OMAP4430_ES2_0:		dpll_param_p = &core_dpll_param[clk_index];		break;	case OMAP4430_ES2_1:	default:		dpll_param_p = &core_dpll_param_ddr400[clk_index];		break;	}	/* Disable autoidle */	sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);	sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);	sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);	sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);	sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);	sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);	sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);	sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);	if (omap_revision() == OMAP4430_ES1_0) {		/* Do this only on ES1.0 */		sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);		sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);		sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);		sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);		sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);		sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);	}	/* Lock the core dpll */	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);}

static void configure_abe_dpll(u32 clk_index){	dpll_param *dpll_param_p;	u32 clkmode_value;	/* Select sys_clk as ref clk for ABE dpll */#ifdef CONFIG_OMAP4_ABE_SYSCK	sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);#endif	/* Unlock the ABE dpll */	sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);	/* Program ABE DPLL */	dpll_param_p = &abe_dpll_param[clk_index];	/* Disable autoidle */	sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0);	/*	 * Enable higher frequencies when fed from 32KHz clk.  Sets	 * DPLL_REGM4XEN, DPLL_LPMODE, DPLL_RELOCK_RAMP_EN, DPLL_RAMP_RATE and	 * DPLL_DRIFTGUARD_EN in the CM_CLKMODE_DPLL_ABE register.	 *	 * Public TRM does not cover all of this: DPLL_RAMP_RATE (bit 5)	 * selects time spent at each stage of clock ramping process.  We	 * spend 4 REFCLKs.  DPLL_RELOCK_RAMP_EN (bit 9) enables the clock	 * ramping feature, using the rate specified in DPLL_RAMP_RATE.	 *	 * Also the DPLL_REGM4XEN bit provides a magic 4x multplier to	 * existing MN dividers.  This is how a DPLL driven from 32KHz clock	 * can achieve 196.608MHz.	 */#ifndef CONFIG_OMAP4_ABE_SYSCK	clkmode_value = (BIT5 | BIT8 | BIT9 | BIT10 | BIT11);	sr32(CM_CLKMODE_DPLL_ABE, 0, 12, clkmode_value);#endif	sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_ABE, 0, 7, dpll_param_p->n);	/* Force DPLL CLKOUTHIF to stay enabled */	sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500);	sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2);	sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1);	/* Force DPLL CLKOUTHIF to stay enabled */	sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100);	sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3);	sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1);	/* Lock the abe dpll */	sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY);	return;}

static void dpll4_init_34xx(u32 sil_index, u32 clk_index){    struct prcm *prcm_base = (struct prcm *)PRCM_BASE;    dpll_param *ptr = (dpll_param *) get_per_dpll_param();    /* Moving it to the right sysclk base */    ptr = ptr + clk_index;    /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */    clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);    wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);    /*     * Errata 1.50 Workaround for OMAP3 ES1.0 only     * If using default divisors, write default divisor + 1     * and then the actual divisor value     */    /* M6 */    clrsetbits_le32(&prcm_base->clksel1_emu,                    0x1F000000, (PER_M6X2 + 1) << 24);    clrsetbits_le32(&prcm_base->clksel1_emu,                    0x1F000000, PER_M6X2 << 24);    /* M5 */    clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));    clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);    /* M4 */    clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));    clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);    /* M3 */    clrsetbits_le32(&prcm_base->clksel_dss,                    0x00001F00, (PER_M3X2 + 1) << 8);    clrsetbits_le32(&prcm_base->clksel_dss,                    0x00001F00, PER_M3X2 << 8);    /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */    clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));    clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);    /* Workaround end */    /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */    clrsetbits_le32(&prcm_base->clksel2_pll,                    0x0007FF00, ptr->m << 8);    /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */    clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);    /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */    clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);    /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */    clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);    wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);}

/********************************************************************************* * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default). *   -- called from SRAM, or Flash (using temp SRAM stack). *********************************************************************************/void prcm_init(void){	u32 div;	void (*f_lock_pll) (u32, u32, u32, u32);	extern void *_end_vect, *_start;	f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);	__raw_writel(0, CM_FCLKEN1_CORE);	   /* stop all clocks to reduce ringing */	__raw_writel(0, CM_FCLKEN2_CORE);	   /* may not be necessary */	__raw_writel(0, CM_ICLKEN1_CORE);	__raw_writel(0, CM_ICLKEN2_CORE);	__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);	/* set DPLL out */	__raw_writel(MPU_DIV, CM_CLKSEL_MPU);	/* set MPU divider */	__raw_writel(DSP_DIV, CM_CLKSEL_DSP);	/* set dsp and iva dividers */	__raw_writel(GFX_DIV, CM_CLKSEL_GFX);	/* set gfx dividers */	div = BUS_DIV;	__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */	sdelay(1000);	if(running_in_sram()){		/* If running fully from SRAM this is OK.  The Flash bus drops out for just a little.		* but then comes back.  If running from Flash this sequence kills you, thus you need		* to run it using CONFIG_PARTIAL_SRAM.		*/		__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */		wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */		sdelay(1000);		/* set clock selection and dpll dividers. */		__raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);	 /* set pll for target rate */		__raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */		sdelay(10000);		__raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */		sdelay(10000);		wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY);  /*wait for dpll lock */	}else if(running_in_flash()){		/* if running from flash, need to jump to small relocated code area in SRAM.		 * This is the only safe spot to do configurations from.		 */		(*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);	}	__raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL);   /* enable apll */	wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);	/* wait for apll lock */	sdelay(1000);}

static void do_scale_vcore(u32 vcore_reg, u32 volt_mv){	u32 temp, offset_code;	u32 step = 12660; /* 12.66 mV represented in uV */	u32 offset = volt_mv;	/* convert to uV for better accuracy in the calculations */	offset *= 1000;	if (omap_revision() == OMAP4430_ES1_0)		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;	else		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;	offset_code = (offset + step - 1) / step;	/* The code starts at 1 not 0 */	offset_code++;	debug("do_scale_vcore: volt - %d offset_code - 0x%x/n", volt_mv,		offset_code);	temp = SMPS_I2C_SLAVE_ADDR |	    (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |	    (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |	    PRM_VC_VAL_BYPASS_VALID_BIT;	writel(temp, &prcm->prm_vc_val_bypass);	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,				&prcm->prm_vc_val_bypass, LDELAY)) {		printf("Scaling voltage failed for 0x%x/n", vcore_reg);	}}

void freq_update_core(void){	u32 freq_config1 = 0;	const struct dpll_params *core_dpll_params;	core_dpll_params = get_core_dpll_params();	/* Put EMIF clock domain in sw wakeup mode */	enable_clock_domain(&prcm->cm_memif_clkstctrl,				CD_CLKCTRL_CLKTRCTRL_SW_WKUP);	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);	freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |	    SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;	freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &				SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;	freq_config1 |= (core_dpll_params->m2 <<			SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &			SHADOW_FREQ_CONFIG1_M2_DIV_MASK;	writel(freq_config1, &prcm->cm_shadow_freq_config1);	if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,				&prcm->cm_shadow_freq_config1, LDELAY)) {		puts("FREQ UPDATE procedure failed!!");		hang();	}	/* Put EMIF clock domain back in hw auto mode */	enable_clock_domain(&prcm->cm_memif_clkstctrl,				CD_CLKCTRL_CLKTRCTRL_HW_AUTO);	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);}

static void configure_mpu_dpll_no_lock(){	dpll_param *dpll_param_p;	u32 clk_index;	clk_index = readl(CM_SYS_CLKSEL);	if (!clk_index)		*(volatile int*)0x4A306110 = 0x7; //CM_SYS_CLKSEL	clk_index = clk_index - 1;	/* Unlock the MPU dpll */	sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY);	/* Program MPU DPLL */	dpll_param_p = &mpu_dpll_param[clk_index];	sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */	/* Set M,N,M2 values */	sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n);	sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2);	sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1);	return;}

static void do_scale_tps62361(u32 reg, u32 volt_mv){	u32 temp, step;	step = volt_mv - TPS62361_BASE_VOLT_MV;	step /= 10;	/*	 * Select SET1 in TPS62361:	 * VSEL1 is grounded on board. So the following selects	 * VSEL1 = 0 and VSEL0 = 1	 */	omap_set_gpio_direction(TPS62361_VSEL0_GPIO, 0);	omap_set_gpio_dataout(TPS62361_VSEL0_GPIO, 1);	temp = TPS62361_I2C_SLAVE_ADDR |	    (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |	    (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |	    PRM_VC_VAL_BYPASS_VALID_BIT;	debug("do_scale_tps62361: volt - %d step - 0x%x/n", volt_mv, step);	writel(temp, &prcm->prm_vc_val_bypass);	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,				&prcm->prm_vc_val_bypass, LDELAY)) {		puts("Scaling voltage failed for vdd_mpu from TPS/n");	}}

static inline void wait_for_bypass(const struct dpll_regs *dpll_regs){	if (!wait_on_value(ST_DPLL_CLK_MASK, 0,			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {		printf("Bypassing DPLL failed 0x%x/n",		       dpll_regs->cm_clkmode_dpll);	}}

void lock_core_dpll(void){	/* Lock the core dpll */	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);	return;}

static void dpll5_init_36xx(u32 sil_index, u32 clk_index){	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;	dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();	/* Moving it to the right sysclk base */	ptr = ptr + clk_index;	/* PER2 DPLL (DPLL5) */	sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);	wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);	sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */	sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */	sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/	sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK);   /* lock mode */	wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);}

static inline void wait_for_bypass(u32 const base){	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;	if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,				LDELAY)) {		printf("Bypassing DPLL failed %x/n", base);	}}

static inline void wait_for_lock(const struct dpll_regs *dpll_regs){	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {		printf("DPLL locking failed for 0x%x LDELAY %d/n",		       dpll_regs->cm_clkmode_dpll, LDELAY);		hang();	}}

static void iva_dpll_init_36XX(int clk_index, int sil_index){	dpll_param *iva;	iva = _get_iva_dpll(clk_index, sil_index);	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);	wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);	/* IVA bypass clock set to CORECLK/2=(100) at OPP1 */	sr32(CM_CLKSEL1_PLL_IVA2, 19, 3, 2);	/* set CLK_SRC */	sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, iva->m);	sr32(CM_CLKSEL1_PLL_IVA2, 0,  7, iva->n);	sr32(CM_CLKSEL2_PLL_IVA2, 0,  5, iva->m2);	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);	/* lock mode */	wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);}

static inline void wait_for_lock(u32 const base){	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,		&dpll_regs->cm_idlest_dpll, LDELAY)) {		printf("DPLL locking failed for %x/n", base);		hang();	}}

static void dpll4_init_36xx(u32 sil_index, u32 clk_index){    struct prcm *prcm_base = (struct prcm *)PRCM_BASE;    struct dpll_per_36x_param *ptr;    ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();    /* Moving it to the right sysclk base */    ptr += clk_index;    /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */    clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);    wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);    /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */    clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);    /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */    clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);    /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */    clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);    /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */    clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);    /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */    clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);    /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */    clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);    /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */    clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);    /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */    clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);    /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */    clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);    wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);}

static void dpll4_init_36xx(u32 sil_index, u32 clk_index){	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;	struct dpll_per_36x_param *ptr;	ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();	/* Moving it to the right sysclk base */	ptr += clk_index;	/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */	sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);	wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);	/* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */	sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);	/* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */	sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);	/* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */	sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);	/* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */	sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */	sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);	/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */	sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);	/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */	sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);	/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */	sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);	/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */	sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);}

static int update_delay_mechanism(u32 base){	/* Initiate the reload of calibrated values. */	clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK,			CFG_REG_ROM_READ_START);	if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END,			   (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))		return ERR_UPDATE_DELAY;	return 0;}

static void per_dpll_init_34XX(int clk_index){	dpll_per_param *dpll_param_p;	sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);	wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);	/* Getting the base address to PER  DPLL param table*/		/* Set N */	dpll_param_p = (dpll_param *)get_per_dpll_param();	/* Moving it to the right sysclk base */	dpll_param_p = dpll_param_p + clk_index;	/* Errata 1.50 Workaround for 3430 ES1.0 only */	/* If using default divisors, write default divisor + 1	   and then the actual divisor value */	/* Need to change it to silicon and revisino check */	if(1) {		sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2 + 1);	/* set M6 */		sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2);		/* set M6 */		sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2 + 1);	/* set M5 */		sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2);		/* set M5 */		sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2 + 1);	/* set M4 */		sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2);		/* set M4 */		sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2 + 1);	/* set M3 */		sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2);		/* set M3 */		sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2 + 1);/* set M2 */		sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2);	/* set M2 */	}	else {		sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2);	/* set M6 */		sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2);	/* set M5 */		sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2);	/* set M4 */		sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2);	/* set M3 */		sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2);	/* set M2 */	}	sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m);	/* set m */	sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n);	/* set n */	sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */	sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);	/* lock mode */	wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);}

static void iva_dpll_init_34XX(int clk_index, int sil_index){	dpll_param *dpll_param_p;	/* Getting the base address to IVA DPLL param table*/	dpll_param_p = (dpll_param *)get_iva_dpll_param();	/* Moving it to the right sysclk and ES rev base */	dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;	/* IVA DPLL (set to 12*20=240MHz) */	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);	wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);	sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2);	/* set M2 */	/* IVA bypass clock set to CORECLK/4=(83Mhz) at OPP1 */	sr32(CM_CLKSEL1_PLL_IVA2, 19, 3, 4);		/* set CLK_SRC */	sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m);	/* set M */	sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n);	/* set N */	sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel);	/* FREQSEL */	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);	/* lock mode */	wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);}

void configure_core_dpll_no_lock(void){	struct dpll_param *dpll_param_p = NULL;	u32 clk_index;	/* Get the sysclk speed from cm_sys_clksel	 * Set it to 38.4 MHz, in case ROM code is bypassed	 */	__raw_writel(0x7, CM_SYS_CLKSEL);	clk_index = 7;	clk_index = clk_index - 1;	/* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */	sr32(CM_CLKSEL_CORE, 0, 32, 0x110);	/* Unlock the CORE dpll */	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);	/* Program Core DPLL */	switch (omap_revision()) {	case OMAP4430_ES1_0:		dpll_param_p = &core_dpll_param_l3_190[clk_index];		break;	case OMAP4430_ES2_0:		dpll_param_p = &core_dpll_param[clk_index];		break;	case OMAP4430_ES2_1:	default:		dpll_param_p = &core_dpll_param_ddr400[clk_index];		break;	}	/* Disable autoidle */	sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);	sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);	sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);	sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);	sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);	sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);	sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);	sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);	sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);	sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);	sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);	sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);	sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);	sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);}

void lock_core_dpll_shadow(void){	dpll_param *dpll_param_p = 0;	u32 clk_index;	u32 temp;	temp = __raw_readl(CM_MEMIF_CLKSTCTRL);	temp &= (~3);	temp |= 2;	__raw_writel(temp, CM_MEMIF_CLKSTCTRL);	while(__raw_readl(CM_MEMIF_EMIF_1_CLKCTRL) & 0x30000)		;	while(__raw_readl(CM_MEMIF_EMIF_2_CLKCTRL) & 0x30000)		;	/* Lock the core dpll using freq update method */	/*(CM_CLKMODE_DPLL_CORE) */	__raw_writel(0x0A, 0x4A004120);	clk_index = 6;	if(omap_revision() == OMAP4430_ES1_0)		dpll_param_p = &core_dpll_param_l3_190[clk_index];	else if (omap_revision() == OMAP4430_ES2_0)		dpll_param_p = &core_dpll_param[clk_index];	else if (omap_revision() >= OMAP4430_ES2_1)		dpll_param_p = &core_dpll_param_ddr400[clk_index];	/* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,	 * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1	 */	__raw_writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260);	/* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */	while((__raw_readl(0x4A004260) & 0x1) == 0x1)		;	/* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);	//lock_core_dpll();	while(__raw_readl(CM_MEMIF_EMIF_1_CLKCTRL) & 0x30000)		;	while(__raw_readl(CM_MEMIF_EMIF_2_CLKCTRL) & 0x30000)		;	__raw_writel(temp|3, CM_MEMIF_CLKSTCTRL);	return;}

static void configure_core_dpll(u32 clk_index){	dpll_param *dpll_param_p;	/* Get the sysclk speed from cm_sys_clksel	 * Set it to 38.4 MHz, in case ROM code is bypassed	 */	if (!clk_index)		*(volatile int*)0x4A306110 = 0x7; //CM_SYS_CLKSEL	/* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */	sr32(CM_CLKSEL_CORE, 0, 32, 0x110);	/* Unlock the CORE dpll */	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);	/* Program USB DPLL */	dpll_param_p = &core_dpll_param[clk_index];	/* Disable autoidle */	sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);	sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);	sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);	sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);	sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);	sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);	sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);	sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);	sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);	/* Lock the core dpll */	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);	return;}