自学教程：C++ warm_reset_detect函数代码示例

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	struct sys_info *sysinfo = &sysinfo_car;	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };	u32 bsp_apicid = 0, val;	msr_t msr;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		/* mov bsp to bus 0xff when > 8 nodes */		set_bsp_node_CHtExtNodeCfgEn();		enumerate_ht_chain();		sb7xx_51xx_pci_port80();	}	post_code(0x30);	if (bist == 0) {		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */		/* All cores run this but the BSP(node0,core0) is the only core that returns. */	}	post_code(0x32);	enable_rs780_dev8();	sb7xx_51xx_lpc_init();	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	ite_kill_watchdog(GPIO_DEV);	console_init();//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	// Load MPB	val = cpuid_eax(1);	printk(BIOS_DEBUG, "BSP Family_Model: %08x /n", val);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid = %02x /n", bsp_apicid);	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx /n", cpu_init_detectedx);	/* Setup sysinfo defaults */	set_sysinfo_in_ram(0);	update_microcode(val);	post_code(0x33);	cpuSetAMDMSR();	post_code(0x34);	amd_ht_init(sysinfo);	post_code(0x35);	/* Setup nodes PCI space and start core 0 AP init. */	finalize_node_setup(sysinfo);	/* Setup any mainboard PCI settings etc. */	setup_mb_resource_map();	post_code(0x36);	/* wait for all the APs core0 started by finalize_node_setup. */	/* FIXME: A bunch of cores are going to start output to serial at once.	   It would be nice to fixup prink spinlocks for ROM XIP mode.	   I think it could be done by putting the spinlock flag in the cache	   of the BSP located right after sysinfo.	 */	wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS	/* Core0 on each node is configured. Now setup any additional cores. */	printk(BIOS_DEBUG, "start_other_cores()/n");	start_other_cores();	post_code(0x37);	wait_all_other_cores_started(bsp_apicid); #endif	post_code(0x38);	/* run _early_setup before soft-reset. */	rs780_early_setup();	sb7xx_51xx_early_setup(); #if CONFIG_SET_FIDVID	msr = rdmsr(0xc0010071);	printk(BIOS_DEBUG, "/nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x /n", msr.hi, msr.lo);	/* FIXME: The sb fid change may survive the warm reset and only	   need to be done once.*/	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);	post_code(0x39);	if (!warm_reset_detect(0)) {			// BSP is node 0		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);	} else {//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	struct sys_info *sysinfo = &sysinfo_car;	u32 bsp_apicid = 0, val, wants_reset;	msr_t msr;	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		set_bsp_node_CHtExtNodeCfgEn();		enumerate_ht_chain();		sio_setup();	}	post_code(0x30);	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	post_code(0x32);	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	val = cpuid_eax(1);	printk(BIOS_DEBUG, "BSP Family_Model: %08x/n", val);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid = %02x/n", bsp_apicid);	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx/n", cpu_init_detectedx);	/* Setup sysinfo defaults */	set_sysinfo_in_ram(0);	update_microcode(val);	post_code(0x33);	cpuSetAMDMSR();	post_code(0x34);	amd_ht_init(sysinfo);	post_code(0x35);	/* Setup nodes PCI space and start core 0 AP init. */	finalize_node_setup(sysinfo);	/* Setup any mainboard PCI settings etc. */	setup_mb_resource_map();	post_code(0x36);	/* wait for all the APs core0 started by finalize_node_setup. */	/* FIXME: A bunch of cores are going to start output to serial at once.	 * It would be nice to fixup prink spinlocks for ROM XIP mode.	 * I think it could be done by putting the spinlock flag in the cache	 * of the BSP located right after sysinfo.	 */	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	/* Core0 on each node is configured. Now setup any additional cores. */	printk(BIOS_DEBUG, "start_other_cores()/n");	start_other_cores();	post_code(0x37);	wait_all_other_cores_started(bsp_apicid);#endif	post_code(0x38);#if CONFIG_SET_FIDVID	msr = rdmsr(0xc0010071);	printk(BIOS_DEBUG, "/nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);	/* FIXME: The sb fid change may survive the warm reset and only	 * need to be done once.*/	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);	post_code(0x39);	if (!warm_reset_detect(0)) {			// BSP is node 0		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);	} else {		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0	}	post_code(0x3A);	/* show final fid and vid */	msr=rdmsr(0xc0010071);	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);#endif	init_timer(); // Need to use TMICT to synconize FID/VID	wants_reset = mcp55_early_setup_x();	/* Reset for HT, FIDVID, PLL and errata changes to take affect. *///.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	struct sys_info *sysinfo = &sysinfo_car;	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };	u32 bsp_apicid = 0, val;	msr_t msr;	timestamp_init(timestamp_get());	timestamp_add_now(TS_START_ROMSTAGE);	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		/* mov bsp to bus 0xff when > 8 nodes */		set_bsp_node_CHtExtNodeCfgEn();		enumerate_ht_chain();		/*enable port80 decoding and southbridge poweron init */		sb_Poweron_Init();	}	post_code(0x30);	if (bist == 0) {		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */		/* All cores run this but the BSP(node0,core0) is the only core that returns. */	}	post_code(0x32);	enable_rs780_dev8();	sb800_clk_output_48Mhz();	w83627hf_set_clksel_48(CLK_DEV);	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	printk(BIOS_DEBUG, "/n");	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	/* Load MPB */	val = cpuid_eax(1);	printk(BIOS_DEBUG, "BSP Family_Model: %08x/n", val);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid = %02x/n", bsp_apicid);	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx/n", cpu_init_detectedx);	/* Setup sysinfo defaults */	set_sysinfo_in_ram(0);	update_microcode(val);	post_code(0x33);	cpuSetAMDMSR(0);	post_code(0x34);	amd_ht_init(sysinfo);	post_code(0x35);	/* Setup nodes PCI space and start core 0 AP init. */	finalize_node_setup(sysinfo);	/* Setup any mainboard PCI settings etc. */	setup_mb_resource_map();	post_code(0x36);	/* wait for all the APs core0 started by finalize_node_setup. */	/* FIXME: A bunch of cores are going to start output to serial at once.	   It would be nice to fixup prink spinlocks for ROM XIP mode.	   I think it could be done by putting the spinlock flag in the cache	   of the BSP located right after sysinfo.	 */	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	/* Core0 on each node is configured. Now setup any additional cores. */	printk(BIOS_DEBUG, "start_other_cores()/n");	start_other_cores(bsp_apicid);	post_code(0x37);	wait_all_other_cores_started(bsp_apicid);#endif	post_code(0x38);	/* run _early_setup before soft-reset. */	rs780_early_setup();#if CONFIG_SET_FIDVID	msr = rdmsr(0xc0010071);	printk(BIOS_DEBUG, "/nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);	post_code(0x39);	if (!warm_reset_detect(0)) {			/* BSP is node 0 */		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);	} else {		init_fidvid_stage2(bsp_apicid, 0);	/* BSP is node 0 */	}//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	u32 val;	post_code(0x30);	agesawrapper_amdinitmmio();	post_code(0x31);	/* Halt if there was a built in self test failure */	post_code(0x33);	report_bist_failure(bist);	sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */	wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE);	sb7xx_51xx_disable_wideio(0);	post_code(0x34);	post_code(0x35);	console_init();	val = cpuid_eax(1);	printk(BIOS_DEBUG, "BSP Family_Model: %08x /n", val);	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx /n", cpu_init_detectedx);	post_code(0x37);	val = agesawrapper_amdinitreset();	if (val) {		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x /n", val);	} else {		printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed/n");	}	if (!cpu_init_detectedx && boot_cpu()) {		post_code(0x38);		/*		 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,		 * Disable all Pcie Bridges to work around It.		 */		sr56x0_rd890_disable_pcie_bridge();		post_code(0x39);		nb_Poweron_Init();		post_code(0x3A);		sb_Poweron_Init();	}	post_code(0x3B);	val = agesawrapper_amdinitearly();	if(val) {		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x /n", val);	} else {		printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed/n");	}	post_code(0x3C);	/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.	 * In order to access W83795G/ADG HWM using I2C protocol,	 * we select function to SDA, SCL function (or GP33, GP32 function).	 */	w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));	nb_Ht_Init();	post_code(0x3D);	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */	if (!warm_reset_detect(0)) {		print_info("...WARM RESET.../n/n/n");		distinguish_cpu_resets(0);		soft_reset();		die("After soft_reset_x - shouldn't see this message!!!/n");	}	post_code(0x40);	val = agesawrapper_amdinitpost();	if (val) {		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x /n", val);	} else {		printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed/n");	}	post_code(0x41);	val = agesawrapper_amdinitenv();	if(val) {		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x /n", val);	}	printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed/n");	post_code(0x42);	post_code(0x50);	print_debug("Disabling cache as ram ");	disable_cache_as_ram();	print_debug("done/n");	post_code(0x51);	copy_and_run();	/* We will not return,  Should never see this message and post code. */	print_debug("should not be here -/n");	post_code(0x54);}

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	struct sys_info *sysinfo = &sysinfo_car;	u32 bsp_apicid = 0, val, wants_reset;	msr_t msr;	timestamp_init(timestamp_get());	timestamp_add_now(TS_START_ROMSTAGE);	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		set_bsp_node_CHtExtNodeCfgEn();		enumerate_ht_chain();		sio_setup();	}	post_code(0x30);	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	post_code(0x32);	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	if (CONFIG_MAX_PHYSICAL_CPUS != 2)		printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!/n", CONFIG_MAX_PHYSICAL_CPUS);	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	val = cpuid_eax(1);	printk(BIOS_DEBUG, "BSP Family_Model: %08x/n", val);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid = %02x/n", bsp_apicid);	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx/n", cpu_init_detectedx);	/* Setup sysinfo defaults */	set_sysinfo_in_ram(0);	update_microcode(val);	post_code(0x33);	cpuSetAMDMSR(0);	post_code(0x34);	amd_ht_init(sysinfo);	post_code(0x35);	/* Setup nodes PCI space and start core 0 AP init. */	finalize_node_setup(sysinfo);	/* Setup any mainboard PCI settings etc. */	setup_mb_resource_map();	post_code(0x36);	/* wait for all the APs core0 started by finalize_node_setup. */	/* FIXME: A bunch of cores are going to start output to serial at once.	 * It would be nice to fix up prink spinlocks for ROM XIP mode.	 * I think it could be done by putting the spinlock flag in the cache	 * of the BSP located right after sysinfo.	 */	wait_all_core0_started();	if (IS_ENABLED(CONFIG_SET_FIDVID)) {		msr = rdmsr(0xc0010071);		printk(BIOS_DEBUG, "/nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);		post_code(0x39);		if (!warm_reset_detect(0)) {			// BSP is node 0			init_fidvid_bsp(bsp_apicid, sysinfo->nodes);		} else {			init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0		}		post_code(0x3A);		/* show final fid and vid */		msr = rdmsr(0xc0010071);		printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);	}	if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {		/* Core0 on each node is configured. Now setup any additional cores. */		printk(BIOS_DEBUG, "start_other_cores()/n");		start_other_cores(bsp_apicid);		post_code(0x37);		wait_all_other_cores_started(bsp_apicid);	}	printk(BIOS_DEBUG, "set_ck804_base_unit_id()/n");	ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID);	post_code(0x38);//.........这里部分代码省略.........

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx){	struct sys_info *sysinfo = &sysinfo_car;	u32 bsp_apicid = 0, val;	msr_t msr;	timestamp_init(timestamp_get());	timestamp_add_now(TS_START_ROMSTAGE);	if (!cpu_init_detectedx && boot_cpu()) {		/* Nothing special needs to be done to find bus 0 */		/* Allow the HT devices to be found */		/* mov bsp to bus 0xff when > 8 nodes */		set_bsp_node_CHtExtNodeCfgEn();		enumerate_ht_chain();		bcm5785_enable_lpc();		pc87417_enable_dev(RTC_DEV); /* Enable RTC */	}	post_code(0x30);	if (bist == 0)		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);	pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);	console_init();	/* Halt if there was a built in self test failure */	report_bist_failure(bist);	pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV	val = cpuid_eax(1);	printk(BIOS_DEBUG, "BSP Family_Model: %08x/n", val);	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]/n",sysinfo,sysinfo+1);	printk(BIOS_DEBUG, "bsp_apicid = %02x/n", bsp_apicid);	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx/n", cpu_init_detectedx);	/* Setup sysinfo defaults */	set_sysinfo_in_ram(0);	update_microcode(val);	post_code(0x33);	cpuSetAMDMSR(0);	post_code(0x34);	amd_ht_init(sysinfo);	post_code(0x35);	/* Setup nodes PCI space and start core 0 AP init. */	finalize_node_setup(sysinfo);	post_code(0x36);	/* wait for all the APs core0 started by finalize_node_setup. */	/* FIXME: A bunch of cores are going to start output to serial at once.	 * It would be nice to fixup prink spinlocks for ROM XIP mode.	 * I think it could be done by putting the spinlock flag in the cache	 * of the BSP located right after sysinfo.	 */	wait_all_core0_started();#if CONFIG_LOGICAL_CPUS	/* Core0 on each node is configured. Now setup any additional cores. */	printk(BIOS_DEBUG, "start_other_cores()/n");	start_other_cores(bsp_apicid);	post_code(0x37);	wait_all_other_cores_started(bsp_apicid);#endif#if CONFIG_SET_FIDVID	msr = rdmsr(0xc0010071);	printk(BIOS_DEBUG, "/nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);	/* FIXME: The sb fid change may survive the warm reset and only	 * need to be done once.*/	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);	post_code(0x39);	if (!warm_reset_detect(0)) {                    // BSP is node 0		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);	} else {		init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0	}	post_code(0x3A);	/* show final fid and vid */	msr = rdmsr(0xc0010071);	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x/n", msr.hi, msr.lo);#endif	init_timer();//.........这里部分代码省略.........