自学教程：C++ write_nic_byte函数代码示例

void rtl8225_host_usb_init(struct net_device *dev){	#if 0	write_nic_byte(dev,RFPinsSelect+1,0);	write_nic_byte(dev,GPIO,0);	write_nic_byte_E(dev,0x53,read_nic_byte_E(dev,0x53) | (1<<7));	write_nic_byte(dev,RFPinsSelect+1,4);	write_nic_byte(dev,GPIO,0x20);	write_nic_byte(dev,GP_ENABLE,0);	/* Config BB & RF */	write_nic_word(dev, RFPinsOutput, 0x80);	write_nic_word(dev, RFPinsSelect, 0x80);	write_nic_word(dev, RFPinsEnable, 0x80);	mdelay(100);	mdelay(1000);#endif}

void SwLedOn(	struct net_device *dev , PLED_8190 pLed){	u8	LedCfg;	LedCfg = read_nic_byte(dev, LEDCFG);		switch(pLed->LedPin)	{	case LED_PIN_GPIO0:		break;	case LED_PIN_LED0:		write_nic_byte(dev, LEDCFG, LedCfg&0xf0); 		break;	case LED_PIN_LED1:		write_nic_byte(dev, LEDCFG, LedCfg&0x0f); 		break;	default:		break;	}	pLed->bLedOn = true;}

void SwLedOff(struct net_device *dev, PLED_8190 pLed){	struct r8192_priv *priv = rtllib_priv(dev);	u8	LedCfg;		LedCfg = read_nic_byte(dev, LEDCFG);		switch(pLed->LedPin)	{	case LED_PIN_GPIO0:		break;	case LED_PIN_LED0:		LedCfg &= 0xf0; 		if(priv->bLedOpenDrain == true) 			write_nic_byte(dev, LEDCFG, (LedCfg|BIT1));		else			write_nic_byte(dev, LEDCFG, (LedCfg|BIT3));		break;	case LED_PIN_LED1:		LedCfg &= 0x0f; 		write_nic_byte(dev, LEDCFG, (LedCfg|BIT7));		break;	default:		break;	}	pLed->bLedOn = false;}

u32 eprom_read(struct net_device *dev, u32 addr){	struct r8180_priv *priv = ieee80211_priv(dev);	short read_cmd[]={1,1,0};	short addr_str[8];	int i;	int addr_len;	u32 ret;	ret=0;        //enable EPROM programming	write_nic_byte(dev, EPROM_CMD,		       (EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT));	force_pci_posting(dev);	udelay(EPROM_DELAY);	if (priv->epromtype==EPROM_93c56){		addr_str[7]=addr & 1;		addr_str[6]=addr & (1<<1);		addr_str[5]=addr & (1<<2);		addr_str[4]=addr & (1<<3);		addr_str[3]=addr & (1<<4);		addr_str[2]=addr & (1<<5);		addr_str[1]=addr & (1<<6);		addr_str[0]=addr & (1<<7);		addr_len=8;	}else{		addr_str[5]=addr & 1;		addr_str[4]=addr & (1<<1);		addr_str[3]=addr & (1<<2);		addr_str[2]=addr & (1<<3);		addr_str[1]=addr & (1<<4);		addr_str[0]=addr & (1<<5);		addr_len=6;	}	eprom_cs(dev, 1);	eprom_ck_cycle(dev);	eprom_send_bits_string(dev, read_cmd, 3);	eprom_send_bits_string(dev, addr_str, addr_len);	//keep chip pin D to low state while reading.	//I'm unsure if it is necessary, but anyway shouldn't hurt	eprom_w(dev, 0);	for(i=0;i<16;i++){		//eeprom needs a clk cycle between writing opcode&adr		//and reading data. (eeprom outs a dummy 0)		eprom_ck_cycle(dev);		ret |= (eprom_r(dev)<<(15-i));	}	eprom_cs(dev, 0);	eprom_ck_cycle(dev);	//disable EPROM programming	write_nic_byte(dev, EPROM_CMD,		       (EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT));	return ret;}

static void eprom_ck_cycle(struct net_device *dev){	write_nic_byte(dev, EPROM_CMD,		       (1<<EPROM_CK_SHIFT) | read_nic_byte(dev, EPROM_CMD));	udelay(EPROM_DELAY);	write_nic_byte(dev, EPROM_CMD,		       read_nic_byte(dev, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT));	udelay(EPROM_DELAY);}

void DoTxHighPower(struct net_device *dev){	struct r8180_priv *priv = ieee80211_priv(dev);	u16			HiPwrUpperTh = 0;	u16			HiPwrLowerTh = 0;	u8			RSSIHiPwrUpperTh;	u8			RSSIHiPwrLowerTh;	u8			u1bTmp;	char			OfdmTxPwrIdx, CckTxPwrIdx;	HiPwrUpperTh = priv->RegHiPwrUpperTh;	HiPwrLowerTh = priv->RegHiPwrLowerTh;	HiPwrUpperTh = HiPwrUpperTh * 10;	HiPwrLowerTh = HiPwrLowerTh * 10;	RSSIHiPwrUpperTh = priv->RegRSSIHiPwrUpperTh;	RSSIHiPwrLowerTh = priv->RegRSSIHiPwrLowerTh;		OfdmTxPwrIdx  = priv->chtxpwr_ofdm[priv->ieee80211->current_network.channel];	CckTxPwrIdx  = priv->chtxpwr[priv->ieee80211->current_network.channel];	if ((priv->UndecoratedSmoothedSS > HiPwrUpperTh) ||		(priv->bCurCCKPkt && (priv->CurCCKRSSI > RSSIHiPwrUpperTh))) {				priv->bToUpdateTxPwr = true;		u1bTmp= read_nic_byte(dev, CCK_TXAGC);				if (CckTxPwrIdx == u1bTmp) {			u1bTmp = (u1bTmp > 16) ? (u1bTmp -16): 0;  			write_nic_byte(dev, CCK_TXAGC, u1bTmp);			u1bTmp= read_nic_byte(dev, OFDM_TXAGC);			u1bTmp = (u1bTmp > 16) ? (u1bTmp -16): 0;  			write_nic_byte(dev, OFDM_TXAGC, u1bTmp);		}	} else if ((priv->UndecoratedSmoothedSS < HiPwrLowerTh) &&		(!priv->bCurCCKPkt || priv->CurCCKRSSI < RSSIHiPwrLowerTh)) {		if (priv->bToUpdateTxPwr) {			priv->bToUpdateTxPwr = false;						u1bTmp= read_nic_byte(dev, CCK_TXAGC);			if (u1bTmp < CckTxPwrIdx) {				write_nic_byte(dev, CCK_TXAGC, CckTxPwrIdx);			}			u1bTmp= read_nic_byte(dev, OFDM_TXAGC);			if (u1bTmp < OfdmTxPwrIdx) {				write_nic_byte(dev, OFDM_TXAGC, OfdmTxPwrIdx);			}		}	}}

static void fw_SetRQPN(struct net_device *dev){		write_nic_dword(dev,  RQPN, 0xffffffff);	write_nic_dword(dev,  RQPN+4, 0xffffffff);	write_nic_byte(dev,  RQPN+8, 0xff);	write_nic_byte(dev,  RQPN+0xB, 0x80);}	/* fw_SetRQPN */

static void eprom_w(struct net_device *dev, short bit){	if (bit)		write_nic_byte(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) |			       read_nic_byte(dev, EPROM_CMD));	else		write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD)			       & ~(1<<EPROM_W_SHIFT));	udelay(EPROM_DELAY);}

void eprom_w(struct net_device *dev,short bit){	if(bit)		write_nic_byte(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) | /			       read_nic_byte(dev,EPROM_CMD));	else		write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev,EPROM_CMD)/			       &~(1<<EPROM_W_SHIFT));	force_pci_posting(dev);	udelay(EPROM_DELAY);}

u32 eprom_read(struct net_device *dev, u32 addr){	struct r8192_priv *priv = rtllib_priv(dev);	short read_cmd[] = {1, 1, 0};	short addr_str[8];	int i;	int addr_len;	u32 ret;	ret = 0;	write_nic_byte(dev, EPROM_CMD,		       (EPROM_CMD_PROGRAM << EPROM_CMD_OPERATING_MODE_SHIFT));	udelay(EPROM_DELAY);	if (priv->epromtype == EEPROM_93C56) {		addr_str[7] = addr & 1;		addr_str[6] = addr & (1<<1);		addr_str[5] = addr & (1<<2);		addr_str[4] = addr & (1<<3);		addr_str[3] = addr & (1<<4);		addr_str[2] = addr & (1<<5);		addr_str[1] = addr & (1<<6);		addr_str[0] = addr & (1<<7);		addr_len = 8;	} else {		addr_str[5] = addr & 1;		addr_str[4] = addr & (1<<1);		addr_str[3] = addr & (1<<2);		addr_str[2] = addr & (1<<3);		addr_str[1] = addr & (1<<4);		addr_str[0] = addr & (1<<5);		addr_len = 6;	}	eprom_cs(dev, 1);	eprom_ck_cycle(dev);	eprom_send_bits_string(dev, read_cmd, 3);	eprom_send_bits_string(dev, addr_str, addr_len);	eprom_w(dev, 0);	for (i = 0; i < 16; i++) {		eprom_ck_cycle(dev);		ret |= (eprom_r(dev)<<(15-i));	}	eprom_cs(dev, 0);	eprom_ck_cycle(dev);	write_nic_byte(dev, EPROM_CMD,		       (EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT));	return ret;}

void eprom_cs(struct net_device *dev, short bit){	if(bit)		write_nic_byte(dev, EPROM_CMD,			       (1<<EPROM_CS_SHIFT) | /			       read_nic_byte(dev, EPROM_CMD)); //enable EPROM	else		write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD)/			       &~(1<<EPROM_CS_SHIFT)); //disable EPROM	force_pci_posting(dev);	udelay(EPROM_DELAY);}

 //just in phyvoid PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH	 Bandwidth)	//20M or 40M{	u8			eRFPath;	struct r8192_priv *priv = ieee80211_priv(dev);	//if (IS_HARDWARE_TYPE_8192S(dev))	if (1)	{#ifndef RTL92SE_FPGA_VERIFY		switch(Bandwidth)		{			case HT_CHANNEL_WIDTH_20:#ifdef FIB_MODIFICATION				write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);#endif				rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);				break;			case HT_CHANNEL_WIDTH_20_40:#ifdef FIB_MODIFICATION				write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);#endif				rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);				break;			default:				;//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X/n",Bandwidth ));				break;		}#endif	}	else	{	for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)	{		switch(Bandwidth)		{			case HT_CHANNEL_WIDTH_20:					//rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01);				break;			case HT_CHANNEL_WIDTH_20_40:					//rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00);				break;			default:				;//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X/n",Bandwidth ));				break;		}	}	}}

void EnableHWSecurityConfig8192(struct net_device *dev){	u8 SECR_value = 0x0;	struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);	struct rtllib_device* ieee = priv->rtllib; 	SECR_value = SCR_TxEncEnable | SCR_RxDecEnable;#ifdef _RTL8192_EXT_PATCH_	if ((((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->rtllib->auth_mode != 2)) 			&&(ieee->iw_mode != IW_MODE_MESH))#else		if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->rtllib->auth_mode != 2))#endif		{			SECR_value |= SCR_RxUseDK;			SECR_value |= SCR_TxUseDK;		}		else if ((ieee->iw_mode == IW_MODE_ADHOC) && (ieee->pairwise_key_type & (KEY_TYPE_CCMP | KEY_TYPE_TKIP)))		{			SECR_value |= SCR_RxUseDK;			SECR_value |= SCR_TxUseDK;		}	ieee->hwsec_active = 1;#ifdef _RTL8192_EXT_PATCH_		if ((ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE) || !hwwep )	{		ieee->hwsec_active = 0;		SECR_value &= ~SCR_RxDecEnable;		SECR_value &= ~SCR_TxUseDK;		SECR_value &= ~SCR_RxUseDK;		SECR_value &= ~SCR_TxEncEnable;	}#else	if ((ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE) || !hwwep)	{		ieee->hwsec_active = 0;		SECR_value &= ~SCR_RxDecEnable;	}#endif#ifdef RTL8192CE	write_nic_byte(dev, REG_CR+1,0x02); #endif	RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x/n", __FUNCTION__, /			ieee->hwsec_active, ieee->pairwise_key_type, SECR_value);		{		write_nic_byte(dev, SECR,  SECR_value);	}}

static void PlatformIOWrite4Byte(struct net_device *dev, u32 offset, u32 data){	if (offset == PhyAddr) {	/* For Base Band configuration. */		unsigned char	cmdByte;		unsigned long	dataBytes;		unsigned char	idx;		u8		u1bTmp;		cmdByte = (u8)(data & 0x000000ff);		dataBytes = data>>8;		/* NdisAcquireSpinLock( &(pDevice->IoSpinLock) ); */		for (idx = 0; idx < 30; idx++) {		/* Make sure command bit is clear before access it. */			u1bTmp = PlatformIORead1Byte(dev, PhyAddr);			if ((u1bTmp & BIT7) == 0)				break;			else				mdelay(10);		}		for (idx = 0; idx < 3; idx++)			PlatformIOWrite1Byte(dev, offset+1+idx, ((u8 *)&dataBytes)[idx]);		write_nic_byte(dev, offset, cmdByte);		/* NdisReleaseSpinLock( &(pDevice->IoSpinLock) ); */	} else {

bool FirmwareEnableCPU(struct net_device *dev){	bool rtStatus = true;	u8 tmpU1b, CPUStatus = 0;	u16 tmpU2b;	u32 iCheckTime = 200;	/* Enable CPU. */	tmpU1b = read_nic_byte(dev, SYS_CLKR);	/* AFE source */	write_nic_byte(dev,  SYS_CLKR, (tmpU1b|SYS_CPU_CLKSEL));	tmpU2b = read_nic_word(dev, SYS_FUNC_EN);	write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|FEN_CPUEN));	/* Poll IMEM Ready after CPU has refilled. */	do {		CPUStatus = read_nic_byte(dev, TCR);		if (CPUStatus & IMEM_RDY)			/* success */			break;		udelay(100);	} while (iCheckTime--);	if (!(CPUStatus & IMEM_RDY)) {		RT_TRACE(COMP_ERR, "%s(): failed to enable CPU", __func__);		rtStatus = false;	}	return rtStatus;}

int rtl8192E_suspend(struct pci_dev *pdev, pm_message_t state){	struct net_device *dev = pci_get_drvdata(pdev);	struct r8192_priv *priv = rtllib_priv(dev);	u32	ulRegRead;	netdev_info(dev, "============> r8192E suspend call./n");	del_timer_sync(&priv->gpio_polling_timer);	cancel_delayed_work(&priv->gpio_change_rf_wq);	priv->polling_timer_on = 0;	if (!netif_running(dev)) {		netdev_info(dev,			    "RTL819XE:UI is open out of suspend function/n");		goto out_pci_suspend;	}	if (dev->netdev_ops->ndo_stop)		dev->netdev_ops->ndo_stop(dev);	netif_device_detach(dev);	if (!priv->rtllib->bSupportRemoteWakeUp) {		MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT, true);		ulRegRead = read_nic_dword(dev, CPU_GEN);		ulRegRead |= CPU_GEN_SYSTEM_RESET;		write_nic_dword(dev, CPU_GEN, ulRegRead);	} else {		write_nic_dword(dev, WFCRC0, 0xffffffff);		write_nic_dword(dev, WFCRC1, 0xffffffff);		write_nic_dword(dev, WFCRC2, 0xffffffff);		write_nic_byte(dev, PMR, 0x5);		write_nic_byte(dev, MacBlkCtrl, 0xa);	}out_pci_suspend:	netdev_info(dev, "WOL is %s/n", priv->rtllib->bSupportRemoteWakeUp ?			    "Supported" : "Not supported");	pci_save_state(pdev);	pci_disable_device(pdev);	pci_enable_wake(pdev, pci_choose_state(pdev, state),			priv->rtllib->bSupportRemoteWakeUp ? 1 : 0);	pci_set_power_state(pdev, pci_choose_state(pdev, state));	mdelay(20);	return 0;}

void rtl8225z2_rf_set_chan(struct net_device *dev, short ch){/*	short gset = (priv->ieee80211->state == IEEE80211_LINKED &&		ieee80211_is_54g(priv->ieee80211->current_network)) ||		priv->ieee80211->iw_mode == IW_MODE_MONITOR;*/	rtl8225z2_SetTXPowerLevel(dev, ch);	RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);	//YJ,add,080828, if set channel failed, write again	if((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])	{		RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);	}	mdelay(1);	force_pci_posting(dev);	mdelay(10);//deleted by David : 2006/8/9#if 0	write_nic_byte(dev,SIFS,0x22);// SIFS: 0x22	if(gset)		write_nic_byte(dev,DIFS,20); //DIFS: 20	else		write_nic_byte(dev,DIFS,0x24); //DIFS: 36	if(priv->ieee80211->state == IEEE80211_LINKED &&		ieee80211_is_shortslot(priv->ieee80211->current_network))		write_nic_byte(dev,SLOT,0x9); //SLOT: 9	else		write_nic_byte(dev,SLOT,0x14); //SLOT: 20 (0x14)	if(gset){		write_nic_byte(dev,EIFS,91 - 20); // EIFS: 91 (0x5B)		write_nic_byte(dev,CW_VAL,0x73); //CW VALUE: 0x37		//DMESG("using G net params");	}else{		write_nic_byte(dev,EIFS,91 - 0x24); // EIFS: 91 (0x5B)		write_nic_byte(dev,CW_VAL,0xa5); //CW VALUE: 0x37		//DMESG("using B net params");	}#endif}

static void PlatformIOWrite1Byte(struct net_device *dev, u32 offset, u8 data){	write_nic_byte(dev, offset, data);	/*	 * To make sure write operation is completed,	 * 2005.11.09, by rcnjko.	 */	read_nic_byte(dev, offset);}

void writeOFDMPowerReg(	struct net_device* dev,	u8		index,	u32*		pValue	){	struct r8192_priv 	*priv = rtllib_priv(dev);	u16 RegOffset_A[6] = {	rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, 							rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, 							rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};	u16 RegOffset_B[6] = {	rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24, 							rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,							rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};	u8 i, rf, pwr_val[4];	u32 writeVal;	u16 RegOffset;	for(rf=0; rf<2; rf++)	{		writeVal = pValue[rf];		for(i=0; i<4; i++)		{			pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));			if (pwr_val[i]  > RF6052_MAX_TX_PWR)				pwr_val[i]  = RF6052_MAX_TX_PWR;		}		writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];		if(rf == 0)			RegOffset = RegOffset_A[index];		else			RegOffset = RegOffset_B[index];		PHY_SetBBReg(dev, RegOffset, bMaskDWord, writeVal);		RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x/n", RegOffset, writeVal));			if(((priv->rf_type == RF_2T2R) && 				(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||		     ((priv->rf_type != RF_2T2R) && 				(RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04))	)		{			writeVal = pwr_val[3];			if(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)				RegOffset = 0xc90;			if(RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)				RegOffset = 0xc98;			for(i=0; i<3; i++)			{				if(i!=2)					writeVal = (writeVal>8)?(writeVal-8):0;				else										writeVal = (writeVal>6)?(writeVal-6):0;				write_nic_byte(dev, (u32)(RegOffset+i), (u8)writeVal);			}		}	}}

void rtl8225_rf_set_chan(struct net_device *dev, short ch){	struct r8180_priv *priv = ieee80211_priv(dev);	short gset = (priv->ieee80211->state == IEEE80211_LINKED &&		ieee80211_is_54g(priv->ieee80211->current_network)) ||		priv->ieee80211->iw_mode == IW_MODE_MONITOR;	int eifs_addr;		if(NIC_8187 == priv->card_8187) {		eifs_addr = EIFS_8187;	} else {		eifs_addr = EIFS_8187B;	}			rtl8225_SetTXPowerLevel(dev, ch);		write_rtl8225(dev, 0x7, rtl8225_chan[ch]);		force_pci_posting(dev);	mdelay(10);		write_nic_byte(dev,SIFS,0x22);// SIFS: 0x22		if(gset)		write_nic_byte(dev,DIFS,20); //DIFS: 20 	else		write_nic_byte(dev,DIFS,0x24); //DIFS: 36 		if(priv->ieee80211->state == IEEE80211_LINKED &&		ieee80211_is_shortslot(priv->ieee80211->current_network))		write_nic_byte(dev,SLOT,0x9); //SLOT: 9			else		write_nic_byte(dev,SLOT,0x14); //SLOT: 20 (0x14)				if(gset){		write_nic_byte(dev,eifs_addr,91 - 20); // EIFS: 91 (0x5B)		write_nic_byte(dev,CW_VAL,0x73); //CW VALUE: 0x37		//DMESG("using G net params");	}else{		write_nic_byte(dev,eifs_addr,91 - 0x24); // EIFS: 91 (0x5B)		write_nic_byte(dev,CW_VAL,0xa5); //CW VALUE: 0x37		//DMESG("using B net params");	}}

void rtl8225_rf_set_chan(struct net_device *dev, short ch){	struct r8180_priv *priv = ieee80211_priv(dev);	short gset = (priv->ieee80211->state == IEEE80211_LINKED &&		ieee80211_is_54g(priv->ieee80211->current_network)) ||		priv->ieee80211->iw_mode == IW_MODE_MONITOR;	rtl8225_SetTXPowerLevel(dev, ch);	write_rtl8225(dev, 0x7, rtl8225_chan[ch]);	force_pci_posting(dev);	mdelay(10);	// A mode sifs 0x44, difs 34-14, slot 9, eifs 23, cwm 3, cwM 7, ctstoself 0x10	if(gset){		write_nic_byte(dev,SIFS,0x22);// SIFS: 0x22		write_nic_byte(dev,DIFS,0x14); //DIFS: 20		//write_nic_byte(dev,DIFS,20); //DIFS: 20	}else{		write_nic_byte(dev,SIFS,0x44);// SIFS: 0x22		write_nic_byte(dev,DIFS,50 - 14); //DIFS: 36	}	if(priv->ieee80211->state == IEEE80211_LINKED &&		ieee80211_is_shortslot(priv->ieee80211->current_network))		write_nic_byte(dev,SLOT,0x9); //SLOT: 9	else		write_nic_byte(dev,SLOT,0x14); //SLOT: 20 (0x14)	if(gset){		write_nic_byte(dev,EIFS,81);//91 - 20); // EIFS: 91 (0x5B)		write_nic_byte(dev,CW_VAL,0x73); //CW VALUE: 0x37		//DMESG("using G net params");	}else{		write_nic_byte(dev,EIFS,81); // EIFS: 91 (0x5B)		write_nic_byte(dev,CW_VAL,0xa5); //CW VALUE: 0x37		//DMESG("using B net params");	}}

static void MlmeDisassociateRequest(struct r8192_priv *priv, u8 *asSta,				    u8 asRsn){	u8 i;	RemovePeerTS(priv->ieee80211, asSta);	SendDisassociation( priv->ieee80211, asSta, asRsn );	if(memcpy(priv->ieee80211->current_network.bssid,asSta,6) == NULL)	{		//ShuChen TODO: change media status.		//ShuChen TODO: What to do when disassociate.		priv->ieee80211->state = IEEE80211_NOLINK;		for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x22;		priv->OpMode = RT_OP_MODE_NO_LINK;		{			RT_OP_MODE	OpMode = priv->OpMode;			u8 btMsr = read_nic_byte(priv, MSR);			btMsr &= 0xfc;			switch(OpMode)			{			case RT_OP_MODE_INFRASTRUCTURE:				btMsr |= MSR_LINK_MANAGED;				break;			case RT_OP_MODE_IBSS:				btMsr |= MSR_LINK_ADHOC;				// led link set separate				break;			case RT_OP_MODE_AP:				btMsr |= MSR_LINK_MASTER;				break;			default:				btMsr |= MSR_LINK_NONE;				break;			}			write_nic_byte(priv, MSR, btMsr);		}		ieee80211_disassociate(priv->ieee80211);		write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);		write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);	}}

/* * Check whether main code is download OK. If OK, turn on CPU * * CPU register locates in different page against general * register.  Switch to CPU register in the begin and switch * back before return */static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev){	unsigned long timeout;	bool rt_status = true;	u32 CPU_status = 0;	/* Check whether put code OK */	timeout = jiffies + msecs_to_jiffies(20);	while (time_before(jiffies, timeout)) {		CPU_status = read_nic_dword(dev, CPU_GEN);		if (CPU_status & CPU_GEN_PUT_CODE_OK)			break;		msleep(2);	}	if (!(CPU_status & CPU_GEN_PUT_CODE_OK)) {		RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!/n");		goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;	} else {		RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!/n");	}	/* Turn On CPU */	CPU_status = read_nic_dword(dev, CPU_GEN);	write_nic_byte(dev, CPU_GEN,		       (u8)((CPU_status | CPU_GEN_PWR_STB_CPU) & 0xff));	mdelay(1);	/* Check whether CPU boot OK */	timeout = jiffies + msecs_to_jiffies(20);	while (time_before(jiffies, timeout)) {		CPU_status = read_nic_dword(dev, CPU_GEN);		if (CPU_status & CPU_GEN_BOOT_RDY)			break;		msleep(2);	}	if (!(CPU_status & CPU_GEN_BOOT_RDY))		goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;	else		RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!/n");	return rt_status;CPUCheckMainCodeOKAndTurnOnCPU_Fail:	RT_TRACE(COMP_ERR, "ERR in %s()/n", __func__);	rt_status = FALSE;	return rt_status;}

bool SetAntenna8185(struct net_device *dev, u8 u1bAntennaIndex){	struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);	bool bAntennaSwitched = false;	switch (u1bAntennaIndex) {	case 0:				write_nic_byte(dev, ANTSEL, 0x03);				write_phy_cck(dev, 0x11, 0x9b); 		write_phy_ofdm(dev, 0x0d, 0x5c); 		bAntennaSwitched = true;		break;	case 1:				write_nic_byte(dev, ANTSEL, 0x00);				write_phy_cck(dev, 0x11, 0xbb); 		write_phy_ofdm(dev, 0x0d, 0x54); 		bAntennaSwitched = true;		break;	default:		printk("SetAntenna8185: unknown u1bAntennaIndex(%d)/n", u1bAntennaIndex);		break;	}	if(bAntennaSwitched)		priv->CurrAntennaIndex = u1bAntennaIndex;	return bAntennaSwitched;}

static void rtl8225_rf_set_chan(struct net_device *dev, short ch){	struct r8180_priv *priv = ieee80211_priv(dev);	short gset = (priv->ieee80211->state == IEEE80211_LINKED &&		ieee80211_is_54g(priv->ieee80211->current_network)) ||		priv->ieee80211->iw_mode == IW_MODE_MONITOR;	rtl8225_SetTXPowerLevel(dev, ch);	write_rtl8225(dev, 0x7, rtl8225_chan[ch]);	force_pci_posting(dev);	mdelay(10);	if (gset) {		write_nic_byte(dev, SIFS, 0x22);		write_nic_byte(dev, DIFS, 0x14);	} else {		write_nic_byte(dev, SIFS, 0x44);		write_nic_byte(dev, DIFS, 0x24);	}	if (priv->ieee80211->state == IEEE80211_LINKED &&	    ieee80211_is_shortslot(priv->ieee80211->current_network))		write_nic_byte(dev, SLOT, 0x9);	else		write_nic_byte(dev, SLOT, 0x14);	if (gset) {		write_nic_byte(dev, EIFS, 81);		write_nic_byte(dev, CW_VAL, 0x73);	} else {		write_nic_byte(dev, EIFS, 81);		write_nic_byte(dev, CW_VAL, 0xa5);	}}

//-----------------------------------------------------------------------------// Procedure:    Check whether main code is download OK. If OK, turn on CPU//// Description:   CPU register locates in different page against general register.//			    Switch to CPU register in the begin and switch back before return////// Arguments:   The pointer of the adapter//// Returns://        NDIS_STATUS_FAILURE - the following initialization process should be terminated//        NDIS_STATUS_SUCCESS - if firmware initialization process success//-----------------------------------------------------------------------------static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev){	bool		rt_status = true;	int		check_putcodeOK_time = 200000, check_bootOk_time = 200000;	u32		CPU_status = 0;	/* Check whether put code OK */	do {		read_nic_dword(dev, CPU_GEN, &CPU_status);		if (CPU_status&CPU_GEN_PUT_CODE_OK)			break;	}while(check_putcodeOK_time--);	if (!(CPU_status&CPU_GEN_PUT_CODE_OK)) {		RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!/n");		goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;	} else {		RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!/n");	}	/* Turn On CPU */	read_nic_dword(dev, CPU_GEN, &CPU_status);	write_nic_byte(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff));	mdelay(1000);	/* Check whether CPU boot OK */	do {		read_nic_dword(dev, CPU_GEN, &CPU_status);		if (CPU_status&CPU_GEN_BOOT_RDY)			break;	}while(check_bootOk_time--);	if (!(CPU_status&CPU_GEN_BOOT_RDY)) {		goto CPUCheckMainCodeOKAndTurnOnCPU_Fail;	} else {		RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!/n");	}	return rt_status;CPUCheckMainCodeOKAndTurnOnCPU_Fail:	RT_TRACE(COMP_ERR, "ERR in %s()/n", __func__);	rt_status = FALSE;	return rt_status;}

static void rtl8225_host_pci_init(struct net_device *dev){	write_nic_word(dev, RFPinsOutput, 0x480);	rtl8185_rf_pins_enable(dev);	write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO);	write_nic_byte(dev, GP_ENABLE, 0);	force_pci_posting(dev);	mdelay(200);	/* bit 6 is for RF on/off detection */	write_nic_word(dev, GP_ENABLE, 0xff & (~(1 << 6)));}