自学教程：C++ wrmsrl函数代码示例

/* * Erratum #420 Instruction-Based Sampling Engine May Generate * Interrupt that Cannot Be Cleared: * * Must clear counter mask first, then clear the enable bit. See * Revision Guide for AMD Family 10h Processors, Publication #41322. */static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,					  struct hw_perf_event *hwc, u64 config){	config &= ~perf_ibs->cnt_mask;	wrmsrl(hwc->config_base, config);	config &= ~perf_ibs->enable_mask;	wrmsrl(hwc->config_base, config);}

static void x86_amd_ssb_disable(void){	u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;	if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))		wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);	else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))		wrmsrl(MSR_AMD64_LS_CFG, msrval);}

/* Sandy Bridge uncore support */static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event){	struct hw_perf_event *hwc = &event->hw;	if (hwc->idx < UNCORE_PMC_IDX_FIXED)		wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);	else		wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);}

static void intel_pmu_lbr_reset_64(void){	int i;	for (i = 0; i < x86_pmu.lbr_nr; i++) {		wrmsrl(x86_pmu.lbr_from + i, 0);		wrmsrl(x86_pmu.lbr_to   + i, 0);	}}

static void gx_set_dclk_frequency(struct fb_info *info){	const struct gx_pll_entry *pll_table;	int pll_table_len;	int i, best_i;	long min, diff;	u64 dotpll, sys_rstpll;	int timeout = 1000;	/* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */	if (cpu_data(0).x86_mask == 1) {		pll_table = gx_pll_table_14MHz;		pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);	} else {		pll_table = gx_pll_table_48MHz;		pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);	}	/* Search the table for the closest pixclock. */	best_i = 0;	min = abs(pll_table[0].pixclock - info->var.pixclock);	for (i = 1; i < pll_table_len; i++) {		diff = abs(pll_table[i].pixclock - info->var.pixclock);		if (diff < min) {			min = diff;			best_i = i;		}	}	rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);	rdmsrl(MSR_GLCP_DOTPLL, dotpll);	/* Program new M, N and P. */	dotpll &= 0x00000000ffffffffull;	dotpll |= (u64)pll_table[best_i].dotpll_value << 32;	dotpll |= MSR_GLCP_DOTPLL_DOTRESET;	dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;	wrmsrl(MSR_GLCP_DOTPLL, dotpll);	/* Program dividers. */	sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2			 | MSR_GLCP_SYS_RSTPLL_DOTPREMULT2			 | MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );	sys_rstpll |= pll_table[best_i].sys_rstpll_bits;	wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);	/* Clear reset bit to start PLL. */	dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);	wrmsrl(MSR_GLCP_DOTPLL, dotpll);	/* Wait for LOCK bit. */	do {		rdmsrl(MSR_GLCP_DOTPLL, dotpll);	} while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));}

/* Flush the LBR registers. Caller should do get_cpu() and put_cpu().  */void flush_lbr(bool enable) {    int i;    wrmsrl(MSR_LBR_TOS, 0);    for (i = 0; i < LBR_ENTRIES; i++) {        wrmsrl(MSR_LBR_NHM_FROM + i, 0);        wrmsrl(MSR_LBR_NHM_TO   + i, 0);    }    if (enable) wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTL);    else        wrmsrl(MSR_IA32_DEBUGCTLMSR, 0);}

/* Write the LBR registers for the current CPU. */void put_lbr(struct lbr_t *lbr) {    int i;    wrmsrl(MSR_IA32_DEBUGCTLMSR, lbr->debug);    wrmsrl(MSR_LBR_SELECT,       lbr->select);    wrmsrl(MSR_LBR_TOS,          lbr->tos);    for (i = 0; i < LBR_ENTRIES; i++) {        wrmsrl(MSR_LBR_NHM_FROM + i, lbr->from[i]);        wrmsrl(MSR_LBR_NHM_TO   + i, lbr->to  [i]);    }}

static void __intel_pmu_lbr_enable(void){	u64 debugctl;	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);	if (cpuc->lbr_sel)		wrmsrl(MSR_LBR_SELECT, cpuc->lbr_sel->config);	rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);	debugctl |= (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);	wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);}

static void ppro_setup_ctrs(struct op_msrs const * const msrs){	uint64_t msr_content;	int i;	if (cpu_has_arch_perfmon) {		union cpuid10_eax eax;		eax.full = cpuid_eax(0xa);		/*		 * For Core2 (family 6, model 15), don't reset the		 * counter width:		 */		if (!(eax.split.version_id == 0 &&			current_cpu_data.x86 == 6 &&				current_cpu_data.x86_model == 15)) {			if (counter_width < eax.split.bit_width)				counter_width = eax.split.bit_width;		}	}	/* clear all counters */	for (i = 0 ; i < num_counters; ++i) {		CTRL_READ(msr_content, msrs, i);		CTRL_CLEAR(msr_content);		CTRL_WRITE(msr_content, msrs, i);	}	/* avoid a false detection of ctr overflows in NMI handler */	for (i = 0; i < num_counters; ++i)		wrmsrl(msrs->counters[i].addr, ~0x0ULL);	/* enable active counters */	for (i = 0; i < num_counters; ++i) {		if (counter_config[i].enabled) {			reset_value[i] = counter_config[i].count;			wrmsrl(msrs->counters[i].addr, -reset_value[i]);			CTRL_READ(msr_content, msrs, i);			CTRL_CLEAR(msr_content);			CTRL_SET_ENABLE(msr_content);			CTRL_SET_USR(msr_content, counter_config[i].user);			CTRL_SET_KERN(msr_content, counter_config[i].kernel);			CTRL_SET_UM(msr_content, counter_config[i].unit_mask);			CTRL_SET_EVENT(msr_content, counter_config[i].event);			CTRL_WRITE(msr_content, msrs, i);		} else {			reset_value[i] = 0;		}	}}

static inline void context_load(struct vcpu *v){    unsigned int i;    struct vpmu_struct *vpmu = vcpu_vpmu(v);    struct amd_vpmu_context *ctxt = vpmu->context;    for ( i = 0; i < num_counters; i++ )    {        wrmsrl(counters[i], ctxt->counters[i]);        wrmsrl(ctrls[i], ctxt->ctrls[i]);    }}

static int p4_check_ctrs(struct pt_regs * const regs,			 struct op_msrs const * const msrs){	unsigned long ctr, low, high, stag, real;	int i;	stag = get_stagger();	for (i = 0; i < num_counters; ++i) {		if (!reset_value[i])			continue;		/*		 * there is some eccentricity in the hardware which		 * requires that we perform 2 extra corrections:		 *		 * - check both the CCCR:OVF flag for overflow and the		 *   counter high bit for un-flagged overflows.		 *		 * - write the counter back twice to ensure it gets		 *   updated properly.		 *		 * the former seems to be related to extra NMIs happening		 * during the current NMI; the latter is reported as errata		 * N15 in intel doc 249199-029, pentium 4 specification		 * update, though their suggested work-around does not		 * appear to solve the problem.		 */		real = VIRT_CTR(stag, i);		rdmsr(p4_counters[real].cccr_address, low, high);		rdmsr(p4_counters[real].counter_address, ctr, high);		if (CCCR_OVF_P(low) || !(ctr & OP_CTR_OVERFLOW)) {			oprofile_add_sample(regs, i);			wrmsrl(p4_counters[real].counter_address,			       -(u64)reset_value[i]);			CCCR_CLEAR_OVF(low);			wrmsr(p4_counters[real].cccr_address, low, high);			wrmsrl(p4_counters[real].counter_address,			       -(u64)reset_value[i]);		}	}	/* P4 quirk: you have to re-unmask the apic vector */	apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);	/* See op_model_ppro.c */	return 1;}

void __devinit early_intel_workaround(struct cpuinfo_x86 *c){	if (c->x86_vendor != X86_VENDOR_INTEL)		return;	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */	if (c->x86 == 15 && c->x86_cache_alignment == 64)		c->x86_cache_alignment = 128;	/* Unmask CPUID levels if masked: */	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {		u64 misc_enable;		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);			c->cpuid_level = cpuid_eax(0);			if (opt_cpu_info || c == &boot_cpu_data)				printk(KERN_INFO "revised cpuid level: %d/n",				       c->cpuid_level);		}	}	/* CPUID workaround for Intel 0F33/0F34 CPU */	if (boot_cpu_data.x86 == 0xF && boot_cpu_data.x86_model == 3 &&	    (boot_cpu_data.x86_mask == 3 || boot_cpu_data.x86_mask == 4))		paddr_bits = 36;}

static int apply_microcode_amd(int cpu){	u32 rev, dummy;	int cpu_num = raw_smp_processor_id();	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;	struct microcode_amd *mc_amd = uci->mc;	/* We should bind the task to the CPU */	BUG_ON(cpu_num != cpu);	if (mc_amd == NULL)		return 0;	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);	/* get patch id after patching */	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);	/* check current patch id and patch's id for match */	if (rev != mc_amd->hdr.patch_id) {		printk(KERN_ERR "microcode: CPU%d: update failed "		       "(for patch_level=0x%x)/n", cpu, mc_amd->hdr.patch_id);		return -1;	}	printk(KERN_INFO "microcode: CPU%d: updated (new patch_level=0x%x)/n",	       cpu, rev);	uci->cpu_sig.rev = rev;	return 0;}

static int boost_set_msr(bool enable){	u32 msr_addr;	u64 msr_mask, val;	switch (boot_cpu_data.x86_vendor) {	case X86_VENDOR_INTEL:		msr_addr = MSR_IA32_MISC_ENABLE;		msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE;		break;	case X86_VENDOR_AMD:		msr_addr = MSR_K7_HWCR;		msr_mask = MSR_K7_HWCR_CPB_DIS;		break;	default:		return -EINVAL;	}	rdmsrl(msr_addr, val);	if (enable)		val &= ~msr_mask;	else		val |= msr_mask;	wrmsrl(msr_addr, val);	return 0;}

void stopCounter(int counter){	unsigned long long high_low;				unsigned pmc, setpmc;				switch(counter){					case 0: pmc = IA32_PMC0;							setpmc = IA32_PERFEVTSEL0;							break;					case 1: pmc = IA32_PMC1;							setpmc = IA32_PERFEVTSEL1;							break;					case 2: pmc = IA32_PMC2;							setpmc = IA32_PERFEVTSEL2;							break;					case 3: pmc = IA32_PMC3;							setpmc = IA32_PERFEVTSEL3;							break;					default: printk(KERN_INFO "Unkown counter #%d", counter);					return;						break;				}				rdmsrl(setpmc, high_low);				if((high_low>>22 & 0x1ULL) == 0x1ULL){ //vol. 3 30-4,30-10						printk(KERN_INFO "stopping counter/n");									high_low &=~(0x1ULL<<22);					wrmsrl(setpmc, high_low);					printk(KERN_INFO "stopped tracking/n");				} else{

static int amd_vpmu_save(struct vcpu *v){    struct vpmu_struct *vpmu = vcpu_vpmu(v);    struct amd_vpmu_context *ctx = vpmu->context;    unsigned int i;    /*     * Stop the counters. If we came here via vpmu_save_force (i.e.     * when VPMU_CONTEXT_SAVE is set) counters are already stopped.     */    if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_SAVE) )    {        vpmu_set(vpmu, VPMU_FROZEN);        for ( i = 0; i < num_counters; i++ )            wrmsrl(ctrls[i], 0);        return 0;    }    if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_LOADED) )        return 0;    context_save(v);    if ( !vpmu_is_set(vpmu, VPMU_RUNNING) && ctx->msr_bitmap_set )        amd_vpmu_unset_msr_bitmap(v);    return 1;}

static void init_cpu_pda(unsigned int cpu){#if defined(__x86_64__)    unsigned long *irqstack;    irqstack = (unsigned long *)alloc_pages(STACK_SIZE_PAGE_ORDER);    if (cpu == 0) {	asm volatile ("movl %0,%%fs ; movl %0,%%gs"::"r" (0));	wrmsrl(0xc0000101, &(percpu[cpu]));	/* 0xc0000101 is MSR_GS_BASE */    }    per_cpu(cpu, irqcount) = -1;    per_cpu(cpu, irqstackptr) = (unsigned long)irqstack + STACK_SIZE;    per_cpu(cpu, idle_thread) = create_idle_thread(cpu);    /*     * Save pointer to idle thread onto the irq stack. This is used by     * current macro (and related, smp_processor_id)     */    BUG_ON(!per_cpu(cpu, idle_thread));    irqstack[0] = (unsigned long)per_cpu(cpu, idle_thread);#endif    per_cpu(cpu, current_thread) = per_cpu(cpu, idle_thread);    per_cpu(cpu, cpunumber) = cpu;    per_cpu(cpu, upcall_count) = 0;    memset(&per_cpu(cpu, shadow_time), 0, sizeof(struct shadow_time_info));    per_cpu(cpu, ipi_port) = evtchn_alloc_ipi(ipi_handler, cpu, NULL);    per_cpu(cpu, cpu_state) = cpu == 0 ? CPU_UP : CPU_SLEEPING;    per_cpu(cpu, db_support) = NULL;}

void tsc_verify_tsc_adjust(bool resume){	struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust);	s64 curval;	if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))		return;	/* Rate limit the MSR check */	if (!resume && time_before(jiffies, adj->nextcheck))		return;	adj->nextcheck = jiffies + HZ;	rdmsrl(MSR_IA32_TSC_ADJUST, curval);	if (adj->adjusted == curval)		return;	/* Restore the original value */	wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted);	if (!adj->warned || resume) {		pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring/n",			smp_processor_id(), adj->adjusted, curval);		adj->warned = true;	}}

static int setup_intel_arch_watchdog(void){	unsigned int evntsel;	unsigned ebx;	/*	 * Check whether the Architectural PerfMon supports	 * Unhalted Core Cycles Event or not.	 * NOTE: Corresponding bit = 0 in ebp indicates event present.	 */	ebx = cpuid_ebx(10);	if ((ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))		return 0;	nmi_perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;	clear_msr_range(MSR_ARCH_PERFMON_EVENTSEL0, 2);	clear_msr_range(MSR_ARCH_PERFMON_PERFCTR0, 2);	evntsel = ARCH_PERFMON_EVENTSEL_INT		| ARCH_PERFMON_EVENTSEL_OS		| ARCH_PERFMON_EVENTSEL_USR		| ARCH_PERFMON_NMI_EVENT_SEL		| ARCH_PERFMON_NMI_EVENT_UMASK;	wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);	wrmsrl(MSR_ARCH_PERFMON_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));	apic_write(APIC_LVTPC, APIC_DM_NMI);	evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;	wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);	return 1;}

static void snb_uncore_msr_init_box(struct intel_uncore_box *box){	if (box->pmu->pmu_idx == 0) {		wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,			SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);	}}

static enum ssb_mitigation __init __ssb_select_mitigation(void){	enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;	enum ssb_mitigation_cmd cmd;	if (!boot_cpu_has(X86_FEATURE_SSBD))		return mode;	cmd = ssb_parse_cmdline();	if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&	    (cmd == SPEC_STORE_BYPASS_CMD_NONE ||	     cmd == SPEC_STORE_BYPASS_CMD_AUTO))		return mode;	switch (cmd) {	case SPEC_STORE_BYPASS_CMD_AUTO:	case SPEC_STORE_BYPASS_CMD_SECCOMP:		/*		 * Choose prctl+seccomp as the default mode if seccomp is		 * enabled.		 */		if (IS_ENABLED(CONFIG_SECCOMP))			mode = SPEC_STORE_BYPASS_SECCOMP;		else			mode = SPEC_STORE_BYPASS_PRCTL;		break;	case SPEC_STORE_BYPASS_CMD_ON:		mode = SPEC_STORE_BYPASS_DISABLE;		break;	case SPEC_STORE_BYPASS_CMD_PRCTL:		mode = SPEC_STORE_BYPASS_PRCTL;		break;	case SPEC_STORE_BYPASS_CMD_NONE:		break;	}	/*	 * We have three CPU feature flags that are in play here:	 *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.	 *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass	 *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation	 */	if (mode == SPEC_STORE_BYPASS_DISABLE) {		setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);		/*		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may		 * use a completely different MSR and bit dependent on family.		 */		if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&		    !static_cpu_has(X86_FEATURE_AMD_SSBD)) {			x86_amd_ssb_disable();		} else {			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;			x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;			wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);		}	}	return mode;}

static int ppro_check_ctrs(struct pt_regs * const regs,			   struct op_msrs const * const msrs){	u64 val;	int i;	for (i = 0 ; i < num_counters; ++i) {		if (!reset_value[i])			continue;		rdmsrl(msrs->counters[i].addr, val);		if (CTR_OVERFLOWED(val)) {			oprofile_add_sample(regs, i);			wrmsrl(msrs->counters[i].addr, -reset_value[i]);		}	}	/* Only P6 based Pentium M need to re-unmask the apic vector but it	 * doesn't hurt other P6 variant */	apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);	/* We can't work out if we really handled an interrupt. We	 * might have caught a *second* counter just after overflowing	 * the interrupt for this counter then arrives	 * and we don't find a counter that's overflowed, so we	 * would return 0 and get dazed + confused. Instead we always	 * assume we found an overflow. This sucks.	 */	return 1;}

static void nmi_cpu_restore_registers(struct op_msrs *msrs){	struct op_msr *counters = msrs->counters;	struct op_msr *controls = msrs->controls;	unsigned int i;	for (i = 0; i < model->num_controls; ++i) {		if (controls[i].addr)			wrmsrl(controls[i].addr, controls[i].saved);	}	for (i = 0; i < model->num_counters; ++i) {		if (counters[i].addr)			wrmsrl(counters[i].addr, counters[i].saved);	}}

static void nmi_restore_registers(struct op_msrs * msrs){	unsigned int const nr_ctrs = model->num_counters;	unsigned int const nr_ctrls = model->num_controls;	struct op_msr * counters = msrs->counters;	struct op_msr * controls = msrs->controls;	unsigned int i;	for (i = 0; i < nr_ctrls; ++i) {		wrmsrl(controls[i].addr, controls[i].value);	}	for (i = 0; i < nr_ctrs; ++i) {		wrmsrl(counters[i].addr, counters[i].value);	}}

static void early_init_intel(struct cpuinfo_x86 *c){	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */	if (c->x86 == 15 && c->x86_cache_alignment == 64)		c->x86_cache_alignment = 128;	/* Unmask CPUID levels and NX if masked: */	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {		u64 misc_enable, disable;		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);		disable = misc_enable & (MSR_IA32_MISC_ENABLE_LIMIT_CPUID |					 MSR_IA32_MISC_ENABLE_XD_DISABLE);		if (disable) {			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);			bootsym(trampoline_misc_enable_off) |= disable;		}		if (disable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)			printk(KERN_INFO "revised cpuid level: %d/n",			       cpuid_eax(0));		if (disable & MSR_IA32_MISC_ENABLE_XD_DISABLE) {			write_efer(read_efer() | EFER_NX);			printk(KERN_INFO			       "re-enabled NX (Execute Disable) protection/n");		}	}	/* CPUID workaround for Intel 0F33/0F34 CPU */	if (boot_cpu_data.x86 == 0xF && boot_cpu_data.x86_model == 3 &&	    (boot_cpu_data.x86_mask == 3 || boot_cpu_data.x86_mask == 4))		paddr_bits = 36;}

static void intel_pmu_lbr_reset_32(void){	int i;	for (i = 0; i < x86_pmu.lbr_nr; i++)		wrmsrl(x86_pmu.lbr_from + i, 0);}

void disable_local_APIC(void){    clear_local_APIC();    /*     * Disable APIC (implies clearing of registers     * for 82489DX!).     */    apic_write_around(APIC_SPIV,        apic_read(APIC_SPIV) & ~APIC_SPIV_APIC_ENABLED);    if (enabled_via_apicbase) {        uint64_t msr_content;        rdmsrl(MSR_IA32_APICBASE, msr_content);        wrmsrl(MSR_IA32_APICBASE, msr_content &               ~(MSR_IA32_APICBASE_ENABLE|MSR_IA32_APICBASE_EXTD));    }    if ( kexecing && (current_local_apic_mode() != apic_boot_mode) )    {        uint64_t msr_content;        rdmsrl(MSR_IA32_APICBASE, msr_content);        msr_content &= ~(MSR_IA32_APICBASE_ENABLE|MSR_IA32_APICBASE_EXTD);        wrmsrl(MSR_IA32_APICBASE, msr_content);        switch ( apic_boot_mode )        {        case APIC_MODE_DISABLED:            break; /* Nothing to do - we did this above */        case APIC_MODE_XAPIC:            msr_content |= MSR_IA32_APICBASE_ENABLE;            wrmsrl(MSR_IA32_APICBASE, msr_content);            break;        case APIC_MODE_X2APIC:            msr_content |= MSR_IA32_APICBASE_ENABLE;            wrmsrl(MSR_IA32_APICBASE, msr_content);            msr_content |= MSR_IA32_APICBASE_EXTD;            wrmsrl(MSR_IA32_APICBASE, msr_content);            break;        default:            printk("Default case when reverting #%d lapic to boot state/n",                   smp_processor_id());            break;        }    }}

static void __cpuinit early_init_intel(struct cpuinfo_x86 *c){	/* Unmask CPUID levels if masked: */	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {		u64 misc_enable;		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);			c->cpuid_level = cpuid_eax(0);		}	}	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||		(c->x86 == 0x6 && c->x86_model >= 0x0e))		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);#ifdef CONFIG_X86_64	set_cpu_cap(c, X86_FEATURE_SYSENTER32);#else	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */	if (c->x86 == 15 && c->x86_cache_alignment == 64)		c->x86_cache_alignment = 128;#endif	/* CPUID workaround for 0F33/0F34 CPU */	if (c->x86 == 0xF && c->x86_model == 0x3	    && (c->x86_mask == 0x3 || c->x86_mask == 0x4))		c->x86_phys_bits = 36;	/*	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate	 * with P/T states and does not stop in deep C-states.	 *	 * It is also reliable across cores and sockets. (but not across	 * cabinets - we turn it off in that case explicitly.)	 */	if (c->x86_power & (1 << 8)) {		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);		sched_clock_stable = 1;	}	/*	 * There is a known erratum on Pentium III and Core Solo	 * and Core Duo CPUs.	 * " Page with PAT set to WC while associated MTRR is UC	 *   may consolidate to UC "	 * Because of this erratum, it is better to stick with	 * setting WC in MTRR rather than using PAT on these CPUs.	 *	 * Enable PAT WC only on P4, Core 2 or later CPUs.	 */	if (c->x86 == 6 && c->x86_model < 15)		clear_cpu_cap(c, X86_FEATURE_PAT);}

static void __intel_pmu_lbr_disable(void){	u64 debugctl;	rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);	debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);	wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);}