自学教程：C++ xTaskIncrementTick函数代码示例

	void TIM2_IRQHandler( void )	{		/* Reset the timer counter to avioid overflow. */		TIM2->OC1R += s_nPulseLength;				/* Increment the tick counter. */		if( xTaskIncrementTick() != pdFALSE )		{			/* Select a new task to run. */			vTaskSwitchContext();		}				/* Clear the interrupt in the watchdog. */		TIM2->SR &= ~TIM_FLAG_OC1;	}

void __attribute__ ((interrupt)) __cs3_isr_interrupt_119( void ){unsigned portLONG ulSavedInterruptMask;	/* Clear the PIT0 interrupt. */	MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;	/* Increment the RTOS tick. */	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();		if( xTaskIncrementTick() != pdFALSE )		{			taskYIELD();		}	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );}

void xPortSysTickHandler( void ){uint32_t ulPreviousMask;	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();	{		/* Increment the RTOS tick. */		if( xTaskIncrementTick() != pdFALSE )		{			/* Pend a context switch. */			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;		}	}	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );}

	void vNonPreemptiveTick( void )	{		uint32_t ulDummy;		/* Increment the tick count - which may wake some tasks but as the		preemptive scheduler is not being used any woken task is not given		processor time no matter what its priority. */		xTaskIncrementTick();		/* Clear the PIT interrupt. */		ulDummy = AT91C_BASE_PITC->PITC_PIVR;		/* End the interrupt in the AIC. */		AT91C_BASE_AIC->AIC_EOICR = ulDummy;	}

void xPortSysTickHandler( void ){unsigned long ulDummy;	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();	{		/* Increment the RTOS tick. */		if( xTaskIncrementTick() != pdFALSE )		{			/* Pend a context switch. */			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;		}	}	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );}

__interrupt void vTickISR( void ){	/* Re-enable interrupts. */	__enable_interrupt();	/* Increment the tick, and perform any processing the new tick value	necessitates. */	__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );	{		if( xTaskIncrementTick() != pdFALSE )		{			taskYIELD();		}	}	__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );}

void vTickISR( void ){	/* Re-enabled interrupts. */	__asm volatile( "SETPSW	I" );		/* Increment the tick, and perform any processing the new tick value	necessitates.  Ensure IPL is at the max syscall value first. */	portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();	{		if( xTaskIncrementTick() != pdFALSE )		{			taskYIELD();		}	}	portENABLE_INTERRUPTS_FROM_KERNEL_ISR();}

void xPortSysTickHandler( void ){    nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_TICK);#if configUSE_TICKLESS_IDLE == 1    nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);#endif    uint32_t isrstate = portSET_INTERRUPT_MASK_FROM_ISR();    /* Increment the RTOS tick. */    if ( xTaskIncrementTick() != pdFALSE )    {        /* A context switch is required.  Context switching is performed in        the PendSV interrupt.  Pend the PendSV interrupt. */        SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;        __SEV();    }    portCLEAR_INTERRUPT_MASK_FROM_ISR( isrstate );}

void xPortSysTickHandler( void ){    /* The SysTick runs at the lowest interrupt priority, so when this interrupt    executes all interrupts must be unmasked.  There is therefore no need to    save and then restore the interrupt mask value as its value is already    known. */    ( void ) portSET_INTERRUPT_MASK_FROM_ISR();    {        /* Increment the RTOS tick. */        if( xTaskIncrementTick() != pdFALSE ) {            /* A context switch is required.  Context switching is performed in            the PendSV interrupt.  Pend the PendSV interrupt. */            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;        }    }    portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );}

void vPortIncrementTick( void ){    unsigned portBASE_TYPE uxSavedStatus;    uxSavedStatus = uxPortSetInterruptMaskFromISR();    {        if( xTaskIncrementTick() != pdFALSE )        {            /* Pend a context switch. */            _CP0_BIS_CAUSE( portCORE_SW_0 );        }    }    vPortClearInterruptMaskFromISR( uxSavedStatus );    /* Clear timer 1 interrupt. */    IFS0CLR = _IFS0_T1IF_MASK;}

	void vPreemptiveTick( void )	{		/* Save the context of the current task. */		portSAVE_CONTEXT();		/* Increment the tick count - this may wake a task. */		if( xTaskIncrementTick() != pdFALSE )		{			/* Find the highest priority task that is ready to run. */			vTaskSwitchContext();		}		/* End the interrupt in the AIC. */		AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;		portRESTORE_CONTEXT();	}

void interrupt VectorNumber_Vrtc vPortTickISR( void ){uint32_t ulSavedInterruptMask;	/* Clear the interrupt. */	RTCSC |= RTCSC_RTIF_MASK;	/* Increment the RTOS tick. */	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();	{		if( xTaskIncrementTick() != pdFALSE )		{			taskYIELD();		}	}	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );}

void vPortYieldFromTick( void ){	portSAVE_CONTEXT();	if (--ticksRemainingInSec == 0)	{		system_tick();		ticksRemainingInSec = portTickRateHz;	}	if( xTaskIncrementTick() != pdFALSE )	{		vTaskSwitchContext();	}	portRESTORE_CONTEXT();	asm volatile ( "ret" );}

void vPortTickHandler(void) {  /* this is how we get here:    RTOSTICKLDD1_Interrupt:    push {r4, lr}    ...                                       RTOSTICKLDD1_OnCounterRestart    bl RTOSTICKLDD1_OnCounterRestart     ->   push {r4,lr}    pop {r4, lr}                              mov r4,r0                                              bl vPortTickHandler                                              pop {r4,pc}  */#if configUSE_TICKLESS_IDLE == 1  TICK_INTERRUPT_FLAG_SET();#endif  portSET_INTERRUPT_MASK();   /* disable interrupts */  if (xTaskIncrementTick()!=pdFALSE) { /* increment tick count */    taskYIELD();  }  portCLEAR_INTERRUPT_MASK(); /* enable interrupts again */}

void xPortSysTickHandler( void ){	/* The SysTick runs at the lowest interrupt priority, so when this interrupt	executes all interrupts must be unmasked.  There is therefore no need to	save and then restore the interrupt mask value as its value is already	known - therefore the slightly faster vPortRaiseBASEPRI() function is used	in place of portSET_INTERRUPT_MASK_FROM_ISR(). */	vPortRaiseBASEPRI();	{		/* Increment the RTOS tick. */		if( xTaskIncrementTick() != pdFALSE )		{			/* A context switch is required.  Context switching is performed in			the PendSV interrupt.  Pend the PendSV interrupt. */			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;		}	}	vPortClearBASEPRIFromISR();}

static __arm void vPortTickISR( void ){    volatile unsigned long ulDummy;    /* Increment the tick count - which may wake some tasks but as the    preemptive scheduler is not being used any woken task is not given    processor time no matter what its priority. */    if( xTaskIncrementTick() != pdFALSE ) {        vTaskSwitchContext();    }    /* Clear the PIT interrupt. */    ulDummy = AT91C_BASE_PITC->PITC_PIVR;    /* To remove compiler warning. */    ( void ) ulDummy;    /* The AIC is cleared in the asm wrapper, outside of this function. */}

void vPortIncrementTick( void ){UBaseType_t uxSavedStatus;	uxSavedStatus = uxPortSetInterruptMaskFromISR();	{		if( xTaskIncrementTick() != pdFALSE )		{			/* Pend a context switch. */			_CP0_BIS_CAUSE( portCORE_SW_0 );		}	}	vPortClearInterruptMaskFromISR( uxSavedStatus );	/* Look for the ISR stack getting near or past its limit. */	portCHECK_ISR_STACK();	/* Clear timer interrupt. */	configCLEAR_TICK_TIMER_INTERRUPT();}

void FreeRTOS_Tick_Handler( void ){	/* Set interrupt mask before altering scheduler structures.   The tick	handler runs at the lowest priority, so interrupts cannot already be masked,	so there is no need to save and restore the current mask value. */	__disable_irq();	portICCPMR_PRIORITY_MASK_REGISTER = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );	__asm(	"DSB		/n"			"ISB		/n" );	__enable_irq();	/* Increment the RTOS tick. */	if( xTaskIncrementTick() != pdFALSE )	{		ulPortYieldRequired = pdTRUE;	}	/* Ensure all interrupt priorities are active again. */	portCLEAR_INTERRUPT_MASK();}

void xPortSysTickHandler( void ){    nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_TICK);#if configUSE_TICKLESS_IDLE == 1    nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);#endif    /* The SysTick runs at the lowest interrupt priority, so when this interrupt    executes all interrupts must be unmasked.  There is therefore no need to    save and then restore the interrupt mask value as its value is already    known. */    ( void ) portSET_INTERRUPT_MASK_FROM_ISR();    do{#if configUSE_TICKLESS_IDLE == 1        TickType_t diff;        TickType_t actualTicks = xTaskGetTickCountFromISR();        TickType_t hwTicks     = nrf_rtc_counter_get(portNRF_RTC_REG);        diff = (hwTicks - actualTicks) & portNRF_RTC_MAXTICKS;        if(diff <= 0)        {            break;        }        if(diff > 2) // Correct internat ticks        {            vTaskStepTick(diff - 1);        }#endif        /* Increment the RTOS tick. */        if( xTaskIncrementTick() != pdFALSE )        {            /* A context switch is required.  Context switching is performed in            the PendSV interrupt.  Pend the PendSV interrupt. */            SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;            __SEV();        }    }while(0);    portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );}

/* * Handler for the timer interrupt.  This is the handler that the application * defined callback function vApplicationSetupTimerInterrupt() should install. */void vPortTickISR( void *pvUnused ){extern void vApplicationClearTimerInterrupt( void );	/* Ensure the unused parameter does not generate a compiler warning. */	( void ) pvUnused;	/* This port uses an application defined callback function to clear the tick	interrupt because the kernel will run on lots of different MicroBlaze and	FPGA configurations - not all of which will have the same timer peripherals	defined or available.  An example definition of	vApplicationClearTimerInterrupt() is provided in the official demo	application that accompanies this port. */	vApplicationClearTimerInterrupt();	/* Increment the RTOS tick - this might cause a task to unblock. */	if( xTaskIncrementTick() != pdFALSE )	{		/* Force vTaskSwitchContext() to be called as the interrupt exits. */		ulTaskSwitchRequested = 1;	}}

/* The preemptive scheduler is defined as "naked" as the full context is savedon entry as part of the context switch. */__attribute__((__naked__)) static void vTick( void ){	/* Save the context of the interrupted task. */	portSAVE_CONTEXT_OS_INT();	#if( configTICK_USE_TC==1 )		/* Clear the interrupt flag. */		prvClearTcInt();	#else		/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)		clock cycles from now. */		prvScheduleNextTick();	#endif	/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS	calls in a critical section . */	portENTER_CRITICAL();		xTaskIncrementTick();	portEXIT_CRITICAL();	/* Restore the context of the "elected task". */	portRESTORE_CONTEXT_OS_INT();}

static void ituIrqHandler(void *context){	a++;	ioWrite8(ITU_USB_BUSY, a & 1);	static uint8_t pending;	pending = ioRead8(ITU_IRQ_ACTIVE);	ioWrite8(ITU_IRQ_CLEAR, pending);	BaseType_t do_switch = pdFALSE;/*	if (pending & 0x20) {		RmiiRxInterruptHandler();		do_switch = pdTRUE;	}	if (pending & 0x10) {		do_switch = command_interface_irq();	}	if (pending & 0x08) {		do_switch |= tape_recorder_irq();	}	if (pending & 0x04) {		do_switch |= usb_irq();	}	if (pending & 0x02) {		do_switch |= uart_irq();	}*/	if (pending & 0x01) {		do_switch |= xTaskIncrementTick();	}	if (do_switch != pdFALSE) {		vTaskSwitchContext();	}}

void vTaskISRHandler( void ){static uint8_t pending;	PROFILER_SUB = 1;	/* Which interrupts are pending? */	pending = ioRead8(ITU_IRQ_ACTIVE);	ioWrite8(ITU_IRQ_CLEAR, pending);	//const uint8_t hex[] = "0123456789ABCDEF";	//ioWrite8(UART_DATA, hex[pending >> 4]);	//ioWrite8(UART_DATA, hex[pending & 0x0F]);	//ioWrite8(UART_DATA, '|');	BaseType_t do_switch = pdFALSE;	if (pending & 0x10) {		do_switch = command_interface_irq();	}	if (pending & 0x08) {		do_switch |= tape_recorder_irq();	}	if (pending & 0x04) {		do_switch |= usb_irq();	}	if (pending & 0x02) {		do_switch |= uart_irq();	}	if (pending & 0x01) {		do_switch |= xTaskIncrementTick();	}	if (do_switch != pdFALSE) {		vTaskSwitchContext();	}}

/** * @brief	Tick interrupt handler routine * @return	Nothing * @note	This function handles the tick interrupts that are generated by RITIMER. */void RIT_IRQHandler(void){	unsigned long ulPreviousMask;	/* TODO: check if WWDT interrupt and redirect */	Chip_RIT_ClearInt(LPC_RITIMER);	Chip_RIT_SetCOMPVAL(LPC_RITIMER, Chip_RIT_GetCounter(LPC_RITIMER) + reload_val);/* Reload value */#if configUSE_PREEMPTION == 1	/* If using preemption, also force a context switch. */	*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;#endif	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();	{		/* Increment the RTOS tick. */		if( xTaskIncrementTick() != pdFALSE )		{			/* Pend a context switch. */			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;		}	}	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );}

void prvTickISR( void ){	/* Increment the tick, and perform any processing the new tick value	necessitates. */	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );	{		if( xTaskIncrementTick() != pdFALSE )		{			taskYIELD();		}	}	set_ipl( configKERNEL_INTERRUPT_PRIORITY );	#if configUSE_TICKLESS_IDLE == 1	{		/* The CPU woke because of a tick. */		ulTickFlag = pdTRUE;		/* If this is the first tick since exiting tickless mode then the CMT		compare match value needs resetting. */		CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;	}	#endif}

static void prvSystemTickHandler( int iArg ){uint32_t ulSavedInterruptMask;uint32_t *pxUpperCSA = NULL;uint32_t xUpperCSA = 0UL;extern volatile uint32_t *pxCurrentTCB;int32_t lYieldRequired;	/* Just to avoid compiler warnings about unused parameters. */	( void ) iArg;	/* Clear the interrupt source. */	STM_ISRR.reg = 1UL;	/* Reload the Compare Match register for X ticks into the future.	If critical section or interrupt nesting budgets are exceeded, then	it is possible that the calculated next compare match value is in the	past.  If this occurs (unlikely), it is possible that the resulting	time slippage will exceed a single tick period.  Any adverse effect of	this is time bounded by the fact that only the first n bits of the 56 bit	STM timer are being used for a compare match, so another compare match	will occur after an overflow in just those n bits (not the entire 56 bits).	As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,	a missed tick could result in the next tick interrupt occurring within a	time that is 1.7 times the desired period.  The fact that this is greater	than a single tick period is an effect of using a timer that cannot be	automatically reset, in hardware, by the occurrence of a tick interrupt.	Changing the tick source to a timer that has an automatic reset on compare	match (such as a GPTA timer) will reduce the maximum possible additional	period to exactly 1 times the desired period. */	STM_CMP0.reg += ulCompareMatchValue;	/* Kernel API calls require Critical Sections. */	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();	{		/* Increment the Tick. */		lYieldRequired = xTaskIncrementTick();	}	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );	if( lYieldRequired != pdFALSE )	{		/* Save the context of a task.		The upper context is automatically saved when entering a trap or interrupt.		Need to save the lower context as well and copy the PCXI CSA ID into		pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the		TCB of a task.		Call vTaskSwitchContext to select the next task, note that this changes the		value of pxCurrentTCB so that it needs to be reloaded.		Call vPortSetMPURegisterSetOne to change the MPU mapping for the task		that has just been switched in.		Load the context of the task.		Need to restore the lower context by loading the CSA from		pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).		In the Interrupt handler post-amble, RSLCX will restore the lower context		of the task. RFE will restore the upper context of the task, jump to the		return address and restore the previous state of interrupts being		enabled/disabled. */		_disable();		_dsync();		xUpperCSA = _mfcr( $PCXI );		pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );		*pxCurrentTCB = pxUpperCSA[ 0 ];		vTaskSwitchContext();		pxUpperCSA[ 0 ] = *pxCurrentTCB;		CPU_SRC0.bits.SETR = 0;		_isync();	}}

	interrupt (TIMERA0_VECTOR) prvTickISR( void )	{		xTaskIncrementTick();	}

    void TIMER1_COMPA_vect( void )	{		xTaskIncrementTick();	}

	void SIG_OUTPUT_COMPARE1A( void )	{		xTaskIncrementTick();	}

	void vNonPreemptiveTick( void )	{			xTaskIncrementTick();		T0IR = 2;		VICVectAddr = portCLEAR_VIC_INTERRUPT;	}