自学教程：C++ xhci_warn函数代码示例

/* Drop an endpoint from a new bandwidth configuration for this device. * Only one call to this function is allowed per endpoint before * check_bandwidth() or reset_bandwidth() must be called. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will * add the endpoint to the schedule with possibly new parameters denoted by a * different endpoint descriptor in usb_host_endpoint. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is * not allowed. * * The USB core will not allow URBs to be queued to an endpoint that is being * disabled, so there's no need for mutual exclusion to protect * the xhci->devs[slot_id] structure. */int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,		struct usb_host_endpoint *ep){	struct xhci_hcd *xhci;	struct xhci_container_ctx *in_ctx, *out_ctx;	struct xhci_input_control_ctx *ctrl_ctx;	unsigned int ep_index;	struct xhci_ep_ctx *ep_ctx;	u32 drop_flag;	u32 new_add_flags, new_drop_flags;	int ret;	ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);	if (ret <= 0)		return ret;	xhci = hcd_to_xhci(hcd);	if (xhci->xhc_state & XHCI_STATE_DYING)		return -ENODEV;	xhci_dbg(xhci, "%s called for udev %p/n", __func__, udev);	drop_flag = xhci_get_endpoint_flag(&ep->desc);	if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {		xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x/n",				__func__, drop_flag);		return 0;	}	in_ctx = xhci->devs[udev->slot_id]->in_ctx;	out_ctx = xhci->devs[udev->slot_id]->out_ctx;	ctrl_ctx = xhci_get_input_control_ctx(in_ctx);	if (!ctrl_ctx) {		xhci_warn(xhci, "%s: Could not get input context, bad type./n",				__func__);		return 0;	}	ep_index = xhci_get_endpoint_index(&ep->desc);	ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);	/* If the HC already knows the endpoint is disabled,	 * or the HCD has noted it is disabled, ignore this request	 */	if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==	     cpu_to_le32(EP_STATE_DISABLED)) ||	    le32_to_cpu(ctrl_ctx->drop_flags) &	    xhci_get_endpoint_flag(&ep->desc)) {		/* Do not warn when called after a usb_device_reset */		if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)			xhci_warn(xhci, "xHCI %s called with disabled ep %p/n",				  __func__, ep);		return 0;	}	ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);	new_drop_flags = le32_t

/* Return the maximum endpoint service interval time (ESIT) payload. * Basically, this is the maxpacket size, multiplied by the burst size * and mult size. */static inline u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,		struct usb_device *udev,		struct usb_host_endpoint *ep){	int max_burst;	int max_packet;	/* Only applies for interrupt or isochronous endpoints */	if (usb_endpoint_xfer_control(&ep->desc) ||			usb_endpoint_xfer_bulk(&ep->desc))		return 0;	if (udev->speed == USB_SPEED_SUPER) {		if (ep->ss_ep_comp)			return ep->ss_ep_comp->desc.wBytesPerInterval;		xhci_warn(xhci, "WARN no SS endpoint companion descriptor./n");		/* Assume no bursts, no multiple opportunities to send. */		return ep->desc.wMaxPacketSize;	}	max_packet = ep->desc.wMaxPacketSize & 0x3ff;	max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;	/* A 0 in max burst means 1 transfer per ESIT */	return max_packet * (max_burst + 1);}

/* * Stop device * It issues stop endpoint command for EP 0 to 30. And wait the last command * to complete. * suspend will set to 1, if suspend bit need to set in command. */static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend){	struct xhci_virt_device *virt_dev;	struct xhci_command *cmd;	unsigned long flags;	int timeleft;	int ret;	int i;	ret = 0;	virt_dev = xhci->devs[slot_id];	cmd = etxhci_alloc_command(xhci, false, true, GFP_NOIO);	if (!cmd) {		xhci_dbg(xhci, "Couldn't allocate command structure./n");		return -ENOMEM;	}	spin_lock_irqsave(&xhci->lock, flags);	for (i = LAST_EP_INDEX; i > 0; i--) {		if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)			etxhci_queue_stop_endpoint(xhci, slot_id, i, suspend);	}	cmd->command_trb = xhci->cmd_ring->enqueue;	/* Enqueue pointer can be left pointing to the link TRB,	 * we must handle that	 */	if (TRB_TYPE_LINK_LE32(cmd->command_trb->link.control))		cmd->command_trb =			xhci->cmd_ring->enq_seg->next->trbs;	list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);	etxhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);	etxhci_ring_cmd_db(xhci);	spin_unlock_irqrestore(&xhci->lock, flags);	/* Wait for last stop endpoint command to finish */	timeleft = wait_for_completion_interruptible_timeout(			cmd->completion,			USB_CTRL_SET_TIMEOUT);	if (timeleft <= 0) {		xhci_warn(xhci, "%s while waiting for stop endpoint command/n",				timeleft == 0 ? "Timeout" : "Signal");		spin_lock_irqsave(&xhci->lock, flags);		/* The timeout might have raced with the event ring handler, so		 * only delete from the list if the item isn't poisoned.		 */		if (cmd->cmd_list.next != LIST_POISON1)			list_del(&cmd->cmd_list);		spin_unlock_irqrestore(&xhci->lock, flags);		ret = -ETIME;		goto command_cleanup;	}command_cleanup:	etxhci_free_command(xhci, cmd);	return ret;}

int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,		struct usb_device *udev, gfp_t flags){	struct xhci_virt_device *dev;	int i;	/* Slot ID 0 is reserved */	if (slot_id == 0 || xhci->devs[slot_id]) {		xhci_warn(xhci, "Bad Slot ID %d/n", slot_id);		return 0;	}	xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);	if (!xhci->devs[slot_id])		return 0;	dev = xhci->devs[slot_id];	/* Allocate the (output) device context that will be used in the HC. */	dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);	if (!dev->out_ctx)		goto fail;	xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)/n", slot_id,			(unsigned long long)dev->out_ctx->dma);	/* Allocate the (input) device context for address device command */	dev->in_ctx = xhci_alloc_container_ctx(xhci, (XHCI_CTX_TYPE_INPUT), flags);	if (!dev->in_ctx)		goto fail;	xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)/n", slot_id,			(unsigned long long)dev->in_ctx->dma);	/* Initialize the cancellation list for each endpoint */	for (i = 0; i < 31; i++)		INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);	/* Allocate endpoint 0 ring */	dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags);	if (!dev->eps[0].ring)		goto fail;	init_completion(&dev->cmd_completion);	INIT_LIST_HEAD(&dev->cmd_list);	/* Point to output device context in dcbaa. */	xhci->dcbaa->dev_context_ptrs[slot_id] = SWAP64(dev->out_ctx->dma);	xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx/n",			slot_id,			&xhci->dcbaa->dev_context_ptrs[slot_id],			SWAP64((unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]));	return 1;fail:	xhci_free_virt_device(xhci, slot_id);	return 0;}

int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,		struct usb_device *udev, gfp_t flags){	struct xhci_virt_device *dev;	/* Slot ID 0 is reserved */	if (slot_id == 0 || xhci->devs[slot_id]) {		xhci_warn(xhci, "Bad Slot ID %d/n", slot_id);		return 0;	}	xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);	if (!xhci->devs[slot_id])		return 0;	dev = xhci->devs[slot_id];	/* Allocate the (output) device context that will be used in the HC. */	dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);	if (!dev->out_ctx)		goto fail;	xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)/n", slot_id,			(unsigned long long)dev->out_ctx->dma);	/* Allocate the (input) device context for address device command */	dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);	if (!dev->in_ctx)		goto fail;	xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)/n", slot_id,			(unsigned long long)dev->in_ctx->dma);	/* Allocate endpoint 0 ring */	dev->ep_rings[0] = xhci_ring_alloc(xhci, 1, true, flags);	if (!dev->ep_rings[0])		goto fail;	init_completion(&dev->cmd_completion);	/* Point to output device context in dcbaa. */	xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma;	xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx/n",			slot_id,			&xhci->dcbaa->dev_context_ptrs[slot_id],			(unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]);	UBI_DMA_FLUSH(&xhci->dcbaa->dev_context_ptrs[slot_id], sizeof(u64));	return 1;fail:	xhci_free_virt_device(xhci, slot_id);	return 0;}

/* Get the right ring for the given URB. * If the endpoint supports streams, boundary check the URB's stream ID. * If the endpoint doesn't support streams, return the singular endpoint ring. */static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,		struct urb *urb){	unsigned int slot_id;	unsigned int ep_index;	unsigned int stream_id;	struct xhci_virt_ep *ep;	slot_id = urb->dev->slot_id;	ep_index = xhci_get_endpoint_index(&urb->ep->desc);	stream_id = urb->stream_id;	ep = &xhci->devs[slot_id]->eps[ep_index];	/* Common case: no streams */	if (!(ep->ep_state & EP_HAS_STREAMS))		return ep->ring;	if (stream_id == 0) {		xhci_warn(xhci,				"WARN: Slot ID %u, ep index %u has streams, "				"but URB has no stream ID./n",				slot_id, ep_index);		return NULL;	}	if (stream_id < ep->stream_info->num_streams)		return ep->stream_info->stream_rings[stream_id];	xhci_warn(xhci,			"WARN: Slot ID %u, ep index %u has "			"stream IDs 1 to %u allocated, "			"but stream ID %u is requested./n",			slot_id, ep_index,			ep->stream_info->num_streams - 1,			stream_id);	return NULL;}

/* * Force HC into halt state. * * Disable any IRQs and clear the run/stop bit. * HC will complete any current and actively pipelined transactions, and * should halt within 16 ms of the run/stop bit being cleared. * Read HC Halted bit in the status register to see when the HC is finished. */int xhci_halt(struct xhci_hcd *xhci){	int ret;	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");	xhci_quiesce(xhci);	ret = xhci_handshake(&xhci->op_regs->status,			STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);	if (!ret) {		xhci->xhc_state |= XHCI_STATE_HALTED;		xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;	} else		xhci_warn(xhci, "Host not halted after %u microseconds./n",				XHCI_MAX_HALT_USEC);	return ret;}

void xhci_dbg_ctx(struct xhci_hcd *xhci,		  struct xhci_container_ctx *ctx,		  unsigned int last_ep){	int i;	/* Fields are 32 bits wide, DMA addresses are in bytes */	int field_size = 32 / 8;	dma_addr_t dma = ctx->dma;	int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);	if (ctx->type == XHCI_CTX_TYPE_INPUT) {		struct xhci_input_control_ctx *ctrl_ctx =			xhci_get_input_control_ctx(xhci, ctx);		if (!ctrl_ctx) {			xhci_warn(xhci, "Could not get input context, bad type./n");			return;		}		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags/n",			 &ctrl_ctx->drop_flags, (unsigned long long)dma,			 ctrl_ctx->drop_flags);		dma += field_size;		xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags/n",			 &ctrl_ctx->add_flags, (unsigned long long)dma,			 ctrl_ctx->add_flags);		dma += field_size;		for (i = 0; i < 6; ++i) {			xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]/n",				 &ctrl_ctx->rsvd2[i], (unsigned long long)dma,				 ctrl_ctx->rsvd2[i], i);			dma += field_size;		}		if (csz)			dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);	}	xhci_dbg_slot_ctx(xhci, ctx);	xhci_dbg_ep_ctx(xhci, ctx, last_ep);}

/* * Reset a halted HC. * * This resets pipelines, timers, counters, state machines, etc. * Transactions will be terminated immediately, and operational registers * will be set to their defaults. */int xhci_reset(struct xhci_hcd *xhci){	u32 command;	u32 state;	int ret, i;	state = readl(&xhci->op_regs->status);	if ((state & STS_HALT) == 0) {		xhci_warn(xhci, "Host controller not halted, aborting reset./n");		return 0;	}	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");	command = readl(&xhci->op_regs->command);	command |= CMD_RESET;	writel(command, &xhci->op_regs->command);	ret = xhci_handshake(&xhci->op_regs->command,			CMD_RESET, 0, 10 * 1000 * 1000);	if (ret)		return ret;	xhci_dbg_trace(xhci, trace_xhci_dbg_init,			 "Wait for controller to be ready for doorbell rings");	/*	 * xHCI cannot write to any doorbells or operational registers other	 * than status until the "Controller Not Ready" flag is cleared.	 */	ret = xhci_handshake(&xhci->op_regs->status,			STS_CNR, 0, 10 * 1000 * 1000);	for (i = 0; i < 2; ++i) {		xhci->bus_state[i].port_c_suspend = 0;		xhci->bus_state[i].suspended_ports = 0;		xhci->bus_state[i].resuming_ports = 0;	}	return ret;}

/* * non-error returns are a promise to giveback() the urb later * we drop ownership so next owner (or urb unlink) can get it */int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags){	struct xhci_hcd *xhci = hcd_to_xhci(hcd);	struct xhci_td *buffer;	unsigned long flags;	int ret = 0;	unsigned int slot_id, ep_index;	struct urb_priv	*urb_priv;	int size, i;	if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,					true, true, __func__) <= 0)		return -EINVAL;	slot_id = urb->dev->slot_id;	ep_index = xhci_get_endpoint_index(&urb->ep->desc);	if (!HCD_HW_ACCESSIBLE(hcd)) {		if (!in_interrupt())			xhci_dbg(xhci, "urb submitted during PCI suspend/n");		ret = -ESHUTDOWN;		goto exit;	}	if (usb_endpoint_xfer_isoc(&urb->ep->desc))		size = urb->number_of_packets;	else		size = 1;	urb_priv = kzalloc(sizeof(struct urb_priv) +				  size * sizeof(struct xhci_td *), mem_flags);	if (!urb_priv)		return -ENOMEM;	buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);	if (!buffer) {		kfree(urb_priv);		return -ENOMEM;	}	for (i = 0; i < size; i++) {		urb_priv->td[i] = buffer;		buffer++;	}	urb_priv->length = size;	urb_priv->td_cnt = 0;	urb->hcpriv = urb_priv;	if (usb_endpoint_xfer_control(&urb->ep->desc)) {		/* Check to see if the max packet size for the default control		 * endpoint changed during FS device enumeration		 */		if (urb->dev->speed == USB_SPEED_FULL) {			ret = xhci_check_maxpacket(xhci, slot_id,					ep_index, urb);			if (ret < 0) {				xhci_urb_free_priv(urb_priv);				urb->hcpriv = NULL;				return ret;			}		}		/* We have a spinlock and interrupts disabled, so we must pass		 * atomic context to this function, which may allocate memory.		 */		spin_lock_irqsave(&xhci->lock, flags);		if (xhci->xhc_state & XHCI_STATE_DYING)			goto dying;		ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,				slot_id, ep_index);		if (ret)			goto free_priv;		spin_unlock_irqrestore(&xhci->lock, flags);	} else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {		spin_lock_irqsave(&xhci->lock, flags);		if (xhci->xhc_state & XHCI_STATE_DYING)			goto dying;		if (xhci->devs[slot_id]->eps[ep_index].ep_state &				EP_GETTING_STREAMS) {			xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "					"is transitioning to using streams./n");			ret = -EINVAL;		} else if (xhci->devs[slot_id]->eps[ep_index].ep_state &				EP_GETTING_NO_STREAMS) {			xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "					"is transitioning to "					"not having streams./n");			ret = -EINVAL;		} else {			ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,					slot_id, ep_index);		}		if (ret)			goto free_priv;		spin_unlock_irqrestore(&xhci->lock, flags);//.........这里部分代码省略.........

/* * Full speed devices may have a max packet size greater than 8 bytes, but the * USB core doesn't know that until it reads the first 8 bytes of the * descriptor.  If the usb_device's max packet size changes after that point, * we need to issue an evaluate context command and wait on it. */static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,		unsigned int ep_index, struct urb *urb){	struct xhci_container_ctx *out_ctx;	struct xhci_input_control_ctx *ctrl_ctx;	struct xhci_ep_ctx *ep_ctx;	struct xhci_command *command;	int max_packet_size;	int hw_max_packet_size;	int ret = 0;	out_ctx = xhci->devs[slot_id]->out_ctx;	ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);	hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));	max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);	if (hw_max_packet_size != max_packet_size) {		xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,				"Max Packet Size for ep 0 changed.");		xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,				"Max packet size in usb_device = %d",				max_packet_size);		xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,				"Max packet size in xHCI HW = %d",				hw_max_packet_size);		xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,				"Issuing evaluate context command.");		/* Set up the input context flags for the command */		/* FIXME: This won't work if a non-default control endpoint		 * changes max packet sizes.		 */		command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);		if (!command)			return -ENOMEM;		command->in_ctx = xhci->devs[slot_id]->in_ctx;		ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);		if (!ctrl_ctx) {			xhci_warn(xhci, "%s: Could not get input context, bad type./n",					__func__);			ret = -ENOMEM;			goto command_cleanup;		}		/* Set up the modified control endpoint 0 */		xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,				xhci->devs[slot_id]->out_ctx, ep_index);		ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);		ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);		ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));		ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);		ctrl_ctx->drop_flags = 0;		xhci_dbg(xhci, "Slot %d input context/n", slot_id);		xhci_dbg_ctx(xhci, command->in_ctx, ep_index);		xhci_dbg(xhci, "Slot %d output context/n", slot_id);		xhci_dbg_ctx(xhci, out_ctx, ep_index);		ret = xhci_configure_endpoint(xhci, urb->dev, command,				true, false);		/* Clean up the input context for later use by bandwidth		 * functions.		 */		ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);command_cleanup:		kfree(command->completion);		kfree(command);	}	return ret;}

/* * Stop HC (not bus-specific) * * This is called when the machine transition into S3/S4 mode. * */int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup){	int			rc = 0;	unsigned int		delay = XHCI_MAX_HALT_USEC;	struct usb_hcd		*hcd = xhci_to_hcd(xhci);	u32			command;	if (!hcd->state)		return 0;	if (hcd->state != HC_STATE_SUSPENDED ||			xhci->shared_hcd->state != HC_STATE_SUSPENDED)		return -EINVAL;	/* Clear root port wake on bits if wakeup not allowed. */	if (!do_wakeup)		xhci_disable_port_wake_on_bits(xhci);	/* Don't poll the roothubs on bus suspend. */	xhci_dbg(xhci, "%s: stopping port polling./n", __func__);	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);	del_timer_sync(&hcd->rh_timer);	clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);	del_timer_sync(&xhci->shared_hcd->rh_timer);	spin_lock_irq(&xhci->lock);	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);	/* step 1: stop endpoint */	/* skipped assuming that port suspend has done */	/* step 2: clear Run/Stop bit */	command = readl(&xhci->op_regs->command);	command &= ~CMD_RUN;	writel(command, &xhci->op_regs->command);	/* Some chips from Fresco Logic need an extraordinary delay */	delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;	if (xhci_handshake(&xhci->op_regs->status,		      STS_HALT, STS_HALT, delay)) {		xhci_warn(xhci, "WARN: xHC CMD_RUN timeout/n");		spin_unlock_irq(&xhci->lock);		return -ETIMEDOUT;	}	xhci_clear_command_ring(xhci);	/* step 3: save registers */	xhci_save_registers(xhci);	/* step 4: set CSS flag */	command = readl(&xhci->op_regs->command);	command |= CMD_CSS;	writel(command, &xhci->op_regs->command);	if (xhci_handshake(&xhci->op_regs->status,				STS_SAVE, 0, 10 * 1000)) {		xhci_warn(xhci, "WARN: xHC save state timeout/n");		spin_unlock_irq(&xhci->lock);		return -ETIMEDOUT;	}	spin_unlock_irq(&xhci->lock);	/*	 * Deleting Compliance Mode Recovery Timer because the xHCI Host	 * is about to be suspended.	 */	if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&			(!(xhci_all_ports_seen_u0(xhci)))) {		del_timer_sync(&xhci->comp_mode_recovery_timer);		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,				"%s: compliance mode recovery timer deleted",				__func__);	}	/* step 5: remove core well power */	/* synchronize irq when using MSI-X */	xhci_msix_sync_irqs(xhci);	return rc;}

//.........这里部分代码省略.........			wake_mask = wIndex & 0xff00;		selector = wIndex >> 8;		wIndex &= 0xff;		if (!wIndex || wIndex > max_ports)			goto error;		wIndex--;		status_reg = &xhci->op_regs->port_power_base +			NUM_PORT_REGS*wIndex;		temp = xhci_readl(xhci, port_array[wIndex]);		if (temp == 0xffffffff) {			retval = -ENODEV;			break;		}		temp = xhci_port_state_to_neutral(temp);		/* FIXME: What new port features do we need to support? */		switch (wValue) {		case USB_PORT_FEAT_SUSPEND:			temp = xhci_readl(xhci, port_array[wIndex]);			if ((temp & PORT_PLS_MASK) != XDEV_U0) {				/* Resume the port to U0 first */				xhci_set_link_state(xhci, port_array, wIndex,							XDEV_U0);				spin_unlock_irqrestore(&xhci->lock, flags);				msleep(10);				spin_lock_irqsave(&xhci->lock, flags);			}			/* In spec software should not attempt to suspend			 * a port unless the port reports that it is in the			 * enabled (PED = ‘1’,PLS < ‘3’) state.			 */			temp = xhci_readl(xhci, port_array[wIndex]);			if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)				|| (temp & PORT_PLS_MASK) >= XDEV_U3) {				xhci_warn(xhci, "USB core suspending device "					  "not in U0/U1/U2./n");				goto error;			}			slot_id = xhci_find_slot_id_by_port(hcd, xhci,					wIndex + 1);			if (!slot_id) {				xhci_warn(xhci, "slot_id is zero/n");				goto error;			}			/* unlock to execute stop endpoint commands */			spin_unlock_irqrestore(&xhci->lock, flags);			xhci_stop_device(xhci, slot_id, 1);			spin_lock_irqsave(&xhci->lock, flags);			xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);			spin_unlock_irqrestore(&xhci->lock, flags);			msleep(10); /* wait device to enter */			spin_lock_irqsave(&xhci->lock, flags);			temp = xhci_readl(xhci, port_array[wIndex]);			bus_state->suspended_ports |= 1 << wIndex;			break;		case USB_PORT_FEAT_LINK_STATE:			temp = xhci_readl(xhci, port_array[wIndex]);			/* Disable port */			if (link_state == USB_SS_PORT_LS_SS_DISABLED) {				xhci_dbg(xhci, "Disable port %d/n", wIndex);				temp = xhci_port_state_to_neutral(temp);				/*

//.........这里部分代码省略.........		if (wValue == USB_PORT_FEAT_LINK_STATE)			link_state = (wIndex & 0xff00) >> 3;		if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)			wake_mask = wIndex & 0xff00;		wIndex &= 0xff;		if (!wIndex || wIndex > max_ports)			goto error;		wIndex--;		temp = xhci_readl(xhci, port_array[wIndex]);		if (temp == 0xffffffff) {			retval = -ENODEV;			break;		}		temp = xhci_port_state_to_neutral(temp);		/* FIXME: What new port features do we need to support? */		switch (wValue) {		case USB_PORT_FEAT_SUSPEND:			temp = xhci_readl(xhci, port_array[wIndex]);			if ((temp & PORT_PLS_MASK) != XDEV_U0) {				/* Resume the port to U0 first */				xhci_set_link_state(xhci, port_array, wIndex,							XDEV_U0);				spin_unlock_irqrestore(&xhci->lock, flags);				msleep(10);				spin_lock_irqsave(&xhci->lock, flags);			}			/* In spec software should not attempt to suspend			 * a port unless the port reports that it is in the			 * enabled (PED = ??1??,PLS < ??3??) state.			 */			temp = xhci_readl(xhci, port_array[wIndex]);			if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)				|| (temp & PORT_PLS_MASK) >= XDEV_U3) {				xhci_warn(xhci, "USB core suspending device "					  "not in U0/U1/U2./n");				goto error;			}			slot_id = xhci_find_slot_id_by_port(hcd, xhci,					wIndex + 1);			if (!slot_id) {				xhci_warn(xhci, "slot_id is zero/n");				goto error;			}			/* unlock to execute stop endpoint commands */			spin_unlock_irqrestore(&xhci->lock, flags);			xhci_stop_device(xhci, slot_id, 1);			spin_lock_irqsave(&xhci->lock, flags);			xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);			spin_unlock_irqrestore(&xhci->lock, flags);			msleep(10); /* wait device to enter */			spin_lock_irqsave(&xhci->lock, flags);			temp = xhci_readl(xhci, port_array[wIndex]);			bus_state->suspended_ports |= 1 << wIndex;			break;		case USB_PORT_FEAT_LINK_STATE:			temp = xhci_readl(xhci, port_array[wIndex]);			/* Disable port */			if (link_state == USB_SS_PORT_LS_SS_DISABLED) {				xhci_dbg(xhci, "Disable port %d/n", wIndex);				temp = xhci_port_state_to_neutral(temp);				/*

/* Setup an xHCI virtual device for a Set Address command */int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev){	struct xhci_virt_device *dev;	struct xhci_ep_ctx	*ep0_ctx;	struct usb_device	*top_dev;	struct xhci_slot_ctx    *slot_ctx;	struct xhci_input_control_ctx *ctrl_ctx;	dev = xhci->devs[udev->slot_id];	/* Slot ID 0 is reserved */	if (udev->slot_id == 0 || !dev) {		xhci_warn(xhci, "Slot ID %d is not assigned to this device/n",				udev->slot_id);		return -EINVAL;	}	ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);	ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);	slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);	/* 2) New slot context and endpoint 0 context are valid*/	ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG;	/* 3) Only the control endpoint is valid - one endpoint context */	slot_ctx->dev_info |= LAST_CTX(1);	slot_ctx->dev_info |= (u32) udev->route;	switch (udev->speed) {	case USB_SPEED_SUPER:		slot_ctx->dev_info |= (u32) SLOT_SPEED_SS;		break;	case USB_SPEED_HIGH:		slot_ctx->dev_info |= (u32) SLOT_SPEED_HS;		break;	case USB_SPEED_FULL:		slot_ctx->dev_info |= (u32) SLOT_SPEED_FS;		break;	case USB_SPEED_LOW:		slot_ctx->dev_info |= (u32) SLOT_SPEED_LS;		break;	case USB_SPEED_WIRELESS:		xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds/n");		return -EINVAL;		break;	default:		/* Speed was set earlier, this shouldn't happen. */		BUG();	}	/* Find the root hub port this device is under */	for (top_dev = udev; top_dev->parent && top_dev->parent->parent;			top_dev = top_dev->parent)		/* Found device below root hub */;	slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum);	xhci_dbg(xhci, "Set root hub portnum to %d/n", top_dev->portnum);	/* Is this a LS/FS device under a HS hub? */	if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) &&			udev->tt) {		slot_ctx->tt_info = udev->tt->hub->slot_id;		slot_ctx->tt_info |= udev->ttport << 8;		if (udev->tt->multi)			slot_ctx->dev_info |= DEV_MTT;	}	xhci_dbg(xhci, "udev->tt = %p/n", udev->tt);	xhci_dbg(xhci, "udev->ttport = 0x%x/n", udev->ttport);	/* Step 4 - ring already allocated */	/* Step 5 */	ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);	/*	 * XXX: Not sure about wireless USB devices.	 */	switch (udev->speed) {	case USB_SPEED_SUPER:		ep0_ctx->ep_info2 |= MAX_PACKET(512);		break;	case USB_SPEED_HIGH:	/* USB core guesses at a 64-byte max packet first for FS devices */	case USB_SPEED_FULL:		ep0_ctx->ep_info2 |= MAX_PACKET(64);		break;	case USB_SPEED_LOW:		ep0_ctx->ep_info2 |= MAX_PACKET(8);		break;	case USB_SPEED_WIRELESS:		xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds/n");		return -EINVAL;		break;	default:		/* New speed? */		BUG();	}	/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */	ep0_ctx->ep_info2 |= MAX_BURST(0);	ep0_ctx->ep_info2 |= ERROR_COUNT(3);	ep0_ctx->deq =		dev->eps[0].ring->first_seg->dma;	ep0_ctx->deq |= dev->eps[0].ring->cycle_state;//.........这里部分代码省略.........

int xhci_endpoint_init(struct xhci_hcd *xhci,		struct xhci_virt_device *virt_dev,		struct usb_device *udev,		struct usb_host_endpoint *ep,		gfp_t mem_flags){	unsigned int ep_index;	struct xhci_ep_ctx *ep_ctx;	struct xhci_ring *ep_ring;	unsigned int max_packet;	unsigned int max_burst;	ep_index = xhci_get_endpoint_index(&ep->desc);	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);	/* Set up the endpoint ring */	virt_dev->eps[ep_index].new_ring =		xhci_ring_alloc(xhci, 1, true, mem_flags);	if (!virt_dev->eps[ep_index].new_ring) {		/* Attempt to use the ring cache */		if (virt_dev->num_rings_cached == 0)			return -ENOMEM;		virt_dev->eps[ep_index].new_ring =			virt_dev->ring_cache[virt_dev->num_rings_cached];		virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;		virt_dev->num_rings_cached--;		xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring);	}	ep_ring = virt_dev->eps[ep_index].new_ring;	ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state;	ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep);	/* FIXME dig Mult and streams info out of ep companion desc */	/* Allow 3 retries for everything but isoc;	 * error count = 0 means infinite retries.	 */	if (!usb_endpoint_xfer_isoc(&ep->desc))		ep_ctx->ep_info2 = ERROR_COUNT(3);	else		ep_ctx->ep_info2 = ERROR_COUNT(1);	ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep);	/* Set the max packet size and max burst */	switch (udev->speed) {	case USB_SPEED_SUPER:		max_packet = ep->desc.wMaxPacketSize;		ep_ctx->ep_info2 |= MAX_PACKET(max_packet);		/* dig out max burst from ep companion desc */		if (!ep->ss_ep_comp) {			xhci_warn(xhci, "WARN no SS endpoint companion descriptor./n");			max_packet = 0;		} else {			max_packet = ep->ss_ep_comp->desc.bMaxBurst;		}		ep_ctx->ep_info2 |= MAX_BURST(max_packet);		break;	case USB_SPEED_HIGH:		/* bits 11:12 specify the number of additional transaction		 * opportunities per microframe (USB 2.0, section 9.6.6)		 */		if (usb_endpoint_xfer_isoc(&ep->desc) ||				usb_endpoint_xfer_int(&ep->desc)) {			max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;			ep_ctx->ep_info2 |= MAX_BURST(max_burst);		}		/* Fall through */	case USB_SPEED_FULL:	case USB_SPEED_LOW:		max_packet = ep->desc.wMaxPacketSize & 0x3ff;		ep_ctx->ep_info2 |= MAX_PACKET(max_packet);		break;	default:		BUG();	}

/* * start xHC (not bus-specific) * * This is called when the machine transition from S3/S4 mode. * */int xhci_resume(struct xhci_hcd *xhci, bool hibernated){	u32			command, temp = 0, status;	struct usb_hcd		*hcd = xhci_to_hcd(xhci);	struct usb_hcd		*secondary_hcd;	int			retval = 0;	bool			comp_timer_running = false;	if (!hcd->state)		return 0;	/* Wait a bit if either of the roothubs need to settle from the	 * transition into bus suspend.	 */	if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||			time_before(jiffies,				xhci->bus_state[1].next_statechange))		msleep(100);	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);	set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);	spin_lock_irq(&xhci->lock);	if (xhci->quirks & XHCI_RESET_ON_RESUME)		hibernated = true;	if (!hibernated) {		/* step 1: restore register */		xhci_restore_registers(xhci);		/* step 2: initialize command ring buffer */		xhci_set_cmd_ring_deq(xhci);		/* step 3: restore state and start state*/		/* step 3: set CRS flag */		command = readl(&xhci->op_regs->command);		command |= CMD_CRS;		writel(command, &xhci->op_regs->command);		if (xhci_handshake(&xhci->op_regs->status,			      STS_RESTORE, 0, 10 * 1000)) {			xhci_warn(xhci, "WARN: xHC restore state timeout/n");			spin_unlock_irq(&xhci->lock);			return -ETIMEDOUT;		}		temp = readl(&xhci->op_regs->status);	}	/* If restore operation fails, re-initialize the HC during resume */	if ((temp & STS_SRE) || hibernated) {		if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&				!(xhci_all_ports_seen_u0(xhci))) {			del_timer_sync(&xhci->comp_mode_recovery_timer);			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,				"Compliance Mode Recovery Timer deleted!");		}		/* Let the USB core know _both_ roothubs lost power. */		usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);		usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);		xhci_dbg(xhci, "Stop HCD/n");		xhci_halt(xhci);		xhci_reset(xhci);		spin_unlock_irq(&xhci->lock);		xhci_cleanup_msix(xhci);		xhci_dbg(xhci, "// Disabling event ring interrupts/n");		temp = readl(&xhci->op_regs->status);		writel(temp & ~STS_EINT, &xhci->op_regs->status);		temp = readl(&xhci->ir_set->irq_pending);		writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);		xhci_print_ir_set(xhci, 0);		xhci_dbg(xhci, "cleaning up memory/n");		xhci_mem_cleanup(xhci);		xhci_dbg(xhci, "xhci_stop completed - status = %x/n",			    readl(&xhci->op_regs->status));		/* USB core calls the PCI reinit and start functions twice:		 * first with the primary HCD, and then with the secondary HCD.		 * If we don't do the same, the host will never be started.		 */		if (!usb_hcd_is_primary_hcd(hcd))			secondary_hcd = hcd;		else			secondary_hcd = xhci->shared_hcd;		xhci_dbg(xhci, "Initialize the xhci_hcd/n");		retval = xhci_init(hcd->primary_hcd);		if (retval)			return retval;		comp_timer_running = true;		xhci_dbg(xhci, "Start the primary HCD/n");		retval = xhci_run(hcd->primary_hcd);//.........这里部分代码省略.........