自学教程：C++ BIT函数代码示例

/* hard_start_xmit function for master radio interface wifi#. * AP processing (TX rate control, power save buffering, etc.). * Use hardware TX function to send the frame. */int hostap_master_start_xmit(struct sk_buff *skb, struct net_device *dev){	struct hostap_interface *iface;	local_info_t *local;	int ret = NETDEV_TX_BUSY;	u16 fc;	struct hostap_tx_data tx;	ap_tx_ret tx_ret;	struct hostap_skb_tx_data *meta;	int no_encrypt = 0;	struct ieee80211_hdr *hdr;	iface = netdev_priv(dev);	local = iface->local;	tx.skb = skb;	tx.sta_ptr = NULL;	meta = (struct hostap_skb_tx_data *) skb->cb;	if (meta->magic != HOSTAP_SKB_TX_DATA_MAGIC) {		printk(KERN_DEBUG "%s: invalid skb->cb magic (0x%08x, "		       "expected 0x%08x)/n",		       dev->name, meta->magic, HOSTAP_SKB_TX_DATA_MAGIC);		ret = 0;		iface->stats.tx_dropped++;		goto fail;	}	if (local->host_encrypt) {		/* Set crypt to default algorithm and key; will be replaced in		 * AP code if STA has own alg/key */		tx.crypt = local->crypt_info.crypt[local->crypt_info.tx_keyidx];		tx.host_encrypt = 1;	} else {		tx.crypt = NULL;		tx.host_encrypt = 0;	}	if (skb->len < 24) {		printk(KERN_DEBUG "%s: hostap_master_start_xmit: short skb "		       "(len=%d)/n", dev->name, skb->len);		ret = 0;		iface->stats.tx_dropped++;		goto fail;	}	/* FIX (?):	 * Wi-Fi 802.11b test plan suggests that AP should ignore power save	 * bit in authentication and (re)association frames and assume tha	 * STA remains awake for the response. */	tx_ret = hostap_handle_sta_tx(local, &tx);	skb = tx.skb;	meta = (struct hostap_skb_tx_data *) skb->cb;	hdr = (struct ieee80211_hdr *) skb->data;	fc = le16_to_cpu(hdr->frame_control);	switch (tx_ret) {	case AP_TX_CONTINUE:		break;	case AP_TX_CONTINUE_NOT_AUTHORIZED:		if (local->ieee_802_1x &&		    ieee80211_is_data(hdr->frame_control) &&		    meta->ethertype != ETH_P_PAE &&		    !(meta->flags & HOSTAP_TX_FLAGS_WDS)) {			printk(KERN_DEBUG "%s: dropped frame to unauthorized "			       "port (IEEE 802.1X): ethertype=0x%04x/n",			       dev->name, meta->ethertype);			hostap_dump_tx_80211(dev->name, skb);			ret = 0; /* drop packet */			iface->stats.tx_dropped++;			goto fail;		}		break;	case AP_TX_DROP:		ret = 0; /* drop packet */		iface->stats.tx_dropped++;		goto fail;	case AP_TX_RETRY:		goto fail;	case AP_TX_BUFFERED:		/* do not free skb here, it will be freed when the		 * buffered frame is sent/timed out */		ret = 0;		goto tx_exit;	}	/* Request TX callback if protocol version is 2 in 802.11 header;	 * this version 2 is a special case used between hostapd and kernel	 * driver */	if (((fc & IEEE80211_FCTL_VERS) == BIT(1)) &&	    local->ap && local->ap->tx_callback_idx && meta->tx_cb_idx == 0) {		meta->tx_cb_idx = local->ap->tx_callback_idx;		/* remove special version from the frame header */		fc &= ~IEEE80211_FCTL_VERS;		hdr->frame_control = cpu_to_le16(fc);	}//.........这里部分代码省略.........

/*!    /brief      reset the peripherals    /param[in]  periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum                only one parameter can be selected which is shown as below:      /arg        RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports      /arg        RCU_AFRST : reset alternate function clock      /arg        RCU_USBFSRST: reset USBFS      /arg        RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER      /arg        RCU_WWDGTRST: reset WWDGT      /arg        RCU_SPIxRST (x=0,1,2): reset SPI      /arg        RCU_USARTxRST (x=0,1,2): reset USART      /arg        RCU_UARTxRST (x=3,4): reset UART      /arg        RCU_I2CxRST (x=0,1): reset I2C      /arg        RCU_CANxRST (x=0,1): reset CAN      /arg        RCU_PMURST: reset PMU      /arg        RCU_DACRST: reset DAC      /arg        RCU_ADCxRST (x=0,1): reset ADC      /arg        RCU_CTCRST: reset CTC      /arg        RCU_BKPIRST: reset BKPI    /param[out] none    /retval     none*/void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset){    RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));}

/*!    /brief      enable the stabilization interrupt    /param[in]  stab_int: clock stabilization interrupt, refer to rcu_int_enum                only one parameter can be selected which is shown as below:      /arg        RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable      /arg        RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable      /arg        RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable      /arg        RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable      /arg        RCU_INT_PLLSTB: PLL stabilization interrupt enable      /arg        RCU_INT_PLL1STB: PLL1 stabilization interrupt enable      /arg        RCU_INT_PLL2STB: PLL2 stabilization interrupt enable      /arg        RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable    /param[out] none    /retval     none*/void rcu_interrupt_enable(rcu_int_enum stab_int){    RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));}

static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,	struct ipu_client_platformdata *pdata, struct drm_device *drm){	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);	int dp = -EINVAL;	int ret;	int id;	ret = ipu_get_resources(ipu_crtc, pdata);	if (ret) {		dev_err(ipu_crtc->dev, "getting resources failed with %d./n",				ret);		return ret;	}	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,			&ipu_crtc_helper_funcs, ipu_crtc->dev->of_node);	if (ret) {		dev_err(ipu_crtc->dev, "adding crtc failed with %d./n", ret);		goto err_put_resources;	}	if (pdata->dp >= 0)		dp = IPU_DP_FLOW_SYNC_BG;	id = imx_drm_crtc_id(ipu_crtc->imx_crtc);	ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,					    pdata->dma[0], dp, BIT(id), true);	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);	if (ret) {		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d./n",			ret);		goto err_remove_crtc;	}	/* If this crtc is using the DP, add an overlay plane */	if (pdata->dp >= 0 && pdata->dma[1] > 0) {		ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu,						    pdata->dma[1],						    IPU_DP_FLOW_SYNC_FG,						    BIT(id), false);		if (IS_ERR(ipu_crtc->plane[1]))			ipu_crtc->plane[1] = NULL;	}	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,			"imx_drm", ipu_crtc);	if (ret < 0) {		dev_err(ipu_crtc->dev, "irq request failed with %d./n", ret);		goto err_put_plane_res;	}	return 0;err_put_plane_res:	ipu_plane_put_resources(ipu_crtc->plane[0]);err_remove_crtc:	imx_drm_remove_crtc(ipu_crtc->imx_crtc);err_put_resources:	ipu_put_resources(ipu_crtc);	return ret;}

void luxor_55_10828_device::abcbus_cs(UINT8 data){	UINT8 address = 0x2c | BIT(m_s1->read(), 0);	m_cs = (data == address);}

void ath_paprd_calibrate(struct work_struct *work){	struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);	struct ieee80211_hw *hw = sc->hw;	struct ath_hw *ah = sc->sc_ah;	struct ieee80211_hdr *hdr;	struct sk_buff *skb = NULL;	struct ath9k_hw_cal_data *caldata = ah->caldata;	struct ath_common *common = ath9k_hw_common(ah);	int ftype;	int chain_ok = 0;	int chain;	int len = 1800;	int ret;	if (!caldata || !caldata->paprd_packet_sent || caldata->paprd_done)		return;	ath9k_ps_wakeup(sc);	if (ar9003_paprd_init_table(ah) < 0)		goto fail_paprd;	skb = alloc_skb(len, GFP_KERNEL);	if (!skb)		goto fail_paprd;	skb_put(skb, len);	memset(skb->data, 0, len);	hdr = (struct ieee80211_hdr *)skb->data;	ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;	hdr->frame_control = cpu_to_le16(ftype);	hdr->duration_id = cpu_to_le16(10);	memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);	memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);	memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {		if (!(ah->txchainmask & BIT(chain)))			continue;		chain_ok = 0;		ar9003_paprd_setup_gain_table(ah, chain);		ath_dbg(common, CALIBRATE,			"Sending PAPRD training frame on chain %d/n", chain);		if (!ath_paprd_send_frame(sc, skb, chain))			goto fail_paprd;		if (!ar9003_paprd_is_done(ah)) {			ath_dbg(common, CALIBRATE,				"PAPRD not yet done on chain %d/n", chain);			break;		}		ret = ar9003_paprd_create_curve(ah, caldata, chain);		if (ret == -EINPROGRESS) {			ath_dbg(common, CALIBRATE,				"PAPRD curve on chain %d needs to be re-trained/n",				chain);			break;		} else if (ret) {			ath_dbg(common, CALIBRATE,				"PAPRD create curve failed on chain %d/n",				chain);			break;		}		chain_ok = 1;	}	kfree_skb(skb);	if (chain_ok) {		caldata->paprd_done = true;		ath_paprd_activate(sc);	}fail_paprd:	ath9k_ps_restore(sc);}

//.........这里部分代码省略.........    }    else if (functionName->isEqualTo(kFakeSMCGetKeyValue)) {                result = kIOReturnBadArgument;                if (const char *name = (const char *)param1) {                        result = kIOReturnError;                        if (FakeSMCKey *key = getKey(name)) {                                result = kIOReturnBadArgument;                                if (param2 && param3) {                    UInt8 *size = (UInt8*)param2;                    const void **value = (const void **)param3;                                        *size = key->getSize();                    *value = key->getValue();                                        result = kIOReturnSuccess;                }            }        }    }    else if (functionName->isEqualTo(kFakeSMCTakeVacantGPUIndex)) {                result = kIOReturnBadArgument;                KEYSLOCK;                if (SInt8 *index = (SInt8*)param1) {            for (UInt8 i = 0; i <= 0xf; i++) {                if (!bit_get(vacantGPUIndex, BIT(i))) {                    bit_set(vacantGPUIndex, BIT(i));                    *index = i;                    result = kIOReturnSuccess;                    break;                }            }                        if (result != kIOReturnSuccess)                result = kIOReturnError;        }                KEYSUNLOCK;    }    else if (functionName->isEqualTo(kFakeSMCTakeGPUIndex)) {                result = kIOReturnBadArgument;                KEYSLOCK;                if (UInt8 *index = (UInt8*)param1) {            if (*index < 0xf && !bit_get(vacantGPUIndex, BIT(*index))) {                bit_set(vacantGPUIndex, BIT(*index));                result = kIOReturnSuccess;            }                        if (result != kIOReturnSuccess)                result = kIOReturnError;        }                KEYSUNLOCK;    }    else if (functionName->isEqualTo(kFakeSMCReleaseGPUIndex)) {

#define ISL29028_DEV_ATTR(name) (&iio_dev_attr_##name.dev_attr.attr)#define ISL29028_CONST_ATTR(name) (&iio_const_attr_##name.dev_attr.attr)static struct attribute *isl29028_attributes[] = {	ISL29028_CONST_ATTR(in_proximity_sampling_frequency_available),	ISL29028_CONST_ATTR(in_illuminance_scale_available),	NULL,};static const struct attribute_group isl29108_group = {	.attrs = isl29028_attributes,};static const struct iio_chan_spec isl29028_channels[] = {	{		.type = IIO_LIGHT,		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |		BIT(IIO_CHAN_INFO_SCALE) |		BIT(IIO_CHAN_INFO_RAW),	}, {		.type = IIO_INTENSITY,		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	}, {		.type = IIO_PROXIMITY,		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		BIT(IIO_CHAN_INFO_SAMP_FREQ),	}};static const struct iio_info isl29028_info = {	.attrs = &isl29108_group,	.driver_module = THIS_MODULE,

static void send_assoc_resp(struct hostapd_data *hapd, struct sta_info *sta,			    u16 status_code, int reassoc, const u8 *ies,			    size_t ies_len){	int send_len;	u8 buf[sizeof(struct ieee80211_mgmt) + 1024];	struct ieee80211_mgmt *reply;	u8 *p;	os_memset(buf, 0, sizeof(buf));	reply = (struct ieee80211_mgmt *) buf;	reply->frame_control =		IEEE80211_FC(WLAN_FC_TYPE_MGMT,			     (reassoc ? WLAN_FC_STYPE_REASSOC_RESP :			      WLAN_FC_STYPE_ASSOC_RESP));	os_memcpy(reply->da, sta->addr, ETH_ALEN);	os_memcpy(reply->sa, hapd->own_addr, ETH_ALEN);	os_memcpy(reply->bssid, hapd->own_addr, ETH_ALEN);	send_len = IEEE80211_HDRLEN;	send_len += sizeof(reply->u.assoc_resp);	reply->u.assoc_resp.capab_info =		host_to_le16(hostapd_own_capab_info(hapd, sta, 0));	reply->u.assoc_resp.status_code = host_to_le16(status_code);	reply->u.assoc_resp.aid = host_to_le16((sta ? sta->aid : 0)					       | BIT(14) | BIT(15));	/* Supported rates */	p = hostapd_eid_supp_rates(hapd, reply->u.assoc_resp.variable);	/* Extended supported rates */	p = hostapd_eid_ext_supp_rates(hapd, p);#ifdef CONFIG_IEEE80211R	if (status_code == WLAN_STATUS_SUCCESS) {		/* IEEE 802.11r: Mobility Domain Information, Fast BSS		 * Transition Information, RSN, [RIC Response] */		p = wpa_sm_write_assoc_resp_ies(sta->wpa_sm, p,						buf + sizeof(buf) - p,						sta->auth_alg, ies, ies_len);	}#endif /* CONFIG_IEEE80211R */#ifdef CONFIG_IEEE80211W	if (status_code == WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY)		p = hostapd_eid_assoc_comeback_time(hapd, sta, p);#endif /* CONFIG_IEEE80211W */#ifdef CONFIG_IEEE80211N	p = hostapd_eid_ht_capabilities(hapd, p);	p = hostapd_eid_ht_operation(hapd, p);#endif /* CONFIG_IEEE80211N */	if (sta->flags & WLAN_STA_WMM)		p = hostapd_eid_wmm(hapd, p);#ifdef CONFIG_WPS	if (sta->flags & WLAN_STA_WPS) {		struct wpabuf *wps = wps_build_assoc_resp_ie();		if (wps) {			os_memcpy(p, wpabuf_head(wps), wpabuf_len(wps));			p += wpabuf_len(wps);			wpabuf_free(wps);		}	}#endif /* CONFIG_WPS */	send_len += p - reply->u.assoc_resp.variable;	if (hapd->drv.send_mgmt_frame(hapd, reply, send_len) < 0)		wpa_printf(MSG_INFO, "Failed to send assoc resp: %s",			   strerror(errno));}

int superpet_device::pet_diag_r(){	return BIT(m_system, 3);}

	/* NVM SW-Section offset (in words) definitions */	NVM_VERSION_EXT_NVM = 0,	RADIO_CFG_FAMILY_EXT_NVM = 0,	SKU_FAMILY_8000 = 2,	N_HW_ADDRS_FAMILY_8000 = 3,	/* NVM REGULATORY -Section offset (in words) definitions */	NVM_CHANNELS_EXTENDED = 0,	NVM_LAR_OFFSET_OLD = 0x4C7,	NVM_LAR_OFFSET = 0x507,	NVM_LAR_ENABLED = 0x7,};/* SKU Capabilities (actual values from NVM definition) */enum nvm_sku_bits {	NVM_SKU_CAP_BAND_24GHZ		= BIT(0),	NVM_SKU_CAP_BAND_52GHZ		= BIT(1),	NVM_SKU_CAP_11N_ENABLE		= BIT(2),	NVM_SKU_CAP_11AC_ENABLE		= BIT(3),	NVM_SKU_CAP_MIMO_DISABLE	= BIT(5),};/* * These are the channel numbers in the order that they are stored in the NVM */static const u16 iwl_nvm_channels[] = {	/* 2.4 GHz */	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,	/* 5 GHz */	36, 40, 44 , 48, 52, 56, 60, 64,	100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,

void superpet_device::pet_bd_w(address_space &space, offs_t offset, uint8_t data, int &sel){	switch (sel)	{	case pet_expansion_slot_device::SEL9:		if (!m_sel9_rom && is_ram_writable())		{			m_ram[((m_bank & 0x0f) << 12) | (offset & 0xfff)] = data;		}		break;	}	switch (offset)	{	case 0xefe0:	case 0xefe1:	case 0xefe2:	case 0xefe3:		m_dongle->write(space, offset & 0x03, data);		printf("6702 %u %02x/n", offset & 0x03, data);		break;	case 0xeff0:	case 0xeff1:	case 0xeff2:	case 0xeff3:		m_acia->write(space, offset & 0x03, data);		break;	case 0xeff8:	case 0xeff9:		if (BIT(m_bank, 7))		{			/*			    bit     description			    0       SW2 CPU (0=6809, 1=6502)			    1       SW1 RAM (0=read only, 1=read/write)			    2			    3       DIAG			    4			    5			    6			    7			*/			m_system = data;			update_cpu();			printf("SYSTEM %02x/n", data);		}		break;	case 0xeffc:	case 0xeffd:		/*		    bit     description		    0       A0		    1       A1		    2       A2		    3       SEL A		    4       J1 pin 40		    5       SEL B		    6       J1 pin 39		    7       BIT 7		*/		m_bank = data;		printf("BANK %02x/n", data);		break;	}}

inline bool superpet_device::is_ram_writable(){	return (m_sw1 == 2) ? BIT(m_system, 1) : m_sw1;}

static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id){	struct ath_softc *sc;	struct ieee80211_hw *hw;	u8 csz;	u32 val;	int ret = 0;	char hw_name[64];	if (pcim_enable_device(pdev))		return -EIO;	ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));	if (ret) {		pr_err("32-bit DMA not available/n");		return ret;	}	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));	if (ret) {		pr_err("32-bit DMA consistent DMA enable failed/n");		return ret;	}	/*	 * Cache line size is used to size and align various	 * structures used to communicate with the hardware.	 */	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);	if (csz == 0) {		/*		 * Linux 2.4.18 (at least) writes the cache line size		 * register as a 16-bit wide register which is wrong.		 * We must have this setup properly for rx buffer		 * DMA to work so force a reasonable value here if it		 * comes up zero.		 */		csz = L1_CACHE_BYTES / sizeof(u32);		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);	}	/*	 * The default setting of latency timer yields poor results,	 * set it to the value used by other systems. It may be worth	 * tweaking this setting more.	 */	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);	pci_set_master(pdev);	/*	 * Disable the RETRY_TIMEOUT register (0x41) to keep	 * PCI Tx retries from interfering with C3 CPU state.	 */	pci_read_config_dword(pdev, 0x40, &val);	if ((val & 0x0000ff00) != 0)		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);	ret = pcim_iomap_regions(pdev, BIT(0), "ath9k");	if (ret) {		dev_err(&pdev->dev, "PCI memory region reserve error/n");		return -ENODEV;	}	ath9k_fill_chanctx_ops();	hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);	if (!hw) {		dev_err(&pdev->dev, "No memory for ieee80211_hw/n");		return -ENOMEM;	}	SET_IEEE80211_DEV(hw, &pdev->dev);	pci_set_drvdata(pdev, hw);	sc = hw->priv;	sc->hw = hw;	sc->dev = &pdev->dev;	sc->mem = pcim_iomap_table(pdev)[0];	sc->driver_data = id->driver_data;	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);	if (ret) {		dev_err(&pdev->dev, "request_irq failed/n");		goto err_irq;	}	sc->irq = pdev->irq;	ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);	if (ret) {		dev_err(&pdev->dev, "Failed to initialize device/n");		goto err_init;	}	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));	wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d/n",		   hw_name, (unsigned long)sc->mem, pdev->irq);	return 0;err_init://.........这里部分代码省略.........

void tvout_Change_dis_size(u8 factor, bool updateFlag){	static u8 u8pre_factor = 0;	u32 tmpLCDcon46 = 0;	u32 lcd_con_reg_save;	if(!updateFlag)	{		if(u8pre_factor != factor)			u8pre_factor = factor;		else			return;	}			switch(factor)	{		case 0:			lcd_con_reg_save = REG32(LCDCON0);			DIS_OSD1();			DIS_OSD2();			DIS_OSD3();			lcd_set_panel_colour(0,0,0);			#if(0 == LCD_MCU)				waittingLcdFrameEnd();				REG32(LCDCON0) &= ~(BIT(0)|BIT(6));				tmpLCDcon46 = REG32(LCDCON46);				tvout_Set_Dis_Offset(0,0,u32csi_Dma_Size_H);				while (tmpLCDcon46 == REG32(LCDCON46));				tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H,u32csi_Dma_Size_V,tvout_get_w(),tvout_get_h());					REG32(LCDCON0) = lcd_con_reg_save;				REG32(LCDCON0) |= (BIT(0)|BIT(6));			#else				REG32(LCDCON0) &= ~(BIT(6));				waittingLcdFrameEnd();				tmpLCDcon46 = REG32(LCDCON46);				tvout_Set_Dis_Offset(0,0,u32csi_Dma_Size_H);				while (tmpLCDcon46 == REG32(LCDCON46));				tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H,u32csi_Dma_Size_V,tvout_get_w(),tvout_get_h());					waittingLcdFrameEnd();				REG32(LCDCON0) = lcd_con_reg_save;				REG32(LCDCON0) |= (BIT(6));			#endif		break;		case 1:			lcd_con_reg_save = REG32(LCDCON0);			DIS_OSD1();			DIS_OSD2();			DIS_OSD3();			lcd_set_panel_colour(0,0,0);			#if(0 == LCD_MCU)				waittingLcdFrameEnd();				REG32(LCDCON0) &= ~(BIT(0)|BIT(6));				tmpLCDcon46 = REG32(LCDCON46);				tvout_Set_Dis_Offset(u32csi_Dma_Size_H/4,u32csi_Dma_Size_V/4,u32csi_Dma_Size_H);				while (tmpLCDcon46 == REG32(LCDCON46));				tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H/2,u32csi_Dma_Size_V/2,tvout_get_w(),tvout_get_h());					REG32(LCDCON0) = lcd_con_reg_save;				REG32(LCDCON0) |= (BIT(0)|BIT(6));			#else				REG32(LCDCON0) &= ~(BIT(6));				waittingLcdFrameEnd();				tmpLCDcon46 = REG32(LCDCON46);				tvout_Set_Dis_Offset(u32csi_Dma_Size_H/4,u32csi_Dma_Size_V/4,u32csi_Dma_Size_H);				while (tmpLCDcon46 == REG32(LCDCON46));				tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H/2,u32csi_Dma_Size_V/2,tvout_get_w(),tvout_get_h());					waittingLcdFrameEnd();				REG32(LCDCON0) = lcd_con_reg_save;				REG32(LCDCON0) |= (BIT(6));			#endif					break;		case 2:			lcd_con_reg_save = REG32(LCDCON0);			DIS_OSD1();			DIS_OSD2();			DIS_OSD3();			lcd_set_panel_colour(0,0,0);			#if(0 == LCD_MCU)				waittingLcdFrameEnd();				REG32(LCDCON0) &= ~(BIT(0)|BIT(6));				tmpLCDcon46 = REG32(LCDCON46);				tvout_Set_Dis_Offset(u32csi_Dma_Size_H*3/8,u32csi_Dma_Size_V*3/8,u32csi_Dma_Size_H);				while (tmpLCDcon46 == REG32(LCDCON46));				tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H/4,u32csi_Dma_Size_V/4,tvout_get_w(),tvout_get_h());					REG32(LCDCON0) = lcd_con_reg_save;				REG32(LCDCON0) |= (BIT(0)|BIT(6));			#else				REG32(LCDCON0) &= ~(BIT(6));				waittingLcdFrameEnd();				tmpLCDcon46 = REG32(LCDCON46);				tvout_Set_Dis_Offset(u32csi_Dma_Size_H*3/8,u32csi_Dma_Size_V*3/8,u32csi_Dma_Size_H);				while (tmpLCDcon46 == REG32(LCDCON46));				tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H/4,u32csi_Dma_Size_V/4,tvout_get_w(),tvout_get_h());					waittingLcdFrameEnd();				REG32(LCDCON0) = lcd_con_reg_save;				REG32(LCDCON0) |= (BIT(6));			#endif		break;		default:			break;//.........这里部分代码省略.........

/** * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership * @mem_addr: mem region whose ownership need to be reassigned * @mem_sz:   size of the region. * @srcvm:    vmid for current set of owners, each set bit in *            flag indicate a unique owner * @newvm:    array having new owners and corrsponding permission *            flags * @dest_cnt: number of owners in next set. * * Return negative errno on failure, 0 on success, with @srcvm updated. */int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,			unsigned int *srcvm,			struct qcom_scm_vmperm *newvm, int dest_cnt){	struct qcom_scm_current_perm_info *destvm;	struct qcom_scm_mem_map_info *mem_to_map;	phys_addr_t mem_to_map_phys;	phys_addr_t dest_phys;	phys_addr_t ptr_phys;	size_t mem_to_map_sz;	size_t dest_sz;	size_t src_sz;	size_t ptr_sz;	int next_vm;	__le32 *src;	void *ptr;	int ret;	int len;	int i;	src_sz = hweight_long(*srcvm) * sizeof(*src);	mem_to_map_sz = sizeof(*mem_to_map);	dest_sz = dest_cnt * sizeof(*destvm);	ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) +			ALIGN(dest_sz, SZ_64);	ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL);	if (!ptr)		return -ENOMEM;	/* Fill source vmid detail */	src = ptr;	len = hweight_long(*srcvm);	for (i = 0; i < len; i++) {		src[i] = cpu_to_le32(ffs(*srcvm) - 1);		*srcvm ^= 1 << (ffs(*srcvm) - 1);	}	/* Fill details of mem buff to map */	mem_to_map = ptr + ALIGN(src_sz, SZ_64);	mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64);	mem_to_map[0].mem_addr = cpu_to_le64(mem_addr);	mem_to_map[0].mem_size = cpu_to_le64(mem_sz);	next_vm = 0;	/* Fill details of next vmid detail */	destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);	dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);	for (i = 0; i < dest_cnt; i++) {		destvm[i].vmid = cpu_to_le32(newvm[i].vmid);		destvm[i].perm = cpu_to_le32(newvm[i].perm);		destvm[i].ctx = 0;		destvm[i].ctx_size = 0;		next_vm |= BIT(newvm[i].vmid);	}	ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz,				    ptr_phys, src_sz, dest_phys, dest_sz);	dma_free_coherent(__scm->dev, ALIGN(ptr_sz, SZ_64), ptr, ptr_phys);	if (ret) {		dev_err(__scm->dev,			"Assign memory protection call failed %d./n", ret);		return -EINVAL;	}	*srcvm = next_vm;	return 0;}

static DEFINE_CLK_VOTER(bimc_usb_a_clk,  &bimc_a_clk.c,  LONG_MAX);/* Branch Voter clocks */static DEFINE_CLK_BRANCH_VOTER(xo_gcc, &xo_clk_src.c);static DEFINE_CLK_BRANCH_VOTER(xo_otg_clk, &xo_clk_src.c);static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo_clk_src.c);static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo_clk_src.c);static DEFINE_CLK_BRANCH_VOTER(xo_pil_mss_clk, &xo_clk_src.c);static DEFINE_CLK_BRANCH_VOTER(xo_wlan_clk, &xo_clk_src.c);static struct mux_clk rpm_debug_mux = {	.ops = &mux_reg_ops,	.offset = GCC_DEBUG_CLK_CTL,	.mask = 0x1FF,	.en_offset = GCC_DEBUG_CLK_CTL,	.en_mask = BIT(16),	.base = &virt_base,	MUX_SRC_LIST(	{&snoc_clk.c,  0x0000},	{&pcnoc_clk.c, 0x0008},	/* BIMC_CLK is 2x clock to the BIMC Core as well as DDR, while the	 * axi clock is for the BIMC AXI interface. The AXI clock is 1/2 of	 * the BIMC Clock. measure the gcc_bimc_apss_axi_clk.	 */	{&bimc_clk.c,  0x0155},	),	.c = {		.dbg_name = "rpm_debug_mux",		.ops = &clk_ops_gen_mux,		.flags = CLKFLAG_NO_RATE_CACHE,		CLK_INIT(rpm_debug_mux.c),

	RxeOV=		SBIT(14),	RxeCL=		SBIT(15),	RxError=	(RxeLG|RxeNO|RxeSH|RxeCR|RxeOV|RxeCL),	/* various error flags */	/* ether-specific Tx BD bits */	TxPad=		SBIT(1),	/* pad short frames */	TxTC=		SBIT(5),	/* transmit CRC */	TxeDEF=		SBIT(6),	TxeHB=		SBIT(7),	TxeLC=		SBIT(8),	TxeRL=		SBIT(9),	TxeUN=		SBIT(14),	TxeCSL=		SBIT(15),	/* psmr */	CRCE=		BIT(24),	/* Ethernet CRC */	FCE=		BIT(10),	/* flow control */	PRO=		BIT(9),		/* promiscuous mode */	FDE=		BIT(5),		/* full duplex ethernet */	LPB=		BIT(3),		/* local protect bit */	/* gfmr */	ENET=		0xc,		/* ethernet mode */	ENT=		BIT(27),	ENR=		BIT(26),	TCI=		BIT(2),	/* FCC function code register */	GBL=		0x20,	BO=		0x18,	EB=		0x10,		/* Motorola byte order */

 the provisions above, a recipient may use your version of this file under the terms of any one of the MPL, the GPL or the LGPL.  */#include "CPUSensors.h"#include "FakeSMCDefinitions.h"#include "IntelDefinitions.h"#include <IOKit/IODeviceTreeSupport.h>#include <IOKit/IORegistryEntry.h>#include "timer.h"enum {    kCPUSensorsCoreThermalSensor           = BIT(0),    kCPUSensorsPackageThermalSensor        = BIT(1),    kCPUSensorsCoreMultiplierSensor        = BIT(2),    kCPUSensorsPackageMultiplierSensor     = BIT(3),    kCPUSensorsCoreFrequencySensor         = BIT(4),    kCPUSensorsPackageFrequencySensor      = BIT(5),    kCPUSensorsTotalPowerSensor            = BIT(6),    kCPUSensorsCoresPowerSensor            = BIT(7),    kCPUSensorsUncorePowerSensor           = BIT(8),    kCPUSensorsDramPowerSensor             = BIT(9),};#define super FakeSMCPluginOSDefineMetaClassAndStructors(CPUSensors, FakeSMCPlugin)static inline UInt8 get_hex_index(char c)

#define GET_CPU_OF_ATTR(attr) /	(container_of(attr, struct msm_pm_kobj_attribute, ka)->cpu)#define SCLK_HZ (32768)#define MAX_BUF_SIZE  512static int msm_pm_debug_mask = 1;module_param_named(	debug_mask, msm_pm_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);static bool use_acpuclk_apis;enum {	MSM_PM_DEBUG_SUSPEND = BIT(0),	MSM_PM_DEBUG_POWER_COLLAPSE = BIT(1),	MSM_PM_DEBUG_SUSPEND_LIMITS = BIT(2),	MSM_PM_DEBUG_CLOCK = BIT(3),	MSM_PM_DEBUG_RESET_VECTOR = BIT(4),	MSM_PM_DEBUG_IDLE_CLK = BIT(5),	MSM_PM_DEBUG_IDLE = BIT(6),	MSM_PM_DEBUG_IDLE_LIMITS = BIT(7),	MSM_PM_DEBUG_HOTPLUG = BIT(8),};enum msm_pc_count_offsets {	MSM_PC_ENTRY_COUNTER,	MSM_PC_EXIT_COUNTER,	MSM_PC_FALLTHRU_COUNTER,	MSM_PC_NUM_COUNTERS,

#define ST_TEMP_LPS25H_OUT_L_ADDR		0x2bstatic const struct iio_chan_spec st_press_1_channels[] = {	{		.type = IIO_PRESSURE,		.channel2 = IIO_NO_MOD,		.address = ST_PRESS_1_OUT_XL_ADDR,		.scan_index = ST_SENSORS_SCAN_X,		.scan_type = {			.sign = 'u',			.realbits = 24,			.storagebits = 24,			.endianness = IIO_LE,		},		.info_mask_separate =			BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),		.modified = 0,	},	{		.type = IIO_TEMP,		.channel2 = IIO_NO_MOD,		.address = ST_TEMP_1_OUT_L_ADDR,		.scan_index = -1,		.scan_type = {			.sign = 'u',			.realbits = 16,			.storagebits = 16,			.endianness = IIO_LE,		},		.info_mask_separate =			BIT(IIO_CHAN_INFO_RAW) |

static void square_set(board_t * board, int square, int piece, int pos, bool update) {   int piece_12, colour;   int sq;   int i, size;   int sq_64;   uint64 hash_xor;   ASSERT(board!=NULL);   ASSERT(SQUARE_IS_OK(square));   ASSERT(piece_is_ok(piece));   ASSERT(pos>=0);   ASSERT(update==true||update==false);   // init   piece_12 = PIECE_TO_12(piece);   colour = PIECE_COLOUR(piece);   // square   ASSERT(board->square[square]==Empty);   board->square[square] = piece;   // piece list   if (!PIECE_IS_PAWN(piece)) {      // init      size = board->piece_size[colour];      ASSERT(size>=0);      // size      size++;      board->piece[colour][size] = SquareNone;      board->piece_size[colour] = size;      // stable swap      ASSERT(pos>=0&&pos<size);      for (i = size-1; i > pos; i--) {         sq = board->piece[colour][i-1];         board->piece[colour][i] = sq;         ASSERT(board->pos[sq]==i-1);         board->pos[sq] = i;      }      board->piece[colour][pos] = square;      ASSERT(board->pos[square]==-1);      board->pos[square] = pos;   } else {      // init      size = board->pawn_size[colour];      ASSERT(size>=0);      // size      size++;      board->pawn[colour][size] = SquareNone;      board->pawn_size[colour] = size;      // stable swap      ASSERT(pos>=0&&pos<size);      for (i = size-1; i > pos; i--) {         sq = board->pawn[colour][i-1];         board->pawn[colour][i] = sq;         ASSERT(board->pos[sq]==i-1);         board->pos[sq] = i;      }      board->pawn[colour][pos] = square;      ASSERT(board->pos[square]==-1);      board->pos[square] = pos;      // pawn "bitboard"      board->pawn_file[colour][SQUARE_FILE(square)] ^= BIT(PAWN_RANK(square,colour));   }   // material   ASSERT(board->piece_nb<32);//.........这里部分代码省略.........

/*!    /brief      enable the peripherals clock when sleep mode    /param[in]  periph: RCU peripherals, refer to rcu_periph_sleep_enum                only one parameter can be selected which is shown as below:      /arg        RCU_FMC_SLP: FMC clock      /arg        RCU_SRAM_SLP: SRAM clock    /param[out] none    /retval     none*/void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph){    RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));}

static void square_move(board_t * board, int from, int to, int piece, bool update) {   int colour;   int pos;   int from_64, to_64;   int piece_12;   int piece_index;   uint64 hash_xor;   ASSERT(board!=NULL);   ASSERT(SQUARE_IS_OK(from));   ASSERT(SQUARE_IS_OK(to));   ASSERT(piece_is_ok(piece));   ASSERT(update==true||update==false);   // init   colour = PIECE_COLOUR(piece);   pos = board->pos[from];   ASSERT(pos>=0);   // from   ASSERT(board->square[from]==piece);   board->square[from] = Empty;   ASSERT(board->pos[from]==pos);   board->pos[from] = -1; // not needed   // to   ASSERT(board->square[to]==Empty);   board->square[to] = piece;   ASSERT(board->pos[to]==-1);   board->pos[to] = pos;   // piece list   if (!PIECE_IS_PAWN(piece)) {      ASSERT(board->piece[colour][pos]==from);      board->piece[colour][pos] = to;   } else {      ASSERT(board->pawn[colour][pos]==from);      board->pawn[colour][pos] = to;      // pawn "bitboard"      board->pawn_file[colour][SQUARE_FILE(from)] ^= BIT(PAWN_RANK(from,colour));      board->pawn_file[colour][SQUARE_FILE(to)]   ^= BIT(PAWN_RANK(to,colour));   }   // update   if (update) {      // init      from_64 = SQUARE_TO_64(from);      to_64 = SQUARE_TO_64(to);      piece_12 = PIECE_TO_12(piece);      // PST      board->opening += PST(piece_12,to_64,Opening) - PST(piece_12,from_64,Opening);      board->endgame += PST(piece_12,to_64,Endgame) - PST(piece_12,from_64,Endgame);      // hash key      piece_index = RandomPiece + (piece_12^1) * 64; // HACK: ^1 for PolyGlot book      hash_xor = RANDOM_64(piece_index+to_64) ^ RANDOM_64(piece_index+from_64);      board->key ^= hash_xor;      if (PIECE_IS_PAWN(piece)) board->pawn_key ^= hash_xor;   }}

/*!    /brief      clear the interrupt flags    /param[in]  int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum                only one parameter can be selected which is shown as below:      /arg        RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear      /arg        RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear      /arg        RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear      /arg        RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear      /arg        RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear      /arg        RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear      /arg        RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear      /arg        RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear      /arg        RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear    /param[out] none    /retval     none*/void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear){    RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));}

/* * Configure WPA parameters. */static intmadwifi_configure_wpa(struct madwifi_driver_data *drv,		      struct wpa_bss_params *params){	int v;	switch (params->wpa_group) {	case WPA_CIPHER_CCMP:		v = IEEE80211_CIPHER_AES_CCM;		break;	case WPA_CIPHER_TKIP:		v = IEEE80211_CIPHER_TKIP;		break;	case WPA_CIPHER_WEP104:		v = IEEE80211_CIPHER_WEP;		break;	case WPA_CIPHER_WEP40:		v = IEEE80211_CIPHER_WEP;		break;	case WPA_CIPHER_NONE:		v = IEEE80211_CIPHER_NONE;		break;	default:		wpa_printf(MSG_ERROR, "Unknown group key cipher %u",			   params->wpa_group);		return -1;	}	wpa_printf(MSG_DEBUG, "%s: group key cipher=%d", __func__, v);	if (set80211param(drv, IEEE80211_PARAM_MCASTCIPHER, v)) {		printf("Unable to set group key cipher to %u/n", v);		return -1;	}	if (v == IEEE80211_CIPHER_WEP) {		/* key length is done only for specific ciphers */		v = (params->wpa_group == WPA_CIPHER_WEP104 ? 13 : 5);		if (set80211param(drv, IEEE80211_PARAM_MCASTKEYLEN, v)) {			printf("Unable to set group key length to %u/n", v);			return -1;		}	}	v = 0;	if (params->wpa_pairwise & WPA_CIPHER_CCMP)		v |= 1<<IEEE80211_CIPHER_AES_CCM;	if (params->wpa_pairwise & WPA_CIPHER_TKIP)		v |= 1<<IEEE80211_CIPHER_TKIP;	if (params->wpa_pairwise & WPA_CIPHER_NONE)		v |= 1<<IEEE80211_CIPHER_NONE;	wpa_printf(MSG_DEBUG, "%s: pairwise key ciphers=0x%x", __func__, v);	if (set80211param(drv, IEEE80211_PARAM_UCASTCIPHERS, v)) {		printf("Unable to set pairwise key ciphers to 0x%x/n", v);		return -1;	}	wpa_printf(MSG_DEBUG, "%s: key management algorithms=0x%x",		   __func__, params->wpa_key_mgmt);	if (set80211param(drv, IEEE80211_PARAM_KEYMGTALGS,			  params->wpa_key_mgmt)) {		printf("Unable to set key management algorithms to 0x%x/n",			params->wpa_key_mgmt);		return -1;	}	v = 0;	if (params->rsn_preauth)		v |= BIT(0);	wpa_printf(MSG_DEBUG, "%s: rsn capabilities=0x%x",		   __func__, params->rsn_preauth);	if (set80211param(drv, IEEE80211_PARAM_RSNCAPS, v)) {		printf("Unable to set RSN capabilities to 0x%x/n", v);		return -1;	}	wpa_printf(MSG_DEBUG, "%s: enable WPA=0x%x", __func__, params->wpa);	if (set80211param(drv, IEEE80211_PARAM_WPA, params->wpa)) {		printf("Unable to set WPA to %u/n", params->wpa);		return -1;	}	return 0;}

/*!    /brief      turn on the oscillator    /param[in]  osci: oscillator types, refer to rcu_osci_type_enum                only one parameter can be selected which is shown as below:      /arg        RCU_HXTAL: high speed crystal oscillator(HXTAL)      /arg        RCU_LXTAL: low speed crystal oscillator(LXTAL)      /arg        RCU_IRC8M: internal 8M RC oscillators(IRC8M)      /arg        RCU_IRC48M: internal 48M RC oscillators(IRC48M)      /arg        RCU_IRC40K: internal 40K RC oscillator(IRC40K)      /arg        RCU_PLL_CK: phase locked loop(PLL)      /arg        RCU_PLL1_CK: phase locked loop 1      /arg        RCU_PLL2_CK: phase locked loop 2    /param[out] none    /retval     none*/void rcu_osci_on(rcu_osci_type_enum osci){    RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));}

#include <linux/tick.h>#include <linux/suspend.h>#include <linux/pm_qos.h>#include <linux/of_platform.h>#include <mach/mpm.h>#include <mach/cpuidle.h>#include <mach/event_timer.h>#include "pm.h"#include "rpm-notifier.h"#include "spm.h"#include "idle.h"#define SCLK_HZ (32768)enum {	MSM_LPM_LVL_DBG_SUSPEND_LIMITS = BIT(0),	MSM_LPM_LVL_DBG_IDLE_LIMITS = BIT(1),};struct power_params {	uint32_t latency_us;	uint32_t ss_power;	uint32_t energy_overhead;	uint32_t time_overhead_us;	uint32_t target_residency_us;};struct lpm_cpu_level {	const char *name;	enum msm_pm_sleep_mode mode;	struct power_params pwr;