自学教程：C++ BRCM_WRITE_REG函数代码示例

//============================================================================//// Function Name: cVoid chal_audio_earpath_enable(CHAL_HANDLE handle, cUInt16 enable)//// Description:  Enable or Disable earpiece path//// Parameters:   handle - audio chal handle.//                 enable - true : enable, false : disable.// Return:       None.////============================================================================cVoid chal_audio_earpath_enable(CHAL_HANDLE handle, cUInt16 enable){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    cUInt32 reg_val;    cUInt32 Channl_Ctrl = 0x00000000;    if(enable == CHAL_AUDIO_ENABLE)    {        Channl_Ctrl |= AUDIOH_DAC_CTL_VOUT_ENABLE_MASK;    }    else    {        Channl_Ctrl &= ~AUDIOH_DAC_CTL_VOUT_ENABLE_MASK;    }    reg_val = BRCM_READ_REG(base, AUDIOH_DAC_CTL);    reg_val &= ~(AUDIOH_DAC_CTL_VOUT_ENABLE_MASK);    reg_val |= Channl_Ctrl;    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_DAC_CTL, reg_val);    return;}

//function parameters changedvoid chal_audio_vinpath_set_cic_scale(CHAL_HANDLE handle,			cUInt32 dmic1_coarse_scale,			cUInt32 dmic1_fine_scale,			cUInt32 dmic2_coarse_scale,			cUInt32 dmic2_fine_scale){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    cUInt32 value = 0;    // Read VIN path FIFO status	value = BRCM_READ_REG(base, AUDIOH_VIN_FILTER_CTRL);    value &= ~(AUDIOH_VIN_FILTER_CTRL_DMIC1_CIC_BIT_SEL_MASK|AUDIOH_VIN_FILTER_CTRL_DMIC1_CIC_FINE_SCL_MASK|AUDIOH_VIN_FILTER_CTRL_DMIC2_CIC_BIT_SEL_MASK|AUDIOH_VIN_FILTER_CTRL_DMIC2_CIC_FINE_SCL_MASK);    dmic1_coarse_scale <<= (AUDIOH_VIN_FILTER_CTRL_DMIC1_CIC_BIT_SEL_SHIFT);    dmic1_fine_scale <<= (AUDIOH_VIN_FILTER_CTRL_DMIC1_CIC_FINE_SCL_SHIFT);    dmic2_coarse_scale <<= (AUDIOH_VIN_FILTER_CTRL_DMIC2_CIC_BIT_SEL_SHIFT);    dmic2_fine_scale <<= (AUDIOH_VIN_FILTER_CTRL_DMIC2_CIC_FINE_SCL_SHIFT);    value |= (dmic1_coarse_scale|dmic1_fine_scale|dmic2_coarse_scale|dmic2_fine_scale);    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_VIN_FILTER_CTRL, value);    return;}

/**** Description:  Enable or Disable dac loopback** Parameters:   handle - audio chal handle.*               enable - true : enable, false : disable.** Return:       None.******************************************************************************/cVoid chal_audio_dac_loopback_enable(CHAL_HANDLE handle, cUInt16 enable){	cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;	cUInt32 reg_val;	reg_val = BRCM_READ_REG(base, AUDIOH_LOOPBACK_CTRL);	if(enable == CHAL_AUDIO_ENABLE) {		reg_val |= AUDIOH_LOOPBACK_CTRL_ENABLE_DIG_TX_CLK_MASK;		reg_val |= AUDIOH_LOOPBACK_CTRL_DISABLE_ANA_TX_CLK_MASK;		reg_val |= AUDIOH_LOOPBACK_CTRL_DISABLE_ANA_RX_CLK_MASK;		reg_val |= AUDIOH_LOOPBACK_CTRL_DAC_SDM_LOOPBACK_9LEVEL_MASK;		reg_val |= AUDIOH_LOOPBACK_CTRL_DAC_SDM_LOOPBACK_EN_MASK;		reg_val &= ~AUDIOH_LOOPBACK_CTRL_LOOPBACK_EN_MASK;	} else {		reg_val  &= ~(AUDIOH_LOOPBACK_CTRL_ENABLE_DIG_TX_CLK_MASK |		AUDIOH_LOOPBACK_CTRL_DISABLE_ANA_TX_CLK_MASK |		AUDIOH_LOOPBACK_CTRL_DISABLE_ANA_RX_CLK_MASK |		AUDIOH_LOOPBACK_CTRL_DAC_SDM_LOOPBACK_9LEVEL_MASK|		AUDIOH_LOOPBACK_CTRL_DAC_SDM_LOOPBACK_EN_MASK);	}	/* Set the required setting */	BRCM_WRITE_REG(base,  AUDIOH_LOOPBACK_CTRL, reg_val);	return;}

void chal_audio_api_set_dac_attenuation(CHAL_HANDLE handle, cUInt32 dac_mask, cUInt16 enable){    cUInt32     reg_val;    cUInt32     reg_dac_mask = 0x00000000;    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    /* Enable/Disable the API attenuation for the DAC Paths.*/    if(dac_mask& (CHAL_AUDIO_PATH_HEADSET_LEFT|CHAL_AUDIO_PATH_HEADSET_RIGHT))    {        reg_dac_mask |= AUDIOH_AUDIO_API_STEREO_API_ATT_MASK;    }    if(dac_mask&CHAL_AUDIO_PATH_IHF_LEFT)    {        reg_dac_mask |= AUDIOH_AUDIO_API_IHF_API_ATT_MASK;    }    if(dac_mask&CHAL_AUDIO_PATH_EARPIECE)    {        reg_dac_mask |= AUDIOH_AUDIO_API_VOUT_API_ATT_MASK;    }    reg_val = BRCM_READ_REG(base, AUDIOH_AUDIO_API);    reg_val &= (~reg_dac_mask);    if(enable == CHAL_AUDIO_ENABLE)    {        reg_val |= (reg_dac_mask);    }    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_AUDIO_API, reg_val);    return;}

//============================================================================//// Function Name: cVoid chal_audio_vibra_int_enable(CHAL_HANDLE handle, cUInt16 thr_int_enable, cUInt16 err_int_enable )//// Description:  Enable or Disable vibra path interrupt//// Parameters:   handle      - audio chal handle.//                 int_enable  - true : enable interrupt, false : disable interrupt.// Return:       None.////============================================================================cVoid chal_audio_vibra_int_enable(CHAL_HANDLE handle, cUInt16 thr_int_enable, cUInt16 err_int_enable  ){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    cUInt32 reg_val;    reg_val = BRCM_READ_REG(base, AUDIOH_AUDIO_INTC);    if(thr_int_enable == CHAL_AUDIO_ENABLE)    {        reg_val |= AUDIOH_AUDIO_INTC_VIBRA_INTEN_MASK;    }    else    {        reg_val &= ~AUDIOH_AUDIO_INTC_VIBRA_INTEN_MASK;    }    if(err_int_enable == CHAL_AUDIO_ENABLE)    {        reg_val |= AUDIOH_AUDIO_INTC_VIBRA_FIFO_ERRINT_EN_MASK;    }    else    {        reg_val &= ~AUDIOH_AUDIO_INTC_VIBRA_FIFO_ERRINT_EN_MASK;    }    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_AUDIO_INTC, reg_val);    return;}

/*============================================================================** Function Name: cVoid chal_audio_stpath_int_enable(CHAL_HANDLE handle,*                            cUInt16 thr_int_enable, cUInt16 err_int_enable )** Description:  Enable interrupt on voice out path** Parameters:   handle      : the sidetone feedback  pathhandle.*                 enable      : enable flag** Return:       None.**============================================================================*/cVoid chal_audio_stpath_int_enable(CHAL_HANDLE handle, cUInt16 thr_int_enable,				   cUInt16 err_int_enable){	cUInt32 base = ((ChalAudioCtrlBlk_t *) handle)->sdt_base;	cUInt32 reg_val;	reg_val = BRCM_READ_REG(base, SDT_SDT_CTRL_3);	if (thr_int_enable == CHAL_AUDIO_ENABLE)		reg_val |= SDT_SDT_CTRL_3_INTR_EN_MASK;	else		reg_val &= ~SDT_SDT_CTRL_3_INTR_EN_MASK;	if (err_int_enable == CHAL_AUDIO_ENABLE)		reg_val |= SDT_SDT_CTRL_3_ERR_INTR_EN_MASK;	else		reg_val &= ~SDT_SDT_CTRL_3_ERR_INTR_EN_MASK;	/* Set the required setting */	BRCM_WRITE_REG(base, SDT_SDT_CTRL_3, reg_val);	return;}

cVoid chal_audio_hspath_sdm_enable_dither(CHAL_HANDLE handle, cUInt16 enable){	cUInt32 reg_val;	cUInt32 hs_dither_enable = 0x00000000;	cUInt32 base = ((ChalAudioCtrlBlk_t *) handle)->audioh_base;	if (enable & CHAL_AUDIO_CHANNEL_LEFT) {		hs_dither_enable |=		    AUDIOH_SDM_DITHER_CTL_STEREO_DITHER_EN_L_MASK;	}	if (enable & CHAL_AUDIO_CHANNEL_RIGHT) {		hs_dither_enable |=		    AUDIOH_SDM_DITHER_CTL_STEREO_DITHER_EN_R_MASK;	}	reg_val = BRCM_READ_REG(base, AUDIOH_SDM_DITHER_CTL);	reg_val &= ~AUDIOH_SDM_DITHER_CTL_STEREO_DITHER_EN_L_MASK;	reg_val &= ~AUDIOH_SDM_DITHER_CTL_STEREO_DITHER_EN_R_MASK;	reg_val |= hs_dither_enable;	BRCM_WRITE_REG(base, AUDIOH_SDM_DITHER_CTL, reg_val);	return;}

/*============================================================================*/void chal_audio_nvinpath_set_filter(CHAL_HANDLE handle, cUInt16 filter){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    cUInt32 reg_val;    reg_val = BRCM_READ_REG(base, AUDIOH_MIN_PHASE);	/*reg_val &= ~(AUDIOH_MIN_PHASE_DMIC3_MIN_PHASE_MASK |	AUDIOH_MIN_PHASE_DMIC4_MIN_PHASE_MASK);*/    if(filter & CHAL_AUDIO_MINIMUM_PHASE_FILTER)    {        reg_val |= AUDIOH_MIN_PHASE_DMIC3_MIN_PHASE_MASK;    }    if(filter & CHAL_AUDIO_MINIMUM_PHASE_FILTER_L)    {        reg_val |= AUDIOH_MIN_PHASE_DMIC4_MIN_PHASE_MASK;    }    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_MIN_PHASE, reg_val);    return;}

void chal_audio_nvinpath_select_sidetone (CHAL_HANDLE handle, cUInt16 read_sidetone){    cUInt32     reg_val;    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    /*Read the current contents*/    reg_val = BRCM_READ_REG(base, AUDIOH_NVIN_FIFO_CTRL);    /* Clear the paths that were enabled before*/    reg_val &= ~AUDIOH_NVIN_FIFO_CTRL_SIDETONE_SEL_L_MASK;    reg_val &= ~AUDIOH_NVIN_FIFO_CTRL_SIDETONE_SEL_R_MASK;    if(read_sidetone&CHAL_AUDIO_CHANNEL_LEFT)    {        /* Enable Left Channel to read side tone data*/        reg_val |= AUDIOH_NVIN_FIFO_CTRL_SIDETONE_SEL_L_MASK;    }    if(read_sidetone&CHAL_AUDIO_CHANNEL_RIGHT)    {        /* Enable Right Channel to read side tone data*/        reg_val |= AUDIOH_NVIN_FIFO_CTRL_SIDETONE_SEL_R_MASK;    }    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_NVIN_FIFO_CTRL, reg_val);    return;}

//============================================================================cVoid chal_audio_ihfpath_enable(CHAL_HANDLE handle, cUInt16 enable_chan){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    cUInt32 reg_val;    cUInt32 Channl_Ctrl = 0x00000000;    if(enable_chan&CHAL_AUDIO_CHANNEL_LEFT)    {       Channl_Ctrl |= AUDIOH_DAC_CTL_IHF_L_ENABLE_MASK;    }    if(enable_chan&CHAL_AUDIO_CHANNEL_RIGHT)    {       Channl_Ctrl |= AUDIOH_DAC_CTL_IHF_R_ENABLE_MASK;    }    reg_val = BRCM_READ_REG(base, AUDIOH_DAC_CTL);    reg_val &= ~(AUDIOH_DAC_CTL_IHF_L_ENABLE_MASK | AUDIOH_DAC_CTL_IHF_R_ENABLE_MASK);    reg_val |= Channl_Ctrl;    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_DAC_CTL, reg_val);    return;}

void chal_audio_vinpath_clr_fifo(CHAL_HANDLE handle){    cUInt32     reg_val;    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    reg_val = BRCM_READ_REG(base, AUDIOH_VIN_FIFO_CTRL);    reg_val |= AUDIOH_VIN_FIFO_CTRL_VIN_FIFO_CLEAR_MASK;    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_VIN_FIFO_CTRL, reg_val);    reg_val &= ~AUDIOH_VIN_FIFO_CTRL_VIN_FIFO_CLEAR_MASK;    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_VIN_FIFO_CTRL, reg_val);    return;}

void chal_audio_int_clear(CHAL_HANDLE handle, cUInt32 reg_val){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_AUDIO_INT_STATUS, reg_val);}

cVoid chal_audio_ihfpath_sdm_enable_dither_gain(CHAL_HANDLE handle,                                   cUInt16 gain_enable){    cUInt32 reg_val;    cUInt32 hs_dither_gain = 0x00000000;    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    if(gain_enable&CHAL_AUDIO_CHANNEL_LEFT)    {        hs_dither_gain |= AUDIOH_SDM_DITHER_CTL_IHF_DITHER_NOISE_GAIN_L_MASK;    }    if(gain_enable&CHAL_AUDIO_CHANNEL_RIGHT)    {        hs_dither_gain |= AUDIOH_SDM_DITHER_CTL_IHF_DITHER_NOISE_GAIN_R_MASK;    }    reg_val = BRCM_READ_REG(base, AUDIOH_SDM_DITHER_CTL);    reg_val &= ~AUDIOH_SDM_DITHER_CTL_IHF_DITHER_NOISE_GAIN_L_MASK;    reg_val &= ~AUDIOH_SDM_DITHER_CTL_IHF_DITHER_NOISE_GAIN_R_MASK;    reg_val |= hs_dither_gain;    BRCM_WRITE_REG(base, AUDIOH_SDM_DITHER_CTL, reg_val);    return;}

/******************************************************************************  Function Name: void chal_caph_switch_disable_clock(CHAL_HANDLE handle)**  Description: CAPH ASW disable clock*  - set M0_RATIO=0*  - wait a 3 CK26MHz clocks (CK96KHZ_en should never go high again)*  - set SSASW_NOC_EN=0*  - could also set M0_RATIO value here****************************************************************************/void chal_caph_switch_disable_clock(CHAL_HANDLE handle){    cUInt32     base = ((chal_caph_switch_cb_t*)handle)->base;	cUInt32 reg_val, loop;	reg_val = BRCM_READ_REG(base, CPH_SSASW_SSASW_MN0_DIVIDER);	reg_val &= ~CPH_SSASW_SSASW_MN0_DIVIDER_M0_RATIO_MASK;	BRCM_WRITE_REG(base, CPH_SSASW_SSASW_MN0_DIVIDER, reg_val);	for (loop = 5; loop != 0; loop--)    reg_val = BRCM_READ_REG( base,  CPH_SSASW_SSASW_NOC);	reg_val = BRCM_READ_REG(base, CPH_SSASW_SSASW_NOC);    reg_val &= ~(CPH_SSASW_SSASW_NOC_SSASW_NOC_EN_MASK);    BRCM_WRITE_REG( base,  CPH_SSASW_SSASW_NOC,reg_val);    return;}

cVoid chal_audio_hspath_sdm_set_dither_strength(CHAL_HANDLE handle,						cUInt16 dither_streng_L,						cUInt16 dither_streng_R){	cUInt32 reg_val;	cUInt32 hs_dither_strngth = 0x00000000;	cUInt32 base = ((ChalAudioCtrlBlk_t *) handle)->audioh_base;	hs_dither_strngth |=	    (dither_streng_L & (CHAL_AUDIO_DITHER_STRENGTH_MASK)) <<	    AUDIOH_SDM_DITHER_CTL_STEREO_DITHER_STRENGTH_L_SHIFT;	hs_dither_strngth |=	    (dither_streng_R & (CHAL_AUDIO_DITHER_STRENGTH_MASK)) <<	    AUDIOH_SDM_DITHER_CTL_STEREO_DITHER_STRENGTH_R_SHIFT;	reg_val = BRCM_READ_REG(base, AUDIOH_SDM_DITHER_CTL);	reg_val &= ~(AUDIOH_SDM_DITHER_CTL_STEREO_DITHER_STRENGTH_L_MASK);	reg_val &= ~(AUDIOH_SDM_DITHER_CTL_STEREO_DITHER_STRENGTH_R_MASK);	reg_val |= hs_dither_strngth;	BRCM_WRITE_REG(base, AUDIOH_SDM_DITHER_CTL, reg_val);	return;}

void chal_audio_ihfpath_sdm_enable_dither(CHAL_HANDLE handle,                                   uint16_t enable){    uint32_t reg_val;    uint32_t hs_dither_enable = 0x00000000;    uint32_t base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    if(enable&CHAL_AUDIO_CHANNEL_LEFT)    {        hs_dither_enable |= AUDIOH_SDM_DITHER_CTL_IHF_DITHER_EN_L_MASK;    }    if(enable&CHAL_AUDIO_CHANNEL_RIGHT)    {        hs_dither_enable |= AUDIOH_SDM_DITHER_CTL_IHF_DITHER_EN_R_MASK;    }    reg_val = BRCM_READ_REG( base, AUDIOH_SDM_DITHER_CTL);    reg_val &= ~AUDIOH_SDM_DITHER_CTL_IHF_DITHER_EN_L_MASK;    reg_val &= ~AUDIOH_SDM_DITHER_CTL_IHF_DITHER_EN_R_MASK;    reg_val |= hs_dither_enable;    BRCM_WRITE_REG( base, AUDIOH_SDM_DITHER_CTL, reg_val);    return;}

cVoid chal_audio_stpath_clr_fifo(CHAL_HANDLE handle){	cUInt32 reg_val;	cUInt32 base = ((ChalAudioCtrlBlk_t *) handle)->sdt_base;	reg_val = BRCM_READ_REG(base, SDT_SDT_CTRL_3);	reg_val |= SDT_SDT_CTRL_3_FIFO_RESET_MASK;	/* Set the required setting */	BRCM_WRITE_REG(base, SDT_SDT_CTRL_3, reg_val);	reg_val &= ~SDT_SDT_CTRL_3_FIFO_RESET_MASK;	/* Set the required setting */	BRCM_WRITE_REG(base, SDT_SDT_CTRL_3, reg_val);	return;}

void chal_audio_ihfpath_int_enable(CHAL_HANDLE handle, uint16_t thr_int_enable, uint16_t err_int_enable ){        uint32_t base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    uint32_t reg_val;    reg_val = BRCM_READ_REG(base, AUDIOH_AUDIO_INTC);    if(thr_int_enable == CHAL_AUDIO_ENABLE)    {        reg_val |= AUDIOH_AUDIO_INTC_IHF_INTEN_MASK;    }    else    {        reg_val &= ~AUDIOH_AUDIO_INTC_IHF_INTEN_MASK;    }    if(err_int_enable == CHAL_AUDIO_ENABLE)    {        reg_val |= AUDIOH_AUDIO_INTC_IHF_FIFO_ERRINT_EN_MASK;    }    else    {        reg_val &= ~AUDIOH_AUDIO_INTC_IHF_FIFO_ERRINT_EN_MASK;    }    /* Set the required setting */    BRCM_WRITE_REG(base,  AUDIOH_AUDIO_INTC, reg_val);    return;}

cVoid chal_audio_earpath_sdm_set_coef(CHAL_HANDLE handle, cUInt32 *SDM_coef ){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    BRCM_WRITE_REG(base,  AUDIOH_VOUT_SDM_COEF, *SDM_coef);    return;}

cVoid chal_audio_earpath_sdm_set_dither_seed(CHAL_HANDLE handle, cUInt32 vout_dither_seed){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    BRCM_WRITE_REG(base,  AUDIOH_VOUT_DITHER_SEED, vout_dither_seed);    return;}

cVoid chal_audio_earpath_sdm_set_dither_poly(CHAL_HANDLE handle, cUInt32 vout_dither_poly){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    BRCM_WRITE_REG(base,  AUDIOH_VOUT_DITHER_POLY, (vout_dither_poly | AUDIOH_VOUT_DITHER_POLY_VOUT_DITHER_SET_MASK));    return;}

void chal_audio_eancpath_ctrl_shift(CHAL_HANDLE handle, cUInt32 shift){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    BRCM_WRITE_REG(base, AUDIOH_EANC_SHIFT_CTRL, shift);    return;}

/* * ============================================================================ * *  Function Name: chal_audio_headset_mic_select * *  Description:   select analog headset mic * *  Parameters: *                 handle   ---  the  audio handle * *  Return:        none * * ============================================================================ */void chal_audio_headset_mic_select(CHAL_HANDLE handle){	cUInt32 base = ((ChalAudioCtrlBlk_t *)handle)->audioh_base;	cUInt32 reg_val = BRCM_READ_REG(base, AUDIOH_AUDIORX_VRX1);	reg_val |= AUDIOH_AUDIORX_VRX1_AUDIORX_VRX_SEL_MIC1B_MIC2_MASK;	BRCM_WRITE_REG(base,  AUDIOH_AUDIORX_VRX1, reg_val);}

cVoid chal_audio_vibra_sdm_set_coef(CHAL_HANDLE handle, cUInt32 *SDM_coef ){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    BRCM_WRITE_REG(base,  AUDIOH_VIBRA_SDM_CTRL, *SDM_coef);    return;}

/******************************************************************************  Function Name: cVoid chal_caph_cfifo_queue_remove_fifo(CHAL_HANDLE handle,*			cUInt16 fifo,*			CAPH_CFIFO_QUEUE_e queue)**  Description: remove fifos from queue*****************************************************************************/cVoid chal_caph_cfifo_queue_remove_fifo(CHAL_HANDLE handle,					cUInt16 fifo, CAPH_CFIFO_QUEUE_e queue){	cUInt32 base = ((chal_caph_cfifo_cb_t *) handle)->base;	cUInt32 arb;	cUInt32 rem_arb;	switch (queue) {	case CAPH_CFIFO_QUEUE2:		/* take it from Q2 */		arb = BRCM_READ_REG(base, CPH_CFIFO_CPH_ARB_CTL_1);		rem_arb = (fifo << CPH_CFIFO_CPH_ARB_CTL_1_Q2_MASK_SHIFT);		arb &= ~rem_arb;		BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_1, arb);		break;	case CAPH_CFIFO_QUEUE3:		/* take it from Q3 */		arb = BRCM_READ_REG(base, CPH_CFIFO_CPH_ARB_CTL_2);		rem_arb = (fifo << CPH_CFIFO_CPH_ARB_CTL_2_Q3_MASK_SHIFT);		arb &= ~rem_arb;		BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_2, arb);		break;	default:		/* take it from Q1 (default) */		arb = BRCM_READ_REG(base, CPH_CFIFO_CPH_ARB_CTL_1);		rem_arb = (fifo << CPH_CFIFO_CPH_ARB_CTL_1_Q1_MASK_SHIFT);		arb &= ~rem_arb;		BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_1, arb);		break;	}	return;}

cVoid chal_audio_hspath_hs_supply_thres(CHAL_HANDLE handle,					cUInt32 hs_supply_thres){	cUInt32 base = ((ChalAudioCtrlBlk_t *) handle)->audioh_base;	BRCM_WRITE_REG(base, AUDIOH_HS_DRIVER_SUPPLY_TH, hs_supply_thres);	return;}

cVoid chal_audio_earpath_set_drv_pwr(CHAL_HANDLE handle, cUInt16 enable){	cUInt32 base = ((ChalAudioCtrlBlk_t *) handle)->audioh_base;	cUInt32 reg_value;	if (enable & CHAL_AUDIO_ENABLE) {		/* Clear power down for the DRV */		reg_value = BRCM_READ_REG(base, AUDIOH_EP_DRV);		reg_value &= ~AUDIOH_EP_DRV_AUDIOTX_EP_DRV_PD_MASK;		BRCM_WRITE_REG(base, AUDIOH_EP_DRV, reg_value);	} else {		/* Shut down for the DRV */		reg_value = BRCM_READ_REG(base, AUDIOH_EP_DRV);		reg_value |= AUDIOH_EP_DRV_AUDIOTX_EP_DRV_PD_MASK;		BRCM_WRITE_REG(base, AUDIOH_EP_DRV, reg_value);	}	return;}

//function renamed from chal_audio_mic_syncvoid chal_audio_adcpath_global_enable( CHAL_HANDLE handle, _Bool on_off ){    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    /* Read and make room for change */    cUInt32 val = ( BRCM_READ_REG(base, AUDIOH_ADCPATH_GLOBAL_CTRL) & ~ AUDIOH_ADCPATH_GLOBAL_CTRL_GLOABAL_EN_MASK );    /* Set the required setting */    BRCM_WRITE_REG ( base,  AUDIOH_ADCPATH_GLOBAL_CTRL, val | (on_off << AUDIOH_ADCPATH_GLOBAL_CTRL_GLOABAL_EN_SHIFT) );}

void chal_audio_stpath_set_filter_taps(CHAL_HANDLE handle, uint16_t lower_taps, uint16_t upper_taps){    uint32_t base =    ((ChalAudioCtrlBlk_t*)handle)->sdt_base;    uint32_t     reg_val = 0;    /*Update the soft slope*/    reg_val = BRCM_READ_REG(base, SDT_SDT_CTRL_2);    reg_val &= (~SDT_SDT_CTRL_2_UPPER_FIT_TAP_MASK);    reg_val |= (upper_taps << SDT_SDT_CTRL_2_UPPER_FIT_TAP_SHIFT);    BRCM_WRITE_REG(base, SDT_SDT_CTRL_2, reg_val);    /*Update the linear and soft slope*/    reg_val = BRCM_READ_REG(base, SDT_SDT_CTL);    reg_val &= (~SDT_SDT_CTL_LOWER_FIT_TAP_MASK);    reg_val |= (lower_taps << SDT_SDT_CTL_LOWER_FIT_TAP_SHIFT);    BRCM_WRITE_REG(base, SDT_SDT_CTL, reg_val);    return;}

cVoid chal_audio_vibra_clr_int(CHAL_HANDLE handle){    cUInt32     reg_val;    cUInt32 base =    ((ChalAudioCtrlBlk_t*)handle)->audioh_base;    reg_val = AUDIOH_AUDIO_INT_STATUS_VIBRA_INT_MASK| AUDIOH_AUDIO_INT_STATUS_VIBRA_FIFO_ERR_MASK;    BRCM_WRITE_REG(base, AUDIOH_AUDIO_INT_STATUS, reg_val);    return;}