自学教程：C++ DELAY函数代码示例

static inttlphy_service(struct mii_softc *self, struct mii_data *mii, int cmd){	struct tlphy_softc *sc = (struct tlphy_softc *)self;	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;	int reg;	if (sc->sc_need_acomp)		tlphy_acomp(sc);	switch (cmd) {	case MII_POLLSTAT:		/*		 * If we're not polling our PHY instance, just return.		 */		if (IFM_INST(ife->ifm_media) != sc->sc_mii.mii_inst)			return (0);		break;	case MII_MEDIACHG:		/*		 * If the media indicates a different PHY instance,		 * isolate ourselves.		 */		if (IFM_INST(ife->ifm_media) != sc->sc_mii.mii_inst) {			reg = PHY_READ(&sc->sc_mii, MII_BMCR);			PHY_WRITE(&sc->sc_mii, MII_BMCR, reg | BMCR_ISO);			return (0);		}				/*		 * If the interface is not up, don't do anything.		 */		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)			break;		switch (IFM_SUBTYPE(ife->ifm_media)) {		case IFM_AUTO:			/*			 * The ThunderLAN PHY doesn't self-configure after			 * an autonegotiation cycle, so there's no such			 * thing as "already in auto mode".			 */			tlphy_auto(sc, 1);			break;		case IFM_10_2:		case IFM_10_5:			PHY_WRITE(&sc->sc_mii, MII_BMCR, 0);			PHY_WRITE(&sc->sc_mii, MII_TLPHY_CTRL, CTRL_AUISEL);			DELAY(100000);			break;		default:			PHY_WRITE(&sc->sc_mii, MII_TLPHY_CTRL, 0);			DELAY(100000);			mii_phy_set_media(&sc->sc_mii);			break;		}		break;	case MII_TICK:		/*		 * If we're not currently selected, just return.		 */		if (IFM_INST(ife->ifm_media) != sc->sc_mii.mii_inst)			return (0);		/*		 * Is the interface even up?		 */		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)			return (0);		/*		 * Only used for autonegotiation.		 */		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)			break;		/*		 * Check to see if we have link.  If we do, we don't		 * need to restart the autonegotiation process.  Read		 * the BMSR twice in case it's latched.		 *		 * XXX WHAT ABOUT CHECKING LINK ON THE BNC/AUI?!		 */		reg = PHY_READ(&sc->sc_mii, MII_BMSR) |		    PHY_READ(&sc->sc_mii, MII_BMSR);		if (reg & BMSR_LINK) {			sc->sc_mii.mii_ticks = 0;			break;		}		/*		 * Only retry autonegotiation every mii_anegticks seconds.		 */		if (++sc->sc_mii.mii_ticks <= sc->sc_mii.mii_anegticks)			return (0);		sc->sc_mii.mii_ticks = 0;		mii_phy_reset(&sc->sc_mii);//.........这里部分代码省略.........

voidplatform_mp_start_ap(void){	uint32_t reg, *src, *dst, cpu_num, div_val, cputype;	vm_offset_t pmu_boot_off;	/*	 * Initialization procedure depends on core revision,	 * in this step CHIP ID is checked to choose proper procedure	 */	cputype = cpu_ident();	cputype &= CPU_ID_CPU_MASK;	/*	 * Set the PA of CPU0 Boot Address Redirect register used in	 * mptramp according to the actual SoC registers' base address.	 */	pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT;	mptramp_pmu_boot = fdt_immr_pa + pmu_boot_off;	dst = pmap_mapdev(0xffff0000, PAGE_SIZE);	for (src = (uint32_t *)mptramp; src < (uint32_t *)mptramp_end;	    src++, dst++) {		*dst = *src;	}	pmap_unmapdev((vm_offset_t)dst, PAGE_SIZE);	if (cputype == CPU_ID_MV88SV584X_V7) {		/* Core rev A0 */		div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);		div_val &= 0x3f;		for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) {			reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);			reg &= CPU_DIVCLK_MASK(cpu_num);			reg |= div_val << (cpu_num * 8);			write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);		}	} else {		/* Core rev Z1 */		div_val = 0x01;		if (mp_ncpus > 1) {			reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0);			reg &= CPU_DIVCLK_MASK(3);			reg |= div_val << 24;			write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg);		}		for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) {			reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);			reg &= CPU_DIVCLK_MASK(cpu_num);			reg |= div_val << (cpu_num * 8);			write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);		}	}	reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);	reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21;	write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);	reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);	reg |= 0x01000000;	write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);	DELAY(100);	reg &= ~(0xf << 21);	write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);	DELAY(100);	bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0);	for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )		bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT,		    pmap_kextract((vm_offset_t)mpentry));	dcache_wbinv_poc_all();	for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )		bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0);	/* XXX: Temporary workaround for hangup after releasing AP's */	wmb();	DELAY(10);	armadaxp_init_coher_fabric();}

static inline voidcs4281_wr(struct sc_info *sc, int regno, u_int32_t data){    bus_space_write_4(sc->st, sc->sh, regno, data);    DELAY(100);}

intI810WaitLpRing(ScrnInfoPtr pScrn, int n, int timeout_millis){   I810Ptr pI810 = I810PTR(pScrn);   I810RingBuffer *ring = &(pI810->LpRing);   int iters = 0;   int start = 0;   int now = 0;   int last_head = 0;   int first = 0;   /* If your system hasn't moved the head pointer in 2 seconds, I'm going to    * call it crashed.    */   if (timeout_millis == 0)      timeout_millis = 2000;   if (I810_DEBUG & DEBUG_VERBOSE_ACCEL) {      ErrorF("I810WaitLpRing %d/n", n);      first = GetTimeInMillis();   }   while (ring->space < n) {      ring->head = INREG(LP_RING + RING_HEAD) & HEAD_ADDR;      ring->space = ring->head - (ring->tail + 8);      if (ring->space < 0)	 ring->space += ring->mem.Size;      iters++;      now = GetTimeInMillis();      if (start == 0 || now < start || ring->head != last_head) {	 if (I810_DEBUG & DEBUG_VERBOSE_ACCEL)	    if (now > start)	       ErrorF("space: %d wanted %d/n", ring->space, n);	 start = now;	 last_head = ring->head;      } else if (now - start > timeout_millis) {	 ErrorF("Error in I810WaitLpRing(), now is %d, start is %d/n", now,		start);	 I810PrintErrorState(pScrn);	 ErrorF("space: %d wanted %d/n", ring->space, n);#ifdef XF86DRI	 if (pI810->directRenderingEnabled) {	    DRIUnlock(screenInfo.screens[pScrn->scrnIndex]);	    DRICloseScreen(screenInfo.screens[pScrn->scrnIndex]);	 }#endif	 pI810->AccelInfoRec = NULL;	/* Stops recursive behavior */	 FatalError("lockup/n");      }      DELAY(10000);   }   if (I810_DEBUG & DEBUG_VERBOSE_ACCEL) {      now = GetTimeInMillis();      if (now - first) {	 ErrorF("Elapsed %d ms/n", now - first);	 ErrorF("space: %d wanted %d/n", ring->space, n);      }   }   return iters;}

voidmc_attach(struct device *parent, struct device *self, void *aux){	struct confargs *ca = aux;	struct mc_softc *sc = (struct mc_softc *)self;	struct ifnet *ifp = &sc->sc_arpcom.ac_if;	u_int8_t lladdr[ETHER_ADDR_LEN];	int nseg, error;	if (OF_getprop(ca->ca_node, "local-mac-address", lladdr,	    ETHER_ADDR_LEN) != ETHER_ADDR_LEN) {		printf(": failed to get MAC address./n");		return;	}	ca->ca_reg[0] += ca->ca_baseaddr;	ca->ca_reg[2] += ca->ca_baseaddr;	ca->ca_reg[4] += ca->ca_baseaddr;	if ((sc->sc_reg = mapiodev(ca->ca_reg[0], ca->ca_reg[1])) == NULL) {		printf(": cannot map registers/n");		return;	}	sc->sc_dmat = ca->ca_dmat;	sc->sc_tail = 0;	if ((sc->sc_txdma = mapiodev(ca->ca_reg[2], ca->ca_reg[3])) == NULL) {		printf(": cannot map TX DMA registers/n");		goto notxdma;	}	if ((sc->sc_rxdma = mapiodev(ca->ca_reg[4], ca->ca_reg[5])) == NULL) {		printf(": cannot map RX DMA registers/n");		goto norxdma;	}	if ((sc->sc_txdbdma = dbdma_alloc(sc->sc_dmat, 2)) == NULL) {		printf(": cannot alloc TX DMA descriptors/n");		goto notxdbdma;	}	sc->sc_txdmacmd = sc->sc_txdbdma->d_addr;	if ((sc->sc_rxdbdma = dbdma_alloc(sc->sc_dmat, 8 + 1)) == NULL) {		printf(": cannot alloc RX DMA descriptors/n");		goto norxdbdma;	}	sc->sc_rxdmacmd = sc->sc_rxdbdma->d_addr;	if ((error = bus_dmamem_alloc(sc->sc_dmat, MACE_BUFSZ, PAGE_SIZE, 0,	    sc->sc_bufseg, 1, &nseg, BUS_DMA_NOWAIT))) {		printf(": cannot allocate DMA mem (%d)/n", error);		goto nodmamem;	}	if ((error = bus_dmamem_map(sc->sc_dmat, sc->sc_bufseg, nseg,	    MACE_BUFSZ, &sc->sc_txbuf, BUS_DMA_NOWAIT))) {		printf(": cannot map DMA mem (%d)/n", error);		goto nodmamap;	}	if ((error = bus_dmamap_create(sc->sc_dmat, MACE_BUFSZ, 1, MACE_BUFSZ,	    0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_bufmap))) {		printf(": cannot create DMA map (%d)/n", error);		goto nodmacreate;	}	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_bufmap, sc->sc_txbuf,	    MACE_BUFSZ, NULL, BUS_DMA_NOWAIT))) {		printf(": cannot load DMA map (%d)/n", error);		goto nodmaload;	}	sc->sc_txbuf_pa = sc->sc_bufmap->dm_segs->ds_addr;	sc->sc_rxbuf = sc->sc_txbuf + MACE_BUFLEN * MACE_TXBUFS;	sc->sc_rxbuf_pa = sc->sc_txbuf_pa + MACE_BUFLEN * MACE_TXBUFS;	printf(": irq %d,%d,%d", ca->ca_intr[0], ca->ca_intr[1],	    ca->ca_intr[2]);	/* disable receive DMA */	dbdma_reset(sc->sc_rxdma);	/* disable transmit DMA */	dbdma_reset(sc->sc_txdma);	/* install interrupt handlers */	mac_intr_establish(parent, ca->ca_intr[2], IST_LEVEL, IPL_NET,	    mc_dmaintr, sc, sc->sc_dev.dv_xname);	mac_intr_establish(parent, ca->ca_intr[0],  IST_LEVEL, IPL_NET,	    mc_intr, sc, sc->sc_dev.dv_xname);	sc->sc_biucc = XMTSP_64;	sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU |	    XMTBRST | RCVBRST;	sc->sc_plscc = PORTSEL_GPSI | ENPLSIO;	/* reset the chip and disable all interrupts */	NIC_PUT(sc, MACE_BIUCC, SWRST);	DELAY(100);	NIC_PUT(sc, MACE_IMR, ~0);//.........这里部分代码省略.........

/** * Distribute @p clock on backplane. *  * @param sc Driver instance state. * @param clock Clock to enable. *  * @retval 0 success * @retval ENODEV If @p clock is unsupported, or if the device does not * 		  support dynamic clock control. */intbhnd_pwrctl_setclk(struct bhnd_pwrctl_softc *sc, bhnd_clock clock){	uint32_t	scc;	PWRCTL_LOCK_ASSERT(sc, MA_OWNED);	/* Is dynamic clock control supported? */	if (PWRCTL_QUIRK(sc, FIXED_CLK))		return (ENODEV);	/* Chips with ccrev 10 are EOL and they don't have SYCC_HR used below */	if (bhnd_get_hwrev(sc->chipc_dev) == 10)		return (ENODEV);	scc = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL);	switch (clock) {	case BHND_CLOCK_HT:		/* fast (pll) clock */		if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) {			scc &= ~(CHIPC_SCC_XC | CHIPC_SCC_FS | CHIPC_SCC_IP);			scc |= CHIPC_SCC_IP;			/* force xtal back on before clearing SCC_DYN_XTAL.. */			bhnd_pwrctl_ungate_clock(sc->chipc_dev, BHND_CLOCK_HT);		} else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) {			scc |= CHIPC_SYCC_HR;		} else {			return (ENODEV);		}		bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc);		DELAY(CHIPC_PLL_DELAY);		break;			case BHND_CLOCK_DYN:		/* enable dynamic clock control */		if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) {			scc &= ~(CHIPC_SCC_FS | CHIPC_SCC_IP | CHIPC_SCC_XC);			if ((scc & CHIPC_SCC_SS_MASK) != CHIPC_SCC_SS_XTAL)				scc |= CHIPC_SCC_XC;				bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc);			/* for dynamic control, we have to release our xtal_pu			 * "force on" */			if (scc & CHIPC_SCC_XC) {				bhnd_pwrctl_gate_clock(sc->chipc_dev,				    BHND_CLOCK_HT);			}		} else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) {			/* Instaclock */			scc &= ~CHIPC_SYCC_HR;			bhnd_bus_write_4(sc->res, CHIPC_SYS_CLK_CTL, scc);		} else {			return (ENODEV);		}		break;	default:		return (ENODEV);	}	return (0);}

static intimx_ata_ch_attach(device_t dev){	struct ata_pci_controller *ctrl;	struct ata_channel *ch;	int i;	ctrl = device_get_softc(device_get_parent(dev));	ch = device_get_softc(dev);	for (i = ATA_DATA; i < ATA_MAX_RES; i++)		ch->r_io[i].res = ctrl->r_res1;	bus_write_2(ctrl->r_res1, 0x24, 0x80);	DELAY(100);	bus_write_2(ctrl->r_res1, 0x24, 0xc0);	DELAY(100);	/* Write TIME_OFF/ON/1/2W */	bus_write_1(ctrl->r_res1, 0x00, 3);	bus_write_1(ctrl->r_res1, 0x01, 3);	bus_write_1(ctrl->r_res1, 0x02, (25 + 15) / 15);	bus_write_1(ctrl->r_res1, 0x03, (70 + 15) / 15);	/* Write TIME_2R/AX/RDX/4 */	bus_write_1(ctrl->r_res1, 0x04, (70 + 15) / 15);	bus_write_1(ctrl->r_res1, 0x05, (50 + 15) / 15 + 2);	bus_write_1(ctrl->r_res1, 0x06, 1);	bus_write_1(ctrl->r_res1, 0x07, (10 + 15) / 15);	/* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */	bus_write_1(ctrl->r_res1, 0x08, (10 + 15) / 15);	bus_write_2(ctrl->r_res1, 0x24, 0xc1);	DELAY(30000);	/* setup ATA registers */	ch->r_io[ATA_DATA   ].offset = 0xa0;	ch->r_io[ATA_FEATURE].offset = 0xa4;	ch->r_io[ATA_ERROR  ].offset = 0xa4;	ch->r_io[ATA_COUNT  ].offset = 0xa8;	ch->r_io[ATA_SECTOR ].offset = 0xac;	ch->r_io[ATA_CYL_LSB].offset = 0xb0;	ch->r_io[ATA_CYL_MSB].offset = 0xb4;	ch->r_io[ATA_DRIVE  ].offset = 0xb8;	ch->r_io[ATA_COMMAND].offset = 0xbc;	ch->r_io[ATA_STATUS ].offset = 0xbc;	ch->r_io[ATA_ALTSTAT].offset = 0xd8;	ch->r_io[ATA_CONTROL].offset = 0xd8;	ata_pci_hw(dev);	ch->flags |= ATA_NO_SLAVE;	ch->flags |= ATA_USE_16BIT;	ch->flags |= ATA_CHECKS_CABLE;	ch->flags |= ATA_KNOWN_PRESENCE;	/* Clear pending interrupts. */	bus_write_2(ctrl->r_res1, 0x28, 0xf8);	/* Enable all, but Idle interrupts. */	bus_write_2(ctrl->r_res1, 0x2c, 0x88);	return 0;}

voidehci_arbus_attach(device_t parent, device_t self, void *aux){	ehci_softc_t *sc = device_private(self);	struct arbus_attach_args * const aa = aux;	void *ih = NULL;	int error;	sc->iot = aa->aa_bst_le;	sc->sc_size = aa->aa_size;	//sc->sc_bus.ub_hcpriv = sc;	sc->sc_bus.ub_dmatag = aa->aa_dmat;	sc->sc_bus.ub_revision = USBREV_1_0;	sc->sc_flags |= EHCIF_ETTF;	sc->sc_vendor_init = ehci_arbus_init;	error = bus_space_map(aa->aa_bst, aa->aa_addr, aa->aa_size, 0,	    &sc->ioh);	if (error) {		aprint_error(": failed to map registers: %d/n", error);		return;	}	/* The recommended value is 0x20 for both ports and the host */	REGVAL(AR9344_USB_CONFIG_BASE) = 0x20c00;	/* magic */	DELAY(1000);	/* get offset to operational regs */	uint32_t r = bus_space_read_4(aa->aa_bst, sc->ioh, 0);	if (r != 0x40) {		aprint_error(": error: CAPLENGTH (%#x) != 0x40/n", sc->sc_offs);		return;	}	sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);	aprint_normal("/n");	/* Disable EHCI interrupts */	EOWRITE4(sc, EHCI_USBINTR, 0);	/* establish interrupt */	ih = arbus_intr_establish(aa->aa_cirq, aa->aa_mirq, ehci_intr, sc);	if (ih == NULL)		panic("%s: couldn't establish interrupt",		    device_xname(self));	/*	 * There are no companion controllers	 */	sc->sc_ncomp = 0;	error = ehci_init(sc);	if (error) {		aprint_error("%s: init failed, error=%d/n", device_xname(self),		    error);		if (ih != NULL)			arbus_intr_disestablish(ih);		return;	}	/* Attach USB device */	sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint);}

intlk201_init(struct lk201_state *lks){	int i;	lks->waitack = 0;	send(lks, LK_LED_ENABLE);	send(lks, LK_LED_ALL);	/*	 * set all keys to updown mode; autorepeat is	 * done by wskbd software	 */	for (i = 1; i <= 14; i++)		send(lks, LK_CMD_MODE(LK_UPDOWN, i));	send(lks, LK_CL_ENABLE);	send(lks, LK_PARAM_VOLUME(3));	lks->kcvol = (8 - 3) * 100 / 8;	lks->bellvol = -1; /* not yet set */	for (i = 0; i < LK_KLL; i++)		lks->down_keys_list[i] = -1;	send(lks, LK_KBD_ENABLE);	send(lks, LK_LED_DISABLE);	send(lks, LK_LED_ALL);	lks->leds_state = 0;	/*	 * Swallow all the keyboard acknowledges from lk201_init().	 * There should be 14 of them - one per LK_CMD_MODE command.	 */	for(;;) {		lks->waitack = 1;		for (i = 100; i != 0; i--) {			DELAY(1000);			if (lks->waitack == 0)				break;		}		if (i == 0)			break;	}	/*	 * Try to set the keyboard in LK-401 mode.	 * If we receive an error, this is an LK-201 keyboard.	 */	lks->waitack = 1;	send(lks, LK_ENABLE_401);	for (i = 100; i != 0; i--) {		DELAY(1000);		if (lks->waitack == 0)			break;	}	if (lks->waitack != 0)		lks->kbdtype = KBD_NONE;	else {		if (lks->ackdata == LK_INPUT_ERROR)			lks->kbdtype = KBD_LK201;		else			lks->kbdtype = KBD_LK401;	}	lks->waitack = 0;	printf("lkkbd0: %s/n", lkkbd_descr[lks->kbdtype]);	return 0;}

voidpchbattach(struct device *parent, struct device *self, void *aux){	struct pchb_softc *sc = (struct pchb_softc *)self;	struct pci_attach_args *pa = aux;	struct pcibus_attach_args pba;	pcireg_t bcreg, bir;	u_char pbnum;	pcitag_t tag;	int i, r;	int doattach = 0;	switch (PCI_VENDOR(pa->pa_id)) {	case PCI_VENDOR_AMD:		printf("/n");		switch (PCI_PRODUCT(pa->pa_id)) {		case PCI_PRODUCT_AMD_AMD64_0F_HT:		case PCI_PRODUCT_AMD_AMD64_10_HT:			for (i = 0; i < AMD64HT_NUM_LDT; i++)				pchb_amd64ht_attach(self, pa, i);			break;		}		break;	case PCI_VENDOR_INTEL:		switch (PCI_PRODUCT(pa->pa_id)) {		case PCI_PRODUCT_INTEL_82915G_HB:		case PCI_PRODUCT_INTEL_82945G_HB:		case PCI_PRODUCT_INTEL_82925X_HB:		case PCI_PRODUCT_INTEL_82955X_HB:			sc->sc_bt = pa->pa_memt;			if (bus_space_map(sc->sc_bt, I82802_IOBASE,			    I82802_IOSIZE, 0, &sc->sc_bh))				break;			/* probe and init rng */			if (!(bus_space_read_1(sc->sc_bt, sc->sc_bh,			    I82802_RNG_HWST) & I82802_RNG_HWST_PRESENT))				break;			/* enable RNG */			bus_space_write_1(sc->sc_bt, sc->sc_bh,			    I82802_RNG_HWST,			    bus_space_read_1(sc->sc_bt, sc->sc_bh,			    I82802_RNG_HWST) | I82802_RNG_HWST_ENABLE);			/* see if we can read anything */			for (i = 1000; i-- &&			    !(bus_space_read_1(sc->sc_bt, sc->sc_bh,			    I82802_RNG_RNGST) & I82802_RNG_RNGST_DATAV); )				DELAY(10);			if (!(bus_space_read_1(sc->sc_bt, sc->sc_bh,			    I82802_RNG_RNGST) & I82802_RNG_RNGST_DATAV))				break;			r = bus_space_read_1(sc->sc_bt, sc->sc_bh,			    I82802_RNG_DATA);			timeout_set(&sc->sc_rng_to, pchb_rnd, sc);			sc->sc_rng_i = 4;			pchb_rnd(sc);			sc->sc_rng_active = 1;			break;		}		printf("/n");		break;	case PCI_VENDOR_VIATECH:		switch (PCI_PRODUCT(pa->pa_id)) {		case PCI_PRODUCT_VIATECH_VT8251_PCIE_0:			/*			 * Bump the host bridge into PCI-PCI bridge			 * mode by clearing magic bit on the VLINK			 * device.  This allows us to read the bus			 * number for the PCI bus attached to this			 * host bridge.			 */			tag = pci_make_tag(pa->pa_pc, 0, 17, 7);			bcreg = pci_conf_read(pa->pa_pc, tag, 0xfc);			bcreg &= ~0x00000004; /* XXX Magic */			pci_conf_write(pa->pa_pc, tag, 0xfc, bcreg);			bir = pci_conf_read(pa->pa_pc,			    pa->pa_tag, PPB_REG_BUSINFO);			pbnum = PPB_BUSINFO_PRIMARY(bir);			if (pbnum > 0)				doattach = 1;			/* Switch back to host bridge mode. */			bcreg |= 0x00000004; /* XXX Magic */			pci_conf_write(pa->pa_pc, tag, 0xfc, bcreg);			break;		}		printf("/n");		break;	default:		printf("/n");		break;	}#if NAGP > 0//.........这里部分代码省略.........

static uint8_t programMode(){    int i = 0;    char confirm[3];    DELAY(API_DELAY);    DELAY(API_DELAY);    UART_putString(xbeeUartId, "+++", 3);    DELAY(API_DELAY);    //wait for "OK/r"    do {        confirm[i] = UART_getChar(xbeeUartId);        if (confirm[i] != 0)            i++;    } while(i < 3);    if (!(confirm[0] == 0x4F && confirm[1] == 0x4B && confirm[2] == 0x0D)){        return FAILURE;    }    DELAY(API_DELAY);    UART_putString(xbeeUartId, "ATRE/r", 5);// Resets to Factory settings    DELAY(API_DELAY);    UART_putString(xbeeUartId, "ATCH15/r", 7);    DELAY(API_DELAY);    UART_putString(xbeeUartId, "ATDH0/r", 6);    DELAY(API_DELAY);    #ifdef UNICAST_MSG    #ifdef IS_COMPAS    UART_putString(xbeeUartId, "ATDLAAC3/r", 9);    DELAY(API_DELAY);    UART_putString(xbeeUartId, "ATMYBC64/r", 9);    #else    UART_putString(xbeeUartId, "ATDLBC64/r", 9);    DELAY(API_DELAY);    UART_putString(xbeeUartId, "ATMYAAC3/r", 9);    #endif    DELAY(API_DELAY);    #endif    UART_putString(xbeeUartId, "ATWR/r", 5);//Writes the command to memory    DELAY(API_DELAY);    UART_putString(xbeeUartId, "ATCN/r", 5);//Leave the menu.    return SUCCESS;}

static voiddec_eb164_cons_init(){	struct ctb *ctb;	struct cia_config *ccp;	extern struct cia_config cia_configuration;	ccp = &cia_configuration;	cia_init(ccp, 0);	ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);	switch (ctb->ctb_term_type) {	case CTB_PRINTERPORT: 		/* serial console ... */		/* XXX */		{			/*			 * Delay to allow PROM putchars to complete.			 * FIFO depth * character time,			 * character time = (1000000 / (defaultrate / 10))			 */			DELAY(160000000 / comcnrate);			if(comcnattach(&ccp->cc_iot, 0x3f8, comcnrate,			    COM_FREQ,			    (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8))				panic("can't init serial console");			break;		}	case CTB_GRAPHICS:#if NPCKBD > 0		/* display console ... */		/* XXX */		(void) pckbc_cnattach(&ccp->cc_iot, IO_KBD, KBCMDP,		    PCKBC_KBD_SLOT, 0);		/*		 * On at least LX164, SRM reports an isa video board		 * as a pci slot with 0xff as the bus and slot numbers.		 * Since these values are not plausible from a pci point		 * of view, it is safe to check for them.		 */		if (CTB_TURBOSLOT_TYPE(ctb->ctb_turboslot) ==		    CTB_TURBOSLOT_TYPE_ISA ||		    (CTB_TURBOSLOT_BUS(ctb->ctb_turboslot) == 0xff &&		     CTB_TURBOSLOT_SLOT(ctb->ctb_turboslot) == 0xff))			isa_display_console(&ccp->cc_iot, &ccp->cc_memt);		else			pci_display_console(&ccp->cc_iot, &ccp->cc_memt,			    &ccp->cc_pc, CTB_TURBOSLOT_BUS(ctb->ctb_turboslot),			    CTB_TURBOSLOT_SLOT(ctb->ctb_turboslot), 0);#else		panic("not configured to use display && keyboard console");#endif		break;	default:		printf("ctb->ctb_term_type = 0x%lx/n", ctb->ctb_term_type);		printf("ctb->ctb_turboslot = 0x%lx/n", ctb->ctb_turboslot);		panic("consinit: unknown console type %ld",		    ctb->ctb_term_type);	}}

static intiavc_isa_probe(device_t dev){	struct iavc_softc *sc;	int ret = ENXIO;	int unit = device_get_unit(dev);		if(isa_get_vendorid(dev))	/* no PnP probes here */		return ENXIO;	/* check max unit range */		if (unit >= IAVC_MAXUNIT)	{		kprintf("iavc%d: too many units/n", unit);		return(ENXIO);		}	sc = iavc_find_sc(unit);	/* get softc */			sc->sc_unit = unit;	if (!(sc->sc_resources.io_base[0] =		bus_alloc_resource(dev, SYS_RES_IOPORT,			&sc->sc_resources.io_rid[0],			0UL, ~0UL, B1_IOLENGTH, RF_ACTIVE)))	{		kprintf("iavc%d: can't allocate io region/n", unit);		return(ENXIO);                                       	}	sc->sc_iobase = rman_get_start(sc->sc_resources.io_base[0]);	switch(sc->sc_iobase)	{		case 0x150:		case 0x250:		case 0x300:		case 0x340:			break;		default:			kprintf("iavc%d: ERROR, invalid i/o base addr 0x%x configured!/n", sc->sc_unit, sc->sc_iobase);			bus_release_resource(dev, SYS_RES_IOPORT,					sc->sc_resources.io_rid[0],		                        sc->sc_resources.io_base[0]);		return(ENXIO);	}			sc->sc_io_bt = rman_get_bustag(sc->sc_resources.io_base[0]);	sc->sc_io_bh = rman_get_bushandle(sc->sc_resources.io_base[0]);	/* setup characteristics */	sc->sc_t1 = FALSE;	sc->sc_dma = FALSE;	sc->sc_capi.card_type = CARD_TYPEC_AVM_B1_ISA;	sc->sc_capi.sc_nbch = 2;	b1_reset(sc);	DELAY(100);	ret = b1_detect(sc);	if(ret)	{		kprintf("iavc%d: no card ? b1_detect returns %0x02x/n", sc->sc_unit, ret);		return(ENXIO);	}	DELAY(100);	b1_reset(sc);		DELAY(100);	if(bootverbose)	{		kprintf("iavc%d: class = 0x%02x, rev = 0x%02x/n", sc->sc_unit,			iavc_read_port(sc, B1_ANALYSE),			iavc_read_port(sc, B1_REVISION));	}	device_set_desc(dev, "AVM B1 ISA");	return(0);}

static intdotg_obio_attach(device_t dev){	struct dotg_obio_softc *sc = device_get_softc(dev);	int err;	/* setup controller interface softc */	/* initialise some bus fields */	sc->sc_dci.sc_dev = dev;	sc->sc_dci.sc_bus.parent = dev;	sc->sc_dci.sc_bus.devices = sc->sc_dci.sc_devices;	sc->sc_dci.sc_bus.devices_max = DOTG_MAX_DEVICES;	/* get all DMA memory */	if (usb_bus_mem_alloc_all(&sc->sc_dci.sc_bus,	    USB_GET_DMA_TAG(dev), NULL)) {		printf("No mem/n");		return (ENOMEM);	}	sc->sc_dci.sc_mem_rid = 0;	sc->sc_dci.sc_mem_res =	    bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_dci.sc_irq_rid,			       RF_ACTIVE);	if (!(sc->sc_dci.sc_mem_res)) {		printf("Can`t alloc MEM/n");		goto error;	}	sc->sc_dci.sc_bst = rman_get_bustag(sc->sc_dci.sc_mem_res);	sc->sc_dci.sc_bsh = rman_get_bushandle(sc->sc_dci.sc_mem_res);	sc->sc_dci.sc_irq_rid = 0;	sc->sc_dci.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 	    &sc->sc_dci.sc_irq_rid, RF_SHAREABLE| RF_ACTIVE);	if (!(sc->sc_dci.sc_irq_res)) {		printf("Can`t alloc IRQ/n");		goto error;	}	sc->sc_dci.sc_bus.bdev = device_add_child(dev, "usbus", -1);	if (!(sc->sc_dci.sc_bus.bdev)) {		printf("Can`t add usbus/n");		goto error;	}	device_set_ivars(sc->sc_dci.sc_bus.bdev, &sc->sc_dci.sc_bus);#if (__FreeBSD_version >= 700031)	err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res,	    INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)dotg_interrupt,	    sc, &sc->sc_dci.sc_intr_hdl);#else	err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res,	    INTR_TYPE_BIO | INTR_MPSAFE, (driver_intr_t *)dotg_interrupt,	    sc, &sc->sc_dci.sc_intr_hdl);#endif	if (err) {		sc->sc_dci.sc_intr_hdl = NULL;		printf("Can`t set IRQ handle/n");		goto error;	}	/* Run clock for OTG core */	rt305x_sysctl_set(SYSCTL_CLKCFG1, rt305x_sysctl_get(SYSCTL_CLKCFG1) | 	    SYSCTL_CLKCFG1_OTG_CLK_EN);	rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_OTG);	DELAY(100);	err = dotg_init(&sc->sc_dci);	if (err) printf("dotg_init fail/n");	if (!err) {		err = device_probe_and_attach(sc->sc_dci.sc_bus.bdev);		if (err) printf("device_probe_and_attach fail/n");	}	if (err) {		goto error;	}	return (0);error:	dotg_obio_detach(dev);	return (ENXIO);}

voidcomattach(struct device *parent, struct device *dev, void *aux){	struct com_softc *sc = (struct com_softc *)dev;	int iobase = (int)&IODEVbase->psx16550;#ifdef COM_HAYESP	int	hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 };	int	*hayespp;#endif	com_attached = 1;	callout_init(&sc->sc_diag_ch, 0);	callout_init(&com_poll_ch, 0);	sc->sc_iobase = iobase;	sc->sc_hwflags = 0;	sc->sc_swflags = 0;	printf(": iobase %x", sc->sc_iobase);#ifdef COM_HAYESP	/* Look for a Hayes ESP board. */	for (hayespp = hayesp_ports; *hayespp != 0; hayespp++)		if (comprobeHAYESP(*hayespp, sc)) {			sc->sc_hayespbase = *hayespp;			break;		}	/* No ESP; look for other things. */	if (*hayespp == 0) {#endif	/* look for a NS 16550AF UART with FIFOs */	outb(pio(iobase , com_fifo),	    FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);	DELAY(100);	if (ISSET(inb(pio(iobase , com_iir)), IIR_FIFO_MASK) == IIR_FIFO_MASK)		if (ISSET(inb(pio(iobase , com_fifo)), FIFO_TRIGGER_14) == FIFO_TRIGGER_14) {			SET(sc->sc_hwflags, COM_HW_FIFO);			printf(": ns16550a, working fifo/n");		} else			printf(": ns16550, broken fifo/n");	else		printf(": ns8250 or ns16450, no fifo/n");	outb(pio(iobase , com_fifo), 0);#ifdef COM_HAYESP	}#endif	/* disable interrupts */	outb(pio(iobase , com_ier), 0);	outb(pio(iobase , com_mcr), 0);	if (sc->sc_iobase == CONADDR) {		/*		 * Need to reset baud rate, etc. of next print so reset		 * comconsinit.  Also make sure console is always "hardwired".		 */		comconsinit = 0;		SET(sc->sc_hwflags, COM_HW_CONSOLE);		SET(sc->sc_swflags, COM_SW_SOFTCAR);	}}

/* * Probe and vendor-specific initialization routine for SIC boards */inted_probe_SIC(device_t dev, int port_rid, int flags){	struct ed_softc *sc = device_get_softc(dev);	int	error;	int	i;	u_int	memsize;	u_long	pmem;	u_char	sum;	error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS);	if (error)		return (error);	sc->asic_offset = ED_SIC_ASIC_OFFSET;	sc->nic_offset  = ED_SIC_NIC_OFFSET;	memsize = 16384;	/* XXX Needs to allow different msize */	error = ed_alloc_memory(dev, 0, memsize);	if (error)		return (error);	sc->mem_start = 0;	sc->mem_size  = memsize;	pmem = rman_get_start(sc->mem_res);	error = ed_isa_mem_ok(dev, pmem, memsize);	if (error)		return (error);	/* Reset card to force it into a known state. */	ed_asic_outb(sc, 0, 0x00);	DELAY(100);	/*	 * Here we check the card ROM, if the checksum passes, and the	 * type code and ethernet address check out, then we know we have	 * an SIC card.	 */	ed_asic_outb(sc, 0, 0x81);	DELAY(100);	sum = bus_space_read_1(sc->mem_bst, sc->mem_bsh, 6);	for (i = 0; i < ETHER_ADDR_LEN; i++)		sum ^= (sc->enaddr[i] =		    bus_space_read_1(sc->mem_bst, sc->mem_bsh, i));#ifdef ED_DEBUG	device_printf(dev, "ed_probe_sic: got address %6D/n",	    sc->enaddr, ":");#endif	if (sum != 0)		return (ENXIO);	if ((sc->enaddr[0] | sc->enaddr[1] | sc->enaddr[2]) == 0)		return (ENXIO);	sc->vendor   = ED_VENDOR_SIC;	sc->type_str = "SIC";	sc->isa16bit = 0;	sc->cr_proto = 0;	/*	 * SIC RAM page 0x0000-0x3fff(or 0x7fff)	 */	ed_asic_outb(sc, 0, 0x80);	DELAY(100);	error = ed_clear_memory(dev);	if (error)		return (error);	sc->mem_shared = 1;	sc->mem_end = sc->mem_start + sc->mem_size;	/*	 * allocate one xmit buffer if < 16k, two buffers otherwise	 */	if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))		sc->txb_cnt = 1;	else		sc->txb_cnt = 2;	sc->tx_page_start = 0;	sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt;	sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE;	sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;	sc->sc_write_mbufs = ed_shmem_write_mbufs;	return (0);}

voidahci_os_hardsleep(int us){	DELAY(us);}

static voidbrgphy_reset(struct mii_softc *sc){	struct bge_softc *bge_sc = NULL;	struct bce_softc *bce_sc = NULL;	struct ifnet *ifp;	int i, val;	/*	 * Perform a reset.  Note that at least some Broadcom PHYs default to	 * being powered down as well as isolated after a reset but don't work	 * if one or both of these bits are cleared.  However, they just work	 * fine if both bits remain set, so we don't use mii_phy_reset() here.	 */	PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);	/* Wait 100ms for it to complete. */	for (i = 0; i < 100; i++) {		if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)			break;		DELAY(1000);	}	/* Handle any PHY specific procedures following the reset. */	switch (sc->mii_mpd_oui) {	case MII_OUI_BROADCOM:		switch (sc->mii_mpd_model) {		case MII_MODEL_BROADCOM_BCM5400:			bcm5401_load_dspcode(sc);			break;		case MII_MODEL_BROADCOM_BCM5401:			if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)				bcm5401_load_dspcode(sc);			break;		case MII_MODEL_BROADCOM_BCM5411:			bcm5411_load_dspcode(sc);			break;		case MII_MODEL_BROADCOM_BCM54K2:			bcm54k2_load_dspcode(sc);			break;		}		break;	}	ifp = sc->mii_pdata->mii_ifp;	/* Find the driver associated with this PHY. */	if (strcmp(ifp->if_dname, "bge") == 0)	{		bge_sc = ifp->if_softc;	} else if (strcmp(ifp->if_dname, "bce") == 0) {		bce_sc = ifp->if_softc;	}	if (bge_sc) {		/* Fix up various bugs */		if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)			brgphy_fixup_5704_a0_bug(sc);		if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)			brgphy_fixup_adc_bug(sc);		if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)			brgphy_fixup_adjust_trim(sc);		if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)			brgphy_fixup_ber_bug(sc);		if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)			brgphy_fixup_crc_bug(sc);		if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)			brgphy_fixup_jitter_bug(sc);		brgphy_jumbo_settings(sc, ifp->if_mtu);		if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)			brgphy_ethernet_wirespeed(sc);		/* Enable Link LED on Dell boxes */		if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {			PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,			    PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &			    ~BRGPHY_PHY_EXTCTL_3_LED);		}		/* Adjust output voltage (From Linux driver) */		if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)			PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);	} else if (bce_sc) {		if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&			(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {			/* Store autoneg capabilities/results in digital block (Page 0) */			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);			PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,				BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);			/* Enable fiber mode and autodetection */			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,				PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |				BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |				BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);			/* Enable parallel detection *///.........这里部分代码省略.........

/*---------------------------------------------------------------------------* *	execute a layer 1 command *---------------------------------------------------------------------------*/	voidifpi2_isacsx_l1_cmd(struct l1_softc *sc, int command){	u_char cmd;#ifdef I4B_SMP_WORKAROUND	/* XXXXXXXXXXXXXXXXXXX */		/*	 * patch from Wolfgang Helbig:	 *	 * Here is a patch that makes i4b work on an SMP:	 * The card (TELES 16.3) didn't interrupt on an SMP machine.	 * This is a gross workaround, but anyway it works *and* provides	 * some information as how to finally fix this problem.	 */		HSCX_WRITE(0, H_MASK, 0xff);	HSCX_WRITE(1, H_MASK, 0xff);	ISAC_WRITE(I_MASKD, 0xff);	ISAC_WRITE(I_MASK, 0xff);	DELAY(100);	HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);	HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);	ISAC_WRITE(I_MASKD, isacsx_imaskd);	ISAC_WRITE(I_MASK, isacsx_imask);	/* XXXXXXXXXXXXXXXXXXX */	#endif /* I4B_SMP_WORKAROUND */	if(command < 0 || command > CMD_ILL)	{		NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, ifpi2_printstate(sc));		return;	}                                           	cmd = ISACSX_CIX0_LOW;	switch(command)	{		case CMD_TIM:			NDBGL1(L1_I_CICO, "tx TIM in state %s", ifpi2_printstate(sc));			cmd |= (ISACSX_CIX0_CTIM << 4);			break;		case CMD_RS:			NDBGL1(L1_I_CICO, "tx RS in state %s", ifpi2_printstate(sc));			cmd |= (ISACSX_CIX0_CRS << 4);			break;		case CMD_AR8:			NDBGL1(L1_I_CICO, "tx AR8 in state %s", ifpi2_printstate(sc));			cmd |= (ISACSX_CIX0_CAR8 << 4);			break;		case CMD_AR10:			NDBGL1(L1_I_CICO, "tx AR10 in state %s", ifpi2_printstate(sc));			cmd |= (ISACSX_CIX0_CAR10 << 4);			break;		case CMD_DIU:			NDBGL1(L1_I_CICO, "tx DIU in state %s", ifpi2_printstate(sc));			cmd |= (ISACSX_CIX0_CDIU << 4);			break;	}	ISAC_WRITE(I_CIX0, cmd);}

static voidmmc_ms_delay(int ms){	DELAY(1000 * ms);	/* XXX BAD */}

//.........这里部分代码省略.........          {            *diagsArea << DgSqlCode(-2034) << DgInt0(201)                       << DgString0("I say") << DgString1("control broker");          }          if (diagsArea->contains(-8921))          {            // Should not get timeout error 8921. Get a core-file            // of the SSMP and this process too so that this can be            // debugged.            cbServer_->getControlConnection()->              dumpAndStopOtherEnd(true, false);            genLinuxCorefile("Unexpected timeout error");          }          reportError(diagsArea);          step_ = DONE;          break;        }        // See if stream has the reply yet.        if (!cancelStream_->moreObjects())          return WORK_OK; #pragma warning (disable : 4291)        ControlQueryReply *reply = new (cliGlobals->getIpcHeap())               ControlQueryReply(INVALID_RTS_HANDLE, cliGlobals->getIpcHeap());#pragma warning (default : 4291)        *cancelStream_ >> *reply;        if (reply->didAttemptControl())        {          // yeaah!          cancelStream_->clearAllObjects();        }        else        {          if (cancelStream_->moreObjects() &&              cancelStream_->getNextObjType() == IPC_SQL_DIAG_AREA)          {            ComDiagsArea *diagsArea =               ComDiagsArea::allocate(getGlobals()->getDefaultHeap());            *cancelStream_ >> *diagsArea;            cancelStream_->clearAllObjects();            if ( retryQidNotActive_ &&                (diagsArea->mainSQLCODE() == -EXE_SUSPEND_QID_NOT_ACTIVE) &&                (++retryCount_ <= 60))            {              SQLMXLoggingArea::logExecRtInfo(__FILE__, __LINE__,                                              "Retrying error 8672.", 0);              DELAY(500);              diagsArea->decrRefCount();              step_ = SEND_MESSAGE;              break;            }            reportError(diagsArea);          }          else             ex_assert(0, "Control failed, but no diagnostics.");        }        step_ = DONE;        break;      }      case DONE:       {        if (cancelStream_)        {          cancelStream_->addToCompletedList();          cancelStream_ = NULL;        }        if (cbServer_)        {          cbServer_->release();          cbServer_ = NULL;        }        ex_queue_entry * up_entry = qparent_.up->getTailEntry();        up_entry->copyAtp(pentry_down);        up_entry->upState.parentIndex = pentry_down->downState.parentIndex;        up_entry->upState.downIndex = qparent_.down->getHeadIndex();             up_entry->upState.setMatchNo(1);        up_entry->upState.status = ex_queue::Q_NO_DATA;        qparent_.up->insert();        qparent_.down->removeHead();        step_ = NOT_STARTED;        break;      }      default:        ex_assert( 0, "Unknown step_.");    }

voidixp425_md_pci_init(struct ixp425_softc *sc){	pci_chipset_tag_t pc = &sc->ia_pci_chipset;	u_int32_t reg;	pc->pc_intr_v = sc;	pc->pc_intr_map = nslu2_pci_intr_map;	pc->pc_intr_string = nslu2_pci_intr_string;	pc->pc_intr_evcnt = nslu2_pci_intr_evcnt;	pc->pc_intr_establish = nslu2_pci_intr_establish;	pc->pc_intr_disestablish = nslu2_pci_intr_disestablish;	/* PCI Reset Assert */	reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);	reg &= ~(1u << GPIO_PCI_RESET);	GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);	/* PCI Clock Disable */	reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);	reg &= ~GPCLKR_MUX14;	GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);	/*	 * Set GPIO Direction	 *	Output: PCI_CLK, PCI_RESET	 *	Input:  PCI_INTA, PCI_INTB, PCI_INTC	 */	reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);	reg &= ~((1u << GPIO_PCI_CLK) | (1u << GPIO_PCI_RESET));	reg |= (1u << GPIO_PCI_INTA) | (1u << GPIO_PCI_INTB) |	    (1u << GPIO_PCI_INTC);	GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);	/*	 * Set GPIO interrupt type	 *      PCI_INT_A, PCI_INTB, PCI_INT_C: Active Low	 */	reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA));	reg &= ~GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_MASK);	reg |= GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_ACT_LOW);	GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA), reg);	reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB));	reg &= ~GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_MASK);	reg |= GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_ACT_LOW);	GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB), reg);	reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC));	reg &= ~GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_MASK);	reg |= GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_ACT_LOW);	GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC), reg);	/* Clear ISR */	GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, (1u << GPIO_PCI_INTA) |	    (1u << GPIO_PCI_INTB) | (1u << GPIO_PCI_INTC));	/* Wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */	DELAY(1000);	reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);	reg |= (0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT);	GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);	/* PCI Clock Enable */	reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);	reg |= GPCLKR_MUX14;	GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);	/*	 * Wait 100us to satisfy "minimum reset assertion time from clock stable	 * requirement of the PCI spec	 */	DELAY(100);        /* PCI Reset deassert */	reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);	reg |= 1u << GPIO_PCI_RESET;	GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);	/*	 * AHB->PCI address translation	 *	PCI Memory Map allocation in 0x48000000 (64MB)	 *	see. IXP425_PCI_MEM_HWBASE	 */	PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);	/*	 * PCI->AHB address translation	 * 	begin at the physical memory start + OFFSET	 */#define	AHB_OFFSET	0x10000000UL	reg  = (AHB_OFFSET + 0x00000000) >> 0;	reg |= (AHB_OFFSET + 0x01000000) >> 8;	reg |= (AHB_OFFSET + 0x02000000) >> 16;	reg |= (AHB_OFFSET + 0x03000000) >> 24;	PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, reg);	/* Write Mapping registers PCI Configuration Registers */	/* Base Address 0 - 3 */	ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);	ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);//.........这里部分代码省略.........

/** * @brief This method is called when the core requires the OS driver *        to stall execution.  This method is utilized during initialization *        or non-performance paths only. * * @param[in]  microseconds This parameter specifies the number of *             microseconds for which to stall.  The operating system driver *             is allowed to round this value up where necessary. * * @return none. */voidscic_cb_stall_execution(uint32_t microseconds){	DELAY(microseconds);}

static intep_eisa_attach(device_t dev){	struct ep_softc *sc = device_get_softc(dev);	struct resource *eisa_io = NULL;	uint32_t eisa_iobase;	int irq;	int error = 0;	int rid;	rid = 1;	eisa_io = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);	if (!eisa_io) {		device_printf(dev, "No I/O space?!/n");		error = ENXIO;		goto bad;	}	eisa_iobase = rman_get_start(eisa_io);	/* Reset and Enable the card */	outb(eisa_iobase + EP_W0_CONFIG_CTRL, W0_P4_CMD_RESET_ADAPTER);	DELAY(1000);		/* we must wait at least 1 ms */	outb(eisa_iobase + EP_W0_CONFIG_CTRL, W0_P4_CMD_ENABLE_ADAPTER);	/* Now the registers are availible through the lower ioport */	if ((error = ep_alloc(dev))) {		device_printf(dev, "ep_alloc() failed! (%d)/n", error);		goto bad;	}	switch (eisa_get_id(dev)) {	case EISA_DEVICE_ID_3COM_3C579_BNC:	case EISA_DEVICE_ID_3COM_3C579_TP:		sc->stat = F_ACCESS_32_BITS;		break;	}	ep_get_media(sc);	irq = rman_get_start(sc->irq);	if (irq == 9)		irq = 2;	GO_WINDOW(sc, 0);	SET_IRQ(sc, irq);	if ((error = ep_attach(sc))) {		device_printf(dev, "ep_attach() failed! (%d)/n", error);		goto bad;	}	if ((error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 	    NULL, ep_intr, sc, &sc->ep_intrhand))) {		device_printf(dev, "bus_setup_intr() failed! (%d)/n", error);		goto bad;	}	return (0);bad:	if (eisa_io)		bus_release_resource(dev, SYS_RES_IOPORT, 0, eisa_io);	ep_free(dev);	return (error);}

static	intlptopen (dev_t dev, int flags, int fmt, struct thread *td){	struct lpt_softc *sc;	int s;#ifdef PC98	int port;#else	int trys, port;#endif	sc = devclass_get_softc(olpt_devclass, LPTUNIT(minor(dev)));	if (sc->sc_port == 0)		return (ENXIO);	if (sc->sc_state) {		lprintf(("lp: still open %x/n", sc->sc_state));		return(EBUSY);	} else		sc->sc_state |= INIT;	sc->sc_flags = LPTFLAGS(minor(dev));	/* Check for open with BYPASS flag set. */	if (sc->sc_flags & LP_BYPASS) {		sc->sc_state = OPEN;		return(0);	}	s = spltty();	lprintf(("lp flags 0x%x/n", sc->sc_flags));	port = sc->sc_port;	/* set IRQ status according to ENABLE_IRQ flag */	if (sc->sc_irq & LP_ENABLE_IRQ)		sc->sc_irq |= LP_USE_IRQ;	else		sc->sc_irq &= ~LP_USE_IRQ;	/* init printer */#ifndef PC98	if ((sc->sc_flags & LP_NO_PRIME) == 0) {		if((sc->sc_flags & LP_PRIMEOPEN) || sc->sc_primed == 0) {			outb(port+lpt_control, 0);			sc->sc_primed++;			DELAY(500);		}	}	outb (port+lpt_control, LPC_SEL|LPC_NINIT);	/* wait till ready (printer running diagnostics) */	trys = 0;	do {		/* ran out of waiting for the printer */		if (trys++ >= LPINITRDY*4) {			splx(s);			sc->sc_state = 0;			lprintf(("status %x/n", inb(port+lpt_status)));			return (EBUSY);		}		/* wait 1/4 second, give up if we get a signal */		if (tsleep ((caddr_t)sc, LPPRI|PCATCH, "lptinit", hz/4) !=		    EWOULDBLOCK) {			sc->sc_state = 0;			splx(s);			return (EBUSY);		}		/* is printer online and ready for output */	} while ((inb(port+lpt_status) & (LPS_SEL|LPS_OUT|LPS_NBSY|LPS_NERR)) !=		 (LPS_SEL|LPS_NBSY|LPS_NERR));	sc->sc_control = LPC_SEL|LPC_NINIT;	if (sc->sc_flags & LP_AUTOLF)		sc->sc_control |= LPC_AUTOL;	/* enable interrupt if interrupt-driven */	if (sc->sc_irq & LP_USE_IRQ)		sc->sc_control |= LPC_ENA;	outb(port+lpt_control, sc->sc_control);#endif	sc->sc_state = OPEN;	sc->sc_inbuf = geteblk(BUFSIZE);	sc->sc_xfercnt = 0;	splx(s);	/* only use timeout if using interrupt */	lprintf(("irq %x/n", sc->sc_irq));	if (sc->sc_irq & LP_USE_IRQ) {		sc->sc_state |= TOUT;		timeout (lptout, (caddr_t)sc,			 (sc->sc_backoff = hz/LPTOUTINITIAL));	}	lprintf(("opened./n"));	return(0);//.........这里部分代码省略.........

double pulse_measure(unsigned BaseAddress){   #define TIMEOUTVAL  150000   unsigned firstcount = 0;   unsigned secondcount = 0;   unsigned previouscount = 0;   unsigned time = 0;   unsigned long timeout;   unsigned one, two;   OUTPORTB(BaseAddress + 3, 0xB4);           // 1011 0100 ctr2 mode2   OUTPORTB(BaseAddress + 2, 0xFF);           // write 65535 to counters   OUTPORTB(BaseAddress + 2, 0xFF);   OUTPORTB(BaseAddress + 3, 0x72);           // 0111 0010 ctr1 mode2   DELAY(1);   OUTPORTB(BaseAddress + 3, 0x70);           // 0111 0000 ctr1 mode2   DELAY(1);   OUTPORTB(BaseAddress + 3, 0x74);           // 0111 0100 ctr1 mode2   OUTPORTB(BaseAddress + 1, 0xFF);           // write 65535 to counters   OUTPORTB(BaseAddress + 1, 0xFF);   firstcount = total_count(BaseAddress); // read the counter   timeout = 0;   do   {      previouscount = firstcount;      firstcount = total_count(BaseAddress);      timeout++;   }   while ((firstcount != previouscount) && (timeout < TIMEOUTVAL));					  // check to see if the counts are changing   one = count2(BaseAddress);   if (timeout < TIMEOUTVAL)      timeout = 0;   do   {      secondcount = total_count(BaseAddress);      timeout++;   }   while ((firstcount == secondcount) && (timeout < TIMEOUTVAL));					  // check to see if counts are stable   if (timeout < TIMEOUTVAL)      timeout = 0;   do   {      previouscount = secondcount;      DELAY(1);      secondcount = total_count(BaseAddress);      timeout++;   }   while ((secondcount != previouscount) && (timeout < TIMEOUTVAL));					  // check to see if counts are changing   two = count2(BaseAddress);   if (timeout < TIMEOUTVAL)   {      time = firstcount - secondcount;      return(time);                       // return the counts for the pulse   }   else      return 0;}

static intcs4281_init(struct sc_info *sc){    u_int32_t i, v;    /* (0) Blast clock register and serial port */    cs4281_wr(sc, CS4281PCI_CLKCR1, 0);    cs4281_wr(sc, CS4281PCI_SERMC,  0);    /* (1) Make ESYN 0 to turn sync pulse on AC97 link */    cs4281_wr(sc, CS4281PCI_ACCTL, 0);    DELAY(50);    /* (2) Effect Reset */    cs4281_wr(sc, CS4281PCI_SPMC, 0);    DELAY(100);    cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);    /* Wait 50ms for ABITCLK to become stable */    DELAY(50000);    /* (3) Enable Sound System Clocks */    cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP);    DELAY(50000); /* Wait for PLL to stabilize */    cs4281_wr(sc, CS4281PCI_CLKCR1,	      CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE);    /* (4) Power Up - this combination is essential. */    cs4281_set4(sc, CS4281PCI_SSPM,		CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN |		CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN);    /* (5) Wait for clock stabilization */    if (cs4281_waitset(sc,		       CS4281PCI_CLKCR1,		       CS4281PCI_CLKCR1_DLLRDY,		       250) == 0) {	device_printf(sc->dev, "Clock stabilization failed/n");	return -1;    }    /* (6) Enable ASYNC generation. */    cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN);    /* Wait to allow AC97 to start generating clock bit */    DELAY(50000);    /* Set AC97 timing */    cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);    /* (7) Wait for AC97 ready signal */    if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) {	device_printf(sc->dev, "codec did not avail/n");	return -1;    }    /* (8) Assert valid frame signal to begin sending commands to     *     AC97 codec */    cs4281_wr(sc,	      CS4281PCI_ACCTL,	      CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN);    /* (9) Wait for codec calibration */    for(i = 0 ; i < 1000; i++) {	DELAY(10000);	v = cs4281_rdcd(0, sc, AC97_REG_POWER);	if ((v & 0x0f) == 0x0f) {	    break;	}    }    if (i == 1000) {	device_printf(sc->dev, "codec failed to calibrate/n");	return -1;    }    /* (10) Set AC97 timing */    cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);    /* (11) Wait for valid data to arrive */    if (cs4281_waitset(sc,		       CS4281PCI_ACISV,		       CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4),		       10000) == 0) {	device_printf(sc->dev, "cs4281 never got valid data/n");	return -1;    }    /* (12) Start digital data transfer of audio data to codec */    cs4281_wr(sc,	      CS4281PCI_ACOSV,	      CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4));    /* Set Master and headphone to max */    cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0);    cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);    /* Power on the DAC */    v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;    cs4281_wrcd(0, sc, AC97_REG_POWER, v);    /* Wait until DAC state ready *///.........这里部分代码省略.........

int main(int argc, char *argv[]){	unsigned freq=0;	float time = 0;	unsigned BASE = 0xFCA0;	unsigned count = 0;	CLRSCR();	BASE=AskForBaseAddress(BASE);	CLRSCR();	count=AskForCountAddress(); //get counter offset	BASE+=count;                //add counter offset to base address	DELAY(100);	PUTS("8254 Counter Sample");	PUTS("--This program measures frequency and pulse width and generates frequency.");	PUTS("--To measure frequency, connect a source to Clk IN on Pin 33.");	PUTS("");	PUTS("Press any key to continue.");	getch();	while(!kbhit()){	  freq = freq;	  time = frequency_measure(BASE);	  printf("/nThe frequency is %10.3f/n/n", time);	  PUTS("Press any key to continue to pulse width test.");	  GOTOXY(1,WHEREY()-4);	}	getch();	CLRSCR();                //is this correct???	PUTS("--To measure pulse width, connect a source to Gate 1 on Pin 34.");	PUTS("--Without a source, pulse width will read zero.");	PUTS("--Ground Pin 37.");	PUTS("");	PUTS("Press any key to continue.");	getch();	while(!kbhit()){	  time = pulse_width(BASE);	  printf(" Pulse1 %g /n", time);	  DELAY(1000);	  time = pulse_width(BASE);	  printf(" Pulse2 %g /n", time);	  DELAY(397);	  time = pulse_width(BASE);	  printf(" Pulse3 %g /n", time);	  time = pulse_width(BASE);	  printf(" Pulse4 %g /n", time);	  DELAY(300);	  time = pulse_width(BASE);	  printf(" Pulse5 %g /n", time);	  DELAY(10);	  time = pulse_width(BASE);	  printf(" Pulse6 %g /n/n", time);	  PUTS("Press any key to continue to next test.");	  GOTOXY(1,WHEREY()-8);  }  getch();  CLRSCR();  while(!kbhit()){	 PUTS("Generating frequency...");	 PUTS("Verify signal by connecting a frequency meter to Out 2 on Pin 35.");	 PUTS("Press any key to continue.");	 generatefrequency(BASE, 25000);	 GOTOXY(1,WHEREY()-3);  }  getch();	//DELAY(2000);}