自学教程：C++ DEXIT函数代码示例

bool CSTi7108HDMI::Create(void){  DENTRY();  m_pIFrameManager = new CSTmV29IFrames(m_pDisplayDevice,m_ulHDMIOffset);  if(!m_pIFrameManager || !m_pIFrameManager->Create(this,m_pMasterOutput))  {    DEBUGF2(2,("Unable to create HDMI v2.9 Info Frame manager/n"));    delete m_pIFrameManager;    m_pIFrameManager = 0;    return false;  }  if(!CSTmHDFormatterHDMI::Create())    return false;  /*   * We need to put the PHY back into reset now we have a lock created   * (by default the reset controller brings it out of reset on chip reset).   *   * TODO: Think about how we make this SMP safe against other drivers.   */  g_pIOS->LockResource(m_statusLock);  ULONG val = ReadSysCfg0Reg(SYS_CFG12_B0) & ~SYS_CFG12_B0_HDMI_PHY_N_RST;  WriteSysCfg0Reg(SYS_CFG12_B0,val);  g_pIOS->UnlockResource(m_statusLock);  DEXIT();  return true;}

bool CSTi7111HDFormatterOutput::SetFilterCoefficients(const stm_display_filter_setup_t *f){  bool ret = true;  DENTRY();  switch(f->type)  {    case HDF_COEFF_2X_LUMA ... HDF_COEFF_4X_CHROMA:    {      if(f->hdf.div < STM_FLT_DIV_4096)      {        DEBUGF2(2,("%s: Setting filter %d/n",__PRETTY_FUNCTION__,f->type));        m_filters[f->type] = f->hdf;        ret = true;      }      else      {        DEBUGF2(1,("%s: Unsupported filter divide %d/n",__PRETTY_FUNCTION__,f->hdf.div));        ret = false;      }      break;    }    default:      ret = CGenericGammaOutput::SetFilterCoefficients(f);      break;  }  DEXIT();  return ret;}

void CSTi7108MainOutput::DisableDACs(void){  DENTRY();  ULONG val;  /*   *  Power down HD DACs if SD pipeline is not doing SCART   */  stm_clk_divider_output_source_t hdpixsrc;  m_pClkDivider->getSource(STM_CLK_PIX_HD,&hdpixsrc);  if(hdpixsrc == STM_CLK_SRC_0)  {    DEBUGF2(2,("%s: Powering Down HD DACs/n",__PRETTY_FUNCTION__));    val = ReadMainTVOutReg(TVOUT_PADS_CTL) | TVOUT_MAIN_PADS_DAC_POFF;    WriteMainTVOutReg(TVOUT_PADS_CTL, val);    /*     * Disable the HDF sample rate converter as well while we are at it.     */    SetUpsampler(0,0);  }  if(m_bUsingDENC)  {    /*     * Power down SD DACs     */    DEBUGF2(2,("%s: Powering Down SD DACs/n",__PRETTY_FUNCTION__));    val = ReadAuxTVOutReg(TVOUT_PADS_CTL) | TVOUT_AUX_PADS_DAC_POFF;    WriteAuxTVOutReg(TVOUT_PADS_CTL, val);  }  DEXIT();}

void CSTi7111MainOutput::StartSDProgressiveClocks(const stm_mode_line_t *mode){  ULONG val;  DENTRY();#if defined(__TDT__) && defined(UFS912)  WriteClkReg(CKGB_LCK, CKGB_LCK_UNLOCK);  WriteDevReg(STi7111_CLKGEN_BASE + CKGB_DISPLAY_CFG, 0x3011);/* maybe we must set fs1_md3 and co here too? especially * if 576p is set as default? */#else  WriteClkReg(CKGB_LCK, CKGB_LCK_UNLOCK);  val = ReadClkReg(CKGB_DISPLAY_CFG);  /*   * Preserve the aux pipeline clock configuration.   */  val &= (CKGB_CFG_PIX_SD_FS1(CKGB_CFG_MASK) |          CKGB_CFG_DISP_ID(CKGB_CFG_MASK)    |          CKGB_CFG_PIX_HD_FS1_N_FS0);  val |= CKGB_CFG_TMDS_HDMI(CKGB_CFG_DIV4);  val |= CKGB_CFG_DISP_HD(CKGB_CFG_DIV4);  val |= CKGB_CFG_656(CKGB_CFG_DIV2);  val |= CKGB_CFG_PIX_SD_FS0(CKGB_CFG_DIV4);  WriteClkReg(CKGB_DISPLAY_CFG, val);#endif  DEXIT();}

void CSTmHDMI::EnableInterrupts(void){  DENTRY();  WriteHDMIReg(STM_HDMI_INT_CLR, 0xffffffff);  ULONG intenables = (STM_HDMI_INT_GLOBAL             |                      STM_HDMI_INT_SW_RST             |                      STM_HDMI_INT_NEW_FRAME          |                      STM_HDMI_INT_GENCTRL_PKT        |                      STM_HDMI_INT_PIX_CAP            |                      STM_HDMI_INT_SPDIF_FIFO_OVERRUN);  intenables |= m_ulIFrameManagerIntMask;  if(m_bUseHotplugInt)    intenables |= STM_HDMI_INT_HOT_PLUG;#if 0  /*   * It looks like the PHY signal has been wired up directly to the interrupt,   * so it cannot be cleared. Awaiting clarification from validation.   */  if(m_HWVersion == STM_HDMI_HW_V_2_9)    intenables |= STM_HDMI_INT_SINK_TERM_PRESENT;#endif  DEBUGF2(2,("%s: int enables = 0x%08lx/n", __PRETTY_FUNCTION__, intenables));  WriteHDMIReg(STM_HDMI_INT_EN, intenables);  DEXIT();}

bool CSTi7200HDMI::PreConfiguration(const stm_mode_line_t *mode,                                    ULONG                  tvStandard){  ULONG phy,preemp;  DENTRY();  /*   * Power up HDMI serializer   */  WriteSysCfgReg(SYS_CFG21, ReadSysCfgReg(SYS_CFG21) & ~SYS_CFG21_HDMI_POFF);  /*   * Setup PHY parameters for mode   */  phy = ReadSysCfgReg(SYS_CFG47) & ~SYS_CFG47_HDMIPHY_BUFFER_SPEED_MASK;  preemp = 0;  if(mode->TimingParams.ulPixelClock > 74250000)  {    /* 1080p 50/60Hz, 2880x480p or 2880x576p note we will only get here on Cut2 */    DEBUGF2(2,("%s: PHY to 1.6Gb/s/n",__PRETTY_FUNCTION__));    phy |= SYS_CFG47_HDMIPHY_BUFFER_SPEED_16;    /*     * 1080p requires pre-emphasis to be enabled.     */    if(mode->TimingParams.ulPixelClock > 148000000)    {      DEBUGF2(2,("%s: Pre-emphasis enabled/n", __PRETTY_FUNCTION__));      preemp = (3 << SYS_CFG19_HDMIPHY_PREEMP_STR_SHIFT) | SYS_CFG19_HDMIPHY_PREEMP_ON;    }  }  else if(mode->TimingParams.ulPixelClock > 27027000)  {    /* 720p, 1080i, 1440x480p, 1440x576p, 2880x480i, 2880x576i */    DEBUGF2(2,("%s: PHY to 800Mb/s/n",__PRETTY_FUNCTION__));    phy |= SYS_CFG47_HDMIPHY_BUFFER_SPEED_8;  }  else  {    DEBUGF2(2,("%s: PHY to 400Mb/s/n",__PRETTY_FUNCTION__));    phy |= SYS_CFG47_HDMIPHY_BUFFER_SPEED_4;  }  WriteSysCfgReg(SYS_CFG47, phy);  /*   * For Cut2 we need to set the pre-emphasis config register, we can tell   * this from the revision of the HDF/HDMI.   */  if(m_Revision != STM_HDF_HDMI_REV1)    WriteSysCfgReg(SYS_CFG19, preemp);  SetupRejectionPLL(mode,tvStandard);  DEXIT();  return true;}

void CSTi7200Cut2LocalAuxOutput::StartClocks(const stm_mode_line_t *mode){  DENTRY();  /*   * There is no need to start the clock as the base frequency is fixed,   * however reset any clock recovery adjustments to zero.   */  m_pFSynth->SetAdjustment(0);  /*   * Ensure we have the right clock routing to start SD mode from. This may   * have been previously changed by the main output pipeline so don't be   * tempted to put this into the constructor.   */  ULONG val = ReadSysCfgReg(SYS_CFG49) & ~(SYS_CFG49_LOCAL_SDTVO_HD | SYS_CFG49_LOCAL_AUX_PIX_HD);  WriteSysCfgReg(SYS_CFG49, val);  /*   * Configure TVOut sub-clocks, driven from an 108MHz input.   */  WriteAuxTVOutReg(TVOUT_CLK_SEL, (TVOUT_AUX_CLK_SEL_PIX1X(TVOUT_CLK_DIV_8) |                                   TVOUT_AUX_CLK_SEL_DENC(TVOUT_CLK_DIV_4)  |                                   TVOUT_AUX_CLK_SEL_SD_N_HD));  DEXIT();}

void CSTi7111MainOutput::StartSDProgressiveClocks(const stm_mode_line_t *mode){  ULONG val;  DENTRY();  WriteClkReg(CKGB_LCK, CKGB_LCK_UNLOCK);  val = ReadClkReg(CKGB_DISPLAY_CFG);  /*   * Preserve the aux pipeline clock configuration.   */  val &= (CKGB_CFG_PIX_SD_FS1(CKGB_CFG_MASK) |          CKGB_CFG_DISP_ID(CKGB_CFG_MASK)    |          CKGB_CFG_PIX_HD_FS1_N_FS0);  val |= CKGB_CFG_TMDS_HDMI(CKGB_CFG_DIV4);  val |= CKGB_CFG_DISP_HD(CKGB_CFG_DIV4);  val |= CKGB_CFG_656(CKGB_CFG_DIV2);#if defined(__TDT__) && defined(CONFIG_CPU_SUBTYPE_STX7111) && defined(USE_FS1_FOR_SD)  val &= ~CKGB_CFG_PIX_SD_FS1(3); // Clear  val |= CKGB_CFG_PIX_SD_FS1(CKGB_CFG_BYPASS); // CLK_PIX_SD_SEL_WHEN_FS1 (<<12)  val &= ~CKGB_CFG_DISP_ID(3); // Clear  val |= CKGB_CFG_DISP_ID(CKGB_CFG_DIV2); // CLK_DISP_ID_SEL (<<8)#else  val |= CKGB_CFG_PIX_SD_FS0(CKGB_CFG_DIV4);#endif  WriteClkReg(CKGB_DISPLAY_CFG, val);  DEXIT();}

/* * Create a IrNET instance : just initialise some parameters... */intirda_irnet_create(irnet_socket *	self){  DENTER(IRDA_SOCK_TRACE, "(self=0x%X)/n", (unsigned int) self);  self->magic = IRNET_MAGIC;	/* Paranoia */  init_waitqueue_head(&self->query_wait);  self->ttp_open = 0;		/* Prevent higher layer from accessing IrTTP */  self->rname[0] = '/0';	/* May be set via control channel */  self->raddr = DEV_ADDR_ANY;	/* May be set via control channel */  self->daddr = DEV_ADDR_ANY;	/* Until we get connected */  self->saddr = 0x0;		/* so IrLMP assign us any link */  self->max_sdu_size_rx = TTP_SAR_UNBOUND;  /* Register as a client with IrLMP */  self->ckey = irlmp_register_client(0, NULL, NULL, NULL);#ifdef DISCOVERY_NOMASK  self->mask = 0xffff;		/* For W2k compatibility */#else DISCOVERY_NOMASK  self->mask = irlmp_service_to_hint(S_LAN);#endif DISCOVERY_NOMASK  self->tx_flow = FLOW_START;	/* Flow control from IrTTP */  DEXIT(IRDA_SOCK_TRACE, "/n");  return(0);}

bool CSTb7109Cut3HDMI::Create(void){  DENTRY();  /*   * Try and create an FDMA driver InfoFrame manager before we call the   * base class Create().   */  m_pIFrameManager = new CSTmDMAIFrames(m_pDisplayDevice, m_ulHDMIOffset, STb7100_REGISTER_BASE);  if(!m_pIFrameManager || !m_pIFrameManager->Create(this,m_pMasterOutput))  {    DEBUGF2(2,("Unable to create a DMA based Info Frame manager/n"));    /*     * Reset m_pIFrameManager so the base class will create the CPU driven     * version instead.     */    delete m_pIFrameManager;    m_pIFrameManager = 0;  }  if(!CSTmHDMI::Create())    return false;  DEXIT();  return true;}

/* * Function irda_open_tsap (self) * *    Open local Transport Service Access Point (TSAP) * * Create a IrTTP instance for us and set all the IrTTP callbacks. */static inline intirnet_open_tsap(irnet_socket *	self){  notify_t	notify;		/* Callback structure */  DENTER(IRDA_SR_TRACE, "(self=0x%X)/n", (unsigned int) self);  DABORT(self->tsap != NULL, -EBUSY, IRDA_SR_ERROR, "Already busy !/n");  /* Initialize IrTTP callbacks to be used by the IrDA stack */  irda_notify_init(&notify);  notify.connect_confirm	= irnet_connect_confirm;  notify.connect_indication	= irnet_connect_indication;  notify.disconnect_indication	= irnet_disconnect_indication;  notify.data_indication	= irnet_data_indication;  /*notify.udata_indication	= NULL;*/  notify.flow_indication	= irnet_flow_indication;  notify.status_indication	= irnet_status_indication;  notify.instance		= self;  strncpy(notify.name, IRNET_NOTIFY_NAME, NOTIFY_MAX_NAME);  /* Open an IrTTP instance */  self->tsap = irttp_open_tsap(LSAP_ANY, DEFAULT_INITIAL_CREDIT,			       &notify);	  DABORT(self->tsap == NULL, -ENOMEM,	 IRDA_SR_ERROR, "Unable to allocate TSAP !/n");  /* Remember which TSAP selector we actually got */  self->stsap_sel = self->tsap->stsap_sel;  DEXIT(IRDA_SR_TRACE, " - tsap=0x%X, sel=0x%X/n",	(unsigned int) self->tsap, self->stsap_sel);  return 0;}

bool CDisplayPlane::Create(void){  DENTRY();  m_lock = g_pIOS->CreateResourceLock();  if(!m_lock)  {    DERROR("failed to allocate resource lock/n");    return false;  }  DEBUGF2(2,("%s: node entries = %lu /n",__PRETTY_FUNCTION__,m_ulNodeEntries));  g_pIOS->AllocateDMAArea(&m_NodeListArea, (m_ulNodeEntries * sizeof(stm_plane_node)), 0, SDAAF_NONE);  g_pIOS->MemsetDMAArea(&m_NodeListArea, 0, 0, m_NodeListArea.ulDataSize);  if(!m_NodeListArea.pMemory)  {    DERROR("failed to allocate node list/n");    return false;  }  m_pNodeList = (stm_plane_node*)m_NodeListArea.pData;  DEXIT();  return true;}

/* * Function irnet_find_lsap_sel (self) * *    Try to lookup LSAP selector in remote LM-IAS * * Basically, we start a IAP query, and then go to sleep. When the query * return, irnet_getvalue_confirm will wake us up, and we can examine the * result of the query... * Note that in some case, the query fail even before we go to sleep, * creating some races... */static intirnet_find_lsap_sel(irnet_socket *	self){  DENTER(IRDA_SR_TRACE, "(self=0x%X)/n", (unsigned int) self);  /* This should not happen */  DABORT(self->iriap, -EBUSY, IRDA_SR_ERROR, "busy with a previous query./n");  /* Create an IAP instance, will be closed in irnet_getvalue_confirm() */  self->iriap = iriap_open(LSAP_ANY, IAS_CLIENT, self,			   irnet_getvalue_confirm);  /* Treat unexpected signals as disconnect */  self->errno = -EHOSTUNREACH;  /* Query remote LM-IAS */  iriap_getvaluebyclass_request(self->iriap, self->saddr, self->daddr,				IRNET_SERVICE_NAME, IRNET_IAS_VALUE);  /* Wait for answer (if not already failed) */  if(self->iriap != NULL)    interruptible_sleep_on(&self->query_wait);  /* Check what happened */  if(self->errno)    {      DEBUG(IRDA_SR_INFO, "IAS query failed! (%d)/n", self->errno);      /* Requested object/attribute doesn't exist */      if((self->errno == IAS_CLASS_UNKNOWN) ||	 (self->errno == IAS_ATTRIB_UNKNOWN))	return (-EADDRNOTAVAIL);      else	return (-EHOSTUNREACH);    }  /* Get the remote TSAP selector */  switch(self->ias_result->type)    {    case IAS_INTEGER:      DEBUG(IRDA_SR_INFO, "result=%d/n", self->ias_result->t.integer);      if(self->ias_result->t.integer != -1)	self->dtsap_sel = self->ias_result->t.integer;      else 	self->dtsap_sel = 0;      break;    default:      self->dtsap_sel = 0;      DERROR(IRDA_SR_ERROR, "bad type ! (0x%X)/n", self->ias_result->type);      break;    }  /* Cleanup */  if(self->ias_result)    irias_delete_value(self->ias_result);  DEXIT(IRDA_SR_TRACE, "/n");  if(self->dtsap_sel)    return 0;  return -EADDRNOTAVAIL;}

void CGammaCompositorNULL::EnableHW(void){  DENTRY();  //    CDisplayPlane::EnableHW();  DEXIT();}

void CSTmMasterOutput::SetClockReference(stm_clock_ref_frequency_t refClock, int error_ppm){  DENTRY();  if(m_pFSynth)    m_pFSynth->SetClockReference(refClock,error_ppm);  DEXIT();}

bool CSTmHDFormatterHDMI::PostConfiguration(const stm_mode_line_t *mode,                                            ULONG                  tvStandard){  DENTRY();  DEXIT();  return true;}

CSTmV29IFrames::CSTmV29IFrames(CDisplayDevice *pDev,ULONG ulHDMIOffset): CSTmIFrameManager(pDev,ulHDMIOffset){  DENTRY();  m_nSlots = 6;  m_ulConfig = 0;  DEXIT();}

void CSTi7200RemoteOutput::DisableDACs(void){  DENTRY();  ULONG val = ReadTVOutReg(TVOUT_PADS_CTL) | TVOUT_PADS_DAC_POFF;  WriteTVOutReg(TVOUT_PADS_CTL, val);  DEXIT();}

bool CSTi7200Cut2LocalAuxOutput::Start(const stm_mode_line_t *mode, ULONG tvStandard){  ULONG tmp;  DENTRY();  if(!m_pCurrentMode && (m_pVTG->GetCurrentMode() != 0))  {    DEBUGF2(1,("CSTi7200Cut2LocalAuxOutput::Start - hardware in use by main output/n"));    return false;  }  /*   * Ensure we have the right clock routing to start SD mode from. This may   * have been previously changed by the main output pipeline so don't be   * tempted to put this into the constructor.   */  tmp = ReadSysCfgReg(SYS_CFG49) & ~(SYS_CFG49_LOCAL_SDTVO_HD | SYS_CFG49_LOCAL_AUX_PIX_HD);  WriteSysCfgReg(SYS_CFG49, tmp);  /*   * Configure TVOut sub-clocks, driven from an 108MHz input.   */  WriteAuxTVOutReg(TVOUT_CLK_SEL, (TVOUT_AUX_CLK_SEL_PIX1X(TVOUT_CLK_DIV_8) |                                   TVOUT_AUX_CLK_SEL_DENC(TVOUT_CLK_DIV_4)  |                                   TVOUT_AUX_CLK_SEL_SD_N_HD));  /*   * Ensure the DENC is getting the video from the Aux mixer   */  tmp = ReadTVFmtReg(TVFMT_ANA_CFG) & ~ANA_CFG_SEL_MAIN_TO_DENC;  WriteTVFmtReg(TVFMT_ANA_CFG,tmp);  m_pDENC->SetMainOutputFormat(m_ulOutputFormat);  /*   * Make sure the offsets are reset in case the VTG has previously been in use   * by the main display output.   */  m_pVTG->SetHSyncOffset(1, DENC_DELAY);  m_pVTG->SetVSyncHOffset(1, DENC_DELAY);  /*   * Make sure the VTG ref signals are +ve for master mode   */  m_pVTG->SetSyncType(0, STVTG_SYNC_POSITIVE);  if(!CGenericGammaOutput::Start(mode, tvStandard))  {    DEBUGF2(2,("CSTi7200Cut2LocalAuxOutput::Start - failed/n"));    return false;  }  DEXIT();  return true;}

CSTmDMAIFrames::~CSTmDMAIFrames(void){  DENTRY();  g_pIOS->StopDMAChannel(m_DMAChannel);  g_pIOS->DeleteDMATransfer(m_DMAHandle);  g_pIOS->ReleaseDMAChannel(m_DMAChannel);  DEXIT();}

bool CSTi7200Cut1LocalAuxOutput::Start(const stm_mode_line_t *mode, ULONG tvStandard){  ULONG tmp;  DENTRY();  if(!m_pCurrentMode && (m_pVTG->GetCurrentMode() != 0))  {    DEBUGF2(1,("CSTi7200Cut1LocalAuxOutput::Start - hardware in use by main output/n"));    return false;  }  /*   * Ensure we have the right clock routing to start SD mode from the   * 27MHz clock source.   */  tmp = ReadHDMIReg(STM_HDMI_SYNC_CFG) & ~(HDMI_GPOUT_LOCAL_SDTVO_HD | HDMI_GPOUT_LOCAL_AUX_PIX_HD);  WriteHDMIReg(STM_HDMI_SYNC_CFG, tmp);  tmp = ReadTVOutReg(TVOUT_PADS_CTL) & ~(TVOUT_CLK_MASK << TVOUT_AUX_PADS_LOCAL_AUX_DIV_SHIFT);  tmp |= (TVOUT_CLK_DIV_2 << TVOUT_AUX_PADS_LOCAL_AUX_DIV_SHIFT);  WriteTVOutReg(TVOUT_PADS_CTL, tmp);  WriteTVOutReg(TVOUT_CLK_SEL, ((TVOUT_CLK_BYPASS << TVOUT_CLK_SEL_DENC_SHIFT) |                                (TVOUT_CLK_DIV_2  << TVOUT_CLK_SEL_PIX1X_SHIFT)));  /*   * Ensure the DENC is getting the video from the Aux mixer   */  tmp = ReadTVFmtReg(TVFMT_ANA_CFG) & ~ANA_CFG_SEL_MAIN_TO_DENC;  WriteTVFmtReg(TVFMT_ANA_CFG,tmp);  m_pDENC->SetMainOutputFormat(m_ulOutputFormat);  /*   * Make sure the VTG ref signals are +ve for master mode   */  m_pVTG->SetSyncType(0, STVTG_SYNC_POSITIVE);  /*   * Make sure the offsets are reset in case the VTG has previously been in use   * by the main display output.   */  m_pVTG->SetHSyncOffset(1, DENC_DELAY);  m_pVTG->SetVSyncHOffset(1, DENC_DELAY);  if(!CGenericGammaOutput::Start(mode, tvStandard))  {    DEBUGF2(2,("CSTi7200Cut1LocalAuxOutput::Start - failed/n"));    return false;  }  DEXIT();  return true;}