自学教程：C++ DISP_REG_SET_FIELD函数代码示例

int OVLLayerSwitch(unsigned layer, bool en) {    ASSERT(layer<=3);    switch(layer) {    case 0:        DISP_REG_SET_FIELD(SRC_CON_FLD_L0_EN, DISP_REG_OVL_SRC_CON, en);        DISP_REG_SET(DISP_REG_OVL_RDMA0_CTRL, 0);        break;    case 1:        DISP_REG_SET_FIELD(SRC_CON_FLD_L1_EN, DISP_REG_OVL_SRC_CON, en);        DISP_REG_SET(DISP_REG_OVL_RDMA1_CTRL, 0);        break;    case 2:        DISP_REG_SET_FIELD(SRC_CON_FLD_L2_EN, DISP_REG_OVL_SRC_CON, en);        DISP_REG_SET(DISP_REG_OVL_RDMA2_CTRL, 0);        break;    case 3:        DISP_REG_SET_FIELD(SRC_CON_FLD_L3_EN, DISP_REG_OVL_SRC_CON, en);        DISP_REG_SET(DISP_REG_OVL_RDMA3_CTRL, 0);        break;    default:        printk("error: invalid layer=%d /n", layer);           // invalid layer        ASSERT(0);    }    return 0;}

int OVLLayerSwitch(DISP_MODULE_ENUM module,                        unsigned layer,                        unsigned int en,                       void * handle){           int idx = ovl_index(module);    ASSERT(layer<=3);        switch(layer) {        case 0:            DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L0_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);            break;        case 1:            DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L1_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);            break;        case 2:            DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L2_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);            break;        case 3:            DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L3_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);            break;        default:            DDPERR("invalid layer=%d/n", layer);           // invalid layer            ASSERT(0);    }    return 0;}

/* start module */int SCLStart(void){	DISP_REG_SET_FIELD(DSCL_INTEN_FLD_OF_END_INT_EN, DISP_REG_SCL_INTEN, 0);	DISP_REG_SET_FIELD(DSCL_INTEN_FLD_IF_END_INT_EN, DISP_REG_SCL_INTEN, 0);	DISP_REG_SET_FIELD(DSCL_CTRL_FLD_SCL_EN, DISP_REG_SCL_CTRL, 1);	return 0;}

int rdma_reset(DISP_MODULE_ENUM module,void * handle) {    unsigned int delay_cnt=0;    int ret =0;    unsigned int idx = rdma_index(module);    ASSERT(idx <= 2);    DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_SOFT_RESET, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, 1);    while((DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON)&0x700)==0x100)    {        delay_cnt++;        udelay(10);        if(delay_cnt>10000)        {            ret = -1;            DDPERR("rdma%d_reset timeout, stage 1! DISP_REG_RDMA_GLOBAL_CON=0x%x /n", idx, DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON));            break;        }    }          DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_SOFT_RESET, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, 0);    delay_cnt =0;    while((DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON)&0x700)!=0x100)    {        delay_cnt++;        udelay(10);        if(delay_cnt>10000)        {            ret = -1;            DDPERR("rdma%d_reset timeout, stage 2! DISP_REG_RDMA_GLOBAL_CON=0x%x /n", idx, DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON));            break;        }    }       return ret;}

static int ufoe_reset(DISP_MODULE_ENUM module, void *handle){	DISP_REG_SET_FIELD(handle, START_FLD_DISP_UFO_SW_RST_ENGINE, DISP_REG_UFO_START, 1);	DISP_REG_SET_FIELD(handle, START_FLD_DISP_UFO_SW_RST_ENGINE, DISP_REG_UFO_START, 0);	 DDPMSG("ufoe reset done/n");	return 0;}

/*scale reg enable relay mode*/void disp_scl_enable_relay_mode(BOOL enable, unsigned src_width, unsigned src_height){	DISP_REG_SET_FIELD(DSCL_CFG_FLD_RELAY_MODE, DISP_REG_SCL_CFG, enable);	DISP_REG_SET_FIELD(DSCL_HRZ_SIZE_FLD_HRZ_TARSZ, DISP_REG_SCL_HRZ_SIZE, src_width);	DISP_REG_SET_FIELD(DSCL_HRZ_SIZE_FLD_HRZ_SRCSZ, DISP_REG_SCL_HRZ_SIZE, src_width);	DISP_REG_SET_FIELD(DSCL_VRZ_SIZE_FLD_VRZ_TARSZ, DISP_REG_SCL_VRZ_SIZE, src_height);	DISP_REG_SET_FIELD(DSCL_VRZ_SIZE_FLD_VRZ_SRCSZ, DISP_REG_SCL_VRZ_SIZE, src_height);}

/*scale reg enable*/void disp_scl_reg_enable(BOOL enable){	BOOL bEnable = enable;	if (bEnable) {		DISP_REG_SET_FIELD(DSCL_INTEN_FLD_OF_END_INT_EN, DISP_REG_SCL_INTEN, 1);		DISP_REG_SET_FIELD(DSCL_INTEN_FLD_IF_END_INT_EN, DISP_REG_SCL_INTEN, 1);	}	DISP_REG_SET_FIELD(DSCL_CTRL_FLD_SCL_EN, DISP_REG_SCL_CTRL, bEnable);}

void WDMASlowMode(unsigned int idx,                           unsigned int enable,                           unsigned int level,                           unsigned int cnt,                          unsigned int threadhold){        DISP_REG_SET_FIELD(WDMA_SMI_CON_FLD_Slow_Enable, DISP_REG_WDMA_SMI_CON, enable&0x01);    DISP_REG_SET_FIELD(WDMA_SMI_CON_FLD_Slow_Count,  DISP_REG_WDMA_SMI_CON, cnt&0xff);    DISP_REG_SET_FIELD(WDMA_SMI_CON_FLD_Slow_Level,  DISP_REG_WDMA_SMI_CON, level&0x7);    DISP_REG_SET_FIELD(WDMA_SMI_CON_FLD_Threshold,   DISP_REG_WDMA_SMI_CON, threadhold&0xf);}

/* configu module */int SCLConfig(DISP_INTERLACE_FORMAT interlace,	      int rotateDegree, int srcWidth, int srcHeight, int dstWidth, int dstHeight, int flip){	unsigned char rotate = 0;	unsigned char isInterlace = (interlace == DISP_INTERLACE_FORMAT_NONE) ? 0 : 1;	unsigned char isBottomField = (interlace == DISP_INTERLACE_FORMAT_BOTTOM_FIELD) ? 1 : 0;	switch (rotateDegree) {	case 0:		rotate = 0;		break;	case 90:		rotate = 1;		break;	case 180:		rotate = 2;		break;	case 270:		rotate = 3;		break;	default:		DDP_SCL_LOG("unsupport rotate degree %d", rotateDegree);		break;	}	DDP_SCL_LOG("DpEngine_SCL config.../n");	DDP_SCL_LOG(" input (w, h) : %d %d/n", srcWidth, srcHeight);	DDP_SCL_LOG(" output (w, h) : %d %d/n", dstWidth, dstHeight);	DDP_SCL_LOG(" rotate : %d, flip=%d/n", rotate, flip);	disp_scl_set_scale_param(srcWidth,				 srcHeight,				 dstWidth,				 dstHeight,				 isInterlace,	/* 0=progressive source, 1=interlaced source */				 isBottomField,	/* 0=source is top field, 1=source is bottom field */				 rotate,	/* source rotated; 0=no, 1=90, 2=180, 3=270 (clockwise) */				 flip);	/* source horizontal flipped; 0=no flip, 1=flipped */	DISP_REG_SET_FIELD(DSCL_INP_CHKSUM_FLD_INP_CHKSUM_EN, DISP_REG_SCL_INP_CHKSUM, 1);	DISP_REG_SET_FIELD(DSCL_OUTP_CHKSUM_FLD_OUTP_CHKSUM_EN, DISP_REG_SCL_OUTP_CHKSUM, 1);	return 0;}

int ovl_start(DISP_MODULE_ENUM module, void *handle){	int idx = ovl_index(module);	int idx_offset = idx*DISP_OVL_INDEX_OFFSET;	DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_EN, 0x01);	int enable_ovl_irq = 1;#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)	enable_ovl_irq = 1;#else	if(gEnableIRQ==1)	    enable_ovl_irq = 1;	else		enable_ovl_irq = 0;#endif	if(enable_ovl_irq)	    DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTEN, 0x1e2);	else	    DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTEN, 0x1e0);	    	DISP_REG_SET_FIELD(handle, DATAPATH_CON_FLD_LAYER_SMI_ID_EN,			idx_offset+DISP_REG_OVL_DATAPATH_CON, 0x1);	return 0;}

/* stop module */int SCLStop(void){	DISP_REG_SET_FIELD(DSCL_CTRL_FLD_SCL_EN, DISP_REG_SCL_CTRL, 0);	DISP_REG_SET(DISP_REG_SCL_INTEN, 0);	DISP_REG_SET(DISP_REG_SCL_INTSTA, 0);	return 0;}

int RDMAReset(unsigned idx){	unsigned int delay_cnt = 0;	/* static unsigned int cnt=0; */	ASSERT(idx <= 2);	DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET,			   idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 1);	while ((DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON) & 0x700) == 0x100) {		delay_cnt++;		if (delay_cnt > 10000) {			DISP_ERR			    ("[DDP] error, RDMAReset(%d) timeout, stage 1! DISP_REG_RDMA_GLOBAL_CON=0x%x/n",			     idx, DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON));			break;		}	}	DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET,			   idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 0);	while ((DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON) & 0x700) != 0x100) {		delay_cnt++;		if (delay_cnt > 10000) {			DISP_ERR			    ("[DDP] error, RDMAReset(%d) timeout, stage 2! DISP_REG_RDMA_GLOBAL_CON=0x%x/n",			     idx, DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON));			ddp_dump_info(DISP_MODULE_CONFIG);			ddp_dump_info(DISP_MODULE_MUTEX);			ddp_dump_info(DISP_MODULE_OVL);			ddp_dump_info(DISP_MODULE_RDMA);			break;		}	}#if 0	DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 0x00);	DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0x00);	DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_1, 0x00);	DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_CON, 0x00);	DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_START_ADDR, 0x00);	DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_SRC_PITCH, 0x00);	DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_GMC_SETTING_1, 0x20);	/* /TODO: need check */	/* DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_FIFO_CON , 0x80f00008);        ///TODO: need check */#endif	return 0;}

int hdmi_dst_display_path_config(bool enable){    HDMI_FUNC();    if (enable)    {        //FIXME: now nothing can be seen on TV if output UYVY from WDMA0        unsigned int hdmiSourceAddr = hdmi_mva_r;// + p->hdmi_width * p->hdmi_height * hdmi_bpp * hdmi_buffer_read_id;        struct disp_path_config_struct config = {0};        // Config RDMA->DPI1        config.srcWidth = 1280;        config.srcHeight = 720;        config.srcModule = DISP_MODULE_RDMA1;        config.inFormat = RDMA_INPUT_FORMAT_ARGB;        config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;        config.addr = hdmiSourceAddr;        config.pitch = config.srcWidth * 4;        config.dstModule = DISP_MODULE_DPI0;        //if(-1 == dp_mutex_dst)        //   dp_mutex_dst = disp_lock_mutex();        dp_mutex_dst = 2;        disp_dump_reg(DISP_MODULE_RDMA0);        disp_dump_reg(DISP_MODULE_RDMA1);        disp_dump_reg(DISP_MODULE_CONFIG);        HDMI_LOG("Get mutex ID %d for RDMA1>DPI1/n", dp_mutex_dst);        disp_path_get_mutex_(dp_mutex_dst);        disp_path_config_(&config, dp_mutex_dst);        disp_path_release_mutex_(dp_mutex_dst);        disp_dump_reg(DISP_MODULE_CONFIG);        disp_dump_reg(DISP_MODULE_RDMA0);        disp_dump_reg(DISP_MODULE_RDMA1);    }    else    {        if (-1 != dp_mutex_dst)        {            //FIXME: release mutex timeout            HDMI_LOG("Stop RDMA1>DPI1/n");            disp_path_get_mutex_(dp_mutex_dst);            DISP_REG_SET_FIELD(1 << dp_mutex_src , DISP_REG_CONFIG_MUTEX_INTEN,  1);            RDMAStop(1);            RDMAReset(1);            disp_path_release_mutex_(dp_mutex_dst);            //disp_unlock_mutex(dp_mutex_dst);            dp_mutex_dst = -1;        }    }    return 0;}

int RDMAReset(unsigned idx) {	unsigned int delay_cnt = 0;    ASSERT(idx <= 2);    DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 1);    while((DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON)&0x700)==0x100) {    	delay_cnt++;    	if(delay_cnt > 10000) {    		printf("[DDP] error, RDMAReset(%d) timeout, stage 1! DISP_REG_RDMA_GLOBAL_CON=0x%x /n", idx, DISP_REG_GET(idx * 0x1000 + DISP_REG_RDMA_GLOBAL_CON));    		break;    	}    }    DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 0);    return 0;}

int RDMAStop(unsigned idx) {    ASSERT(idx <= 2);    DISP_REG_SET_FIELD(GLOBAL_CON_FLD_ENGINE_EN, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 0);    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_INT_ENABLE, 0);    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_INT_STATUS, 0);    return 0;}

int RDMAReset(unsigned idx) {    ASSERT(idx <= 2);    DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET, DISP_REG_RDMA_GLOBAL_CON, 1);     DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET, DISP_REG_RDMA_GLOBAL_CON, 0);     DISP_REG_SET(DISP_REG_RDMA_GLOBAL_CON     , 0x00);    DISP_REG_SET(DISP_REG_RDMA_SIZE_CON_0     , 0x00);    DISP_REG_SET(DISP_REG_RDMA_SIZE_CON_1     , 0x00);    DISP_REG_SET(DISP_REG_RDMA_MEM_CON         , 0x00);    DISP_REG_SET(DISP_REG_RDMA_MEM_START_ADDR , 0x00);    DISP_REG_SET(DISP_REG_RDMA_MEM_SRC_PITCH     , 0x00);    DISP_REG_SET(DISP_REG_RDMA_MEM_GMC_SETTING_1 , 0x20);     ///TODO: need check    DISP_REG_SET(DISP_REG_RDMA_FIFO_CON , 0x81000040);        ///TODO: need check        return 0;}

int OVLStart(DISP_MODULE_ENUM module,void * handle) {    int idx = ovl_index(module);    DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_INTEN, 0x0E);    DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_EN, 0x01);    DISP_REG_SET_FIELD(handle,DATAPATH_CON_FLD_LAYER_SMI_ID_EN,		                idx*DISP_INDEX_OFFSET+DISP_REG_OVL_DATAPATH_CON,0x1);    return 0;}

int rdma_stop(DISP_MODULE_ENUM module,void * handle) {    unsigned int idx = rdma_index(module);    ASSERT(idx <= 2);    DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_ENGINE_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, 0);    DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_INT_ENABLE, 0);    DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS, 0);    return 0;}

int ufoe_start(DISP_MODULE_ENUM module, void* cmdq){	if(ufoe_enable)	{		DISP_REG_SET_FIELD(cmdq, START_FLD_DISP_UFO_START, DISP_REG_UFO_START, 1);	}	DDPMSG("ufoe_start, ufoe_start:0x%x/n", DISP_REG_GET(DISP_REG_UFO_START));	return 0;}

int WDMAConfigUV(unsigned idx, unsigned int uAddr, unsigned int vAddr, unsigned int dstWidth){    unsigned int bpp=1;    DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_U_ADDR, uAddr);    DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_V_ADDR, vAddr);    DISP_REG_SET_FIELD(WDMA_BUF_ADDR_FLD_UV_Pitch, idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_UV_PITCH, dstWidth * bpp/2);    return 0;}

static int WDMADumpHidenReg(unsigned idx){  unsigned int i=0;  printk("[DDP] dump WDMA 0xac:/n [DDP]:");  for(i=0;i<16;i++)  {      DISP_REG_SET_FIELD(WDMA_CFG_FLD_REG_MASK, idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_CFG, i);      printk("0x%x, ", DISP_REG_GET(DISP_REG_WDMA_CFG));  }}

int RDMAReset(unsigned idx) {    unsigned int delay_cnt=0;    //static unsigned int cnt=0;        // printk("[DDP] RDMAReset called %d /n", cnt++);    ASSERT(idx <= 2);    DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 1);    while((DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON)&0x700)==0x100)    {        delay_cnt++;        if(delay_cnt>10000)        {            printk("[DDP] error, RDMAReset(%d) timeout, stage 1! DISP_REG_RDMA_GLOBAL_CON=0x%x /n", idx, DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON));            break;        }    }          DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 0);    // printk("[DDP] start reset! /n");    while((DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON)&0x700)!=0x100)    {        delay_cnt++;        if(delay_cnt>10000)        {            printk("[DDP] error, RDMAReset(%d) timeout, stage 2! DISP_REG_RDMA_GLOBAL_CON=0x%x /n", idx, DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON));            break;        }    }       // printk("[DDP] end reset! /n");        DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON     , 0x00);    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0     , 0x00);    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_1     , 0x00);    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_CON         , 0x00);    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_START_ADDR , 0x00);    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_SRC_PITCH     , 0x00);    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_GMC_SETTING_1 , 0x20);     ///TODO: need check    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_FIFO_CON , 0x80f00008);        ///TODO: need check        return 0;}

int rdma_resolution_test(DISP_MODULE_ENUM module,unsigned int fw,unsigned fh){	int ret=0;	unsigned int idx = rdma_index(module);		int pw = DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_RDMA_INDEX_OFFSET*idx)&0xfff;	int ph = DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_RDMA_INDEX_OFFSET*idx)&0xfffff;    //reset rdma	ret=rdma_reset(module,NULL);	if(ret!=0)	{		printk("reset fail/n");		return -1;	}	DISP_REG_SET_FIELD(NULL,SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_0, pw);    DISP_REG_SET_FIELD(NULL,SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_1, ph);	DISP_REG_SET_FIELD(NULL,SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_0, fw);    DISP_REG_SET_FIELD(NULL,SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_1, fh);	int w = DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_RDMA_INDEX_OFFSET*idx)&0xfff;    int h = DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_RDMA_INDEX_OFFSET*idx)&0xfffff;    if((w!=pw) && (h!=ph))    {        printk("w=%d,h=%d,pw=%d,ph=%d,fw=%d,fh=%d/n",w,h,pw,ph,fw,fh);		DISP_REG_SET_FIELD(NULL,SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_0, pw);    	DISP_REG_SET_FIELD(NULL,SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_1, ph);		ret =-1;    }		return ret;}

// set ultra registersvoid rdma_set_ultra(unsigned int idx, unsigned int width, unsigned int height, unsigned int bpp, unsigned int frame_rate,void * handle){  // constant  static const unsigned int blank_overhead = 115; //it is 1.15, need to divide 100 later  static const unsigned int rdma_fifo_width = 16; //in unit of byte  static const unsigned int ultra_low_time      = 5; //in unit of us  static const unsigned int pre_ultra_low_time  = 7; //in unit of us  static const unsigned int pre_ultra_high_time = 8; //in unit of us  static const unsigned int fifo_size = 512;  static const unsigned int fifo_valid_line_ratio = 125; //valid size 1/8 line;  static const unsigned int fifo_min_size = 24;  // working variables  unsigned int consume_levels_per_sec;  unsigned int ultra_low_level;  unsigned int pre_ultra_low_level;  unsigned int pre_ultra_high_level;  unsigned int ultra_high_ofs;  unsigned int pre_ultra_low_ofs;  unsigned int pre_ultra_high_ofs;  unsigned int fifo_valid_size = 16;  /* compute fifo valid size */  fifo_valid_size = (width * bpp * fifo_valid_line_ratio) / (rdma_fifo_width * 1000);  fifo_valid_size = fifo_valid_size > fifo_min_size ? fifo_valid_size : fifo_min_size;  //consume_levels_per_sec = ((long long unsigned int)width*height*frame_rate*blank_overhead*bpp)/rdma_fifo_width/100;  //change calculation order to prevent overflow of unsigned int  consume_levels_per_sec = (width*height*frame_rate*bpp/rdma_fifo_width/100)*blank_overhead;    // /1000000 for ultra_low_time in unit of us  ultra_low_level      = (unsigned int)(ultra_low_time      * consume_levels_per_sec / 1000000 );   pre_ultra_low_level  = (unsigned int)(pre_ultra_low_time  * consume_levels_per_sec / 1000000 );   pre_ultra_high_level = (unsigned int)(pre_ultra_high_time * consume_levels_per_sec / 1000000 );     pre_ultra_low_ofs = pre_ultra_low_level - ultra_low_level;  ultra_high_ofs = 1;   pre_ultra_high_ofs = pre_ultra_high_level - pre_ultra_low_level ;    //write ultra_low_level, ultra_high_ofs, pre_ultra_low_ofs, pre_ultra_high_ofs into register DISP_RDMA_MEM_GMC_SETTING_0  DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_GMC_SETTING_0,     ultra_low_level|(pre_ultra_low_ofs<<8)|(ultra_high_ofs<<16)|(pre_ultra_high_ofs<<24));  DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_OUTPUT_VALID_FIFO_THRESHOLD, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, fifo_valid_size);  DDPDBG("FIFO_VALID_Size      = 0x%03x = %d/n", fifo_valid_size     , fifo_valid_size     );   DDPDBG("ultra_low_level      = 0x%03x = %d/n", ultra_low_level     , ultra_low_level     );   DDPDBG("pre_ultra_low_level  = 0x%03x = %d/n", pre_ultra_low_level , pre_ultra_low_level );  DDPDBG("pre_ultra_high_level = 0x%03x = %d/n", pre_ultra_high_level, pre_ultra_high_level);  DDPDBG("ultra_high_ofs       = 0x%03x = %d/n", ultra_high_ofs      , ultra_high_ofs      );  DDPDBG("pre_ultra_low_ofs    = 0x%03x = %d/n", pre_ultra_low_ofs   , pre_ultra_low_ofs   );  DDPDBG("pre_ultra_high_ofs   = 0x%03x = %d/n", pre_ultra_high_ofs  , pre_ultra_high_ofs  );}

int WDMAConfigUV(unsigned idx, unsigned int uAddr, unsigned int vAddr, unsigned int dstWidth){    unsigned int bpp=1;    DISP_REG_SET(DISP_REG_WDMA_DST_ADDR1, uAddr);    DISP_REG_SET(DISP_REG_WDMA_DST_ADDR2, vAddr);    DISP_REG_SET_FIELD(WDMA_BUF_ADDR_FLD_UV_Pitch, DISP_REG_WDMA_DST_UV_PITCH, dstWidth * bpp/2);    return 0;}

int RDMAConfig(unsigned idx,                    enum RDMA_MODE mode,                    enum RDMA_INPUT_FORMAT inputFormat,                     unsigned address,                     enum RDMA_OUTPUT_FORMAT outputFormat,                     unsigned pitch,                    unsigned width,                     unsigned height,                     bool isByteSwap, // input setting                    bool isRGBSwap)  // ourput setting{    unsigned bpp;        ASSERT(idx <= 2);    ASSERT((width <= RDMA_MAX_WIDTH) && (height <= RDMA_MAX_HEIGHT));    switch(inputFormat) {    case RDMA_INPUT_FORMAT_YUYV:    case RDMA_INPUT_FORMAT_UYVY:    case RDMA_INPUT_FORMAT_YVYU:    case RDMA_INPUT_FORMAT_VYUY:    case RDMA_INPUT_FORMAT_RGB565:        bpp = 2;        break;    case RDMA_INPUT_FORMAT_RGB888:        bpp = 3;        break;    case RDMA_INPUT_FORMAT_ARGB:        bpp = 4;        break;    default:        ASSERT(0);    }    printk("RDMA: w=%d, h=%d, addr=%x, pitch=%d, mode=%d /n", width, height, address, width*bpp, mode);	    DISP_REG_SET_FIELD(GLOBAL_CON_FLD_MODE_SEL, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, mode);    DISP_REG_SET_FIELD(MEM_CON_FLD_MEM_MODE_INPUT_FORMAT, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_CON, inputFormat);        DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_START_ADDR, address);    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_SRC_PITCH, pitch);    DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_INT_ENABLE, 0x1F);        DISP_REG_SET_FIELD(SIZE_CON_0_FLD_INPUT_BYTE_SWAP, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, isByteSwap);    DISP_REG_SET_FIELD(SIZE_CON_0_FLD_OUTPUT_FORMAT, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, outputFormat);    DISP_REG_SET_FIELD(SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, width);    DISP_REG_SET_FIELD(SIZE_CON_0_FLD_OUTPUT_RGB_SWAP, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, isRGBSwap);    DISP_REG_SET_FIELD(SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_1, height);    return 0;}

static int ufoe_config(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* handle){	LCM_PARAMS *disp_if_config = &(pConfig->dispif_config);	LCM_DSI_PARAMS *lcm_config = &(disp_if_config->dsi);	if(lcm_config->ufoe_enable == 1 && pConfig->dst_dirty)	{		ufoe_enable = true;		DISP_REG_SET_FIELD(handle, START_FLD_DISP_UFO_BYPASS, DISP_REG_UFO_START, 0);//disable BYPASS ufoe//		DISP_REG_SET_FIELD(handle, START_FLD_DISP_UFO_START, DISP_REG_UFO_START, 1);		if(lcm_config->ufoe_params.lr_mode_en == 1)		{			DISP_REG_SET_FIELD(handle, START_FLD_DISP_UFO_LR_EN, DISP_REG_UFO_START, 1);		}		else		{			DISP_REG_SET_FIELD(handle, START_FLD_DISP_UFO_LR_EN, DISP_REG_UFO_START, 0);			if(lcm_config->ufoe_params.compress_ratio == 3)			{				unsigned int internal_width = disp_if_config->width + disp_if_config->width%4;				DISP_REG_SET_FIELD(handle, CFG_0B_FLD_DISP_UFO_CFG_COM_RATIO, DISP_REG_UFO_CFG_0B, 1);				if(internal_width % 6 != 0)				{					DISP_REG_SET_FIELD(handle, CR0P6_PAD_FLD_DISP_UFO_STR_PAD_NUM, DISP_REG_UFO_CR0P6_PAD , (internal_width/6 + 1) * 6 - internal_width);				}			}			else				DISP_REG_SET_FIELD(handle, CFG_0B_FLD_DISP_UFO_CFG_COM_RATIO, DISP_REG_UFO_CFG_0B, 0);			if(lcm_config->ufoe_params.vlc_disable)			{				DISP_REG_SET_FIELD(handle, CFG_0B_FLD_DISP_UFO_CFG_VLC_EN, DISP_REG_UFO_CFG_0B, 0);				DISP_REG_SET(handle, DISP_REG_UFO_CFG_1B, 0x1);			}			else			{				DISP_REG_SET_FIELD(handle, CFG_0B_FLD_DISP_UFO_CFG_VLC_EN, DISP_REG_UFO_CFG_0B, 1);				DISP_REG_SET(handle, DISP_REG_UFO_CFG_1B,  (lcm_config->ufoe_params.vlc_config == 0)?5: lcm_config->ufoe_params.vlc_config);			}		}		DISP_REG_SET(handle, DISP_REG_UFO_FRAME_WIDTH, pConfig->dst_w);		DISP_REG_SET(handle, DISP_REG_UFO_FRAME_HEIGHT, pConfig->dst_h);		ufoe_dump();	}		return 0;}

int OVLLayerSwitch(unsigned layer, bool en) {        ASSERT(layer<=3);        switch(layer) {        case 0:            DISP_REG_SET_FIELD(SRC_CON_FLD_L0_EN, DISP_REG_OVL_SRC_CON, en);            break;        case 1:            DISP_REG_SET_FIELD(SRC_CON_FLD_L1_EN, DISP_REG_OVL_SRC_CON, en);            break;        case 2:            DISP_REG_SET_FIELD(SRC_CON_FLD_L2_EN, DISP_REG_OVL_SRC_CON, en);            break;        case 3:            DISP_REG_SET_FIELD(SRC_CON_FLD_L3_EN, DISP_REG_OVL_SRC_CON, en);            break;        default:            DDP_DRV_ERR("error: invalid layer=%d /n", layer);           // invalid layer            ASSERT(0);    }    return 0;}

int rdma_build_cmdq(DISP_MODULE_ENUM module,void *cmdq_trigger_handle, CMDQ_STATE state){	int ret = 0;    unsigned int idx = rdma_index(module);	if(cmdq_trigger_handle == NULL) 	{		DDPERR("cmdq_trigger_handle is NULL/n");		return -1;	}		if(disp_helper_get_option(DISP_HELPER_OPTION_DYNAMIC_SWITCH_UNDERFLOW_EN))	{		if(state == CMDQ_AFTER_STREAM_EOF) 	{	    DISP_REG_SET_FIELD(cmdq_trigger_handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 0);	}	else if(state == CMDQ_AFTER_STREAM_SOF)	{	    DISP_REG_SET_FIELD(cmdq_trigger_handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 1);	}	}	return 0;}

static int ddp_mutex_set_l(int mutex_id, int* module_list, DDP_MODE ddp_mode, void * handle){    int i=0;    kal_uint32 value = 0;    int module_num = ddp_get_module_num_l(module_list);    MUTEX_SOF mode = ddp_get_mutex_sof(module_list[module_num-1],ddp_mode);    if(mutex_id < DISP_MUTEX_DDP_FIRST || mutex_id > DISP_MUTEX_DDP_LAST)    {        DDPERR("exceed mutex max (0 ~ %d)/n",DISP_MUTEX_DDP_LAST);        return -1;    }    for(i = 0 ; i < module_num ; i++)    {        if(module_mutex_map[module_list[i]].bit != -1)        {            DDPDBG("module %s added to mutex %d/n",ddp_get_module_name(module_list[i]),mutex_id);            value |= (1 << module_mutex_map[module_list[i]].bit);        }        else        {            DDPDBG("module %s not added to mutex %d/n",ddp_get_module_name(module_list[i]),mutex_id);        }    }    DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_MOD(mutex_id),value);    DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_SOF(mutex_id),mode);    // for primary config thread, save more time for register config    if(gEnableMutexRisingEdge==1 && primary_display_is_video_mode()==1 && mutex_id==0)    {        DISP_REG_SET_FIELD(handle, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF, 1);    }    if(gEnableSWTrigger==1 && primary_display_is_video_mode()==1 && mutex_id==0)    {        // set OVL0/OVL1 to separate mutex        DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_MOD(DISP_OVL_SEPARATE_MUTEX_ID),value&((1 << module_mutex_map[DISP_MODULE_OVL0].bit)|(1 << module_mutex_map[DISP_MODULE_OVL1].bit)));        DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_SOF(DISP_OVL_SEPARATE_MUTEX_ID), SOF_SINGLE);        // move OVL0/OVL1 out from primary path        DISP_REG_SET(handle,DISP_REG_CONFIG_MUTEX_MOD(mutex_id),value&(~((1 << module_mutex_map[DISP_MODULE_OVL0].bit)|(1 << module_mutex_map[DISP_MODULE_OVL1].bit))));    }        DDPDBG("mutex %d value=0x%x, sof=%s/n",mutex_id, value, ddp_get_mutex_sof_name(mode));    return 0;}