自学教程：C++ rt2x00_desc_read函数代码示例

static void rt2400pci_clear_entry(struct queue_entry *entry){	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	u32 word;	if (entry->queue->qid == QID_RX) {		rt2x00_desc_read(entry_priv->desc, 2, &word);		rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);		rt2x00_desc_write(entry_priv->desc, 2, word);		rt2x00_desc_read(entry_priv->desc, 1, &word);		rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);		rt2x00_desc_write(entry_priv->desc, 1, word);		rt2x00_desc_read(entry_priv->desc, 0, &word);		rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);		rt2x00_desc_write(entry_priv->desc, 0, word);	} else {		rt2x00_desc_read(entry_priv->desc, 0, &word);		rt2x00_set_field32(&word, TXD_W0_VALID, 0);		rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);		rt2x00_desc_write(entry_priv->desc, 0, word);	}}

static void rt2800pci_clear_entry(struct queue_entry *entry){    struct queue_entry_priv_pci *entry_priv = entry->priv_data;    struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);    struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;    u32 word;    if (entry->queue->qid == QID_RX) {        rt2x00_desc_read(entry_priv->desc, 0, &word);        rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);        rt2x00_desc_write(entry_priv->desc, 0, word);        rt2x00_desc_read(entry_priv->desc, 1, &word);        rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);        rt2x00_desc_write(entry_priv->desc, 1, word);        /*         * Set RX IDX in register to inform hardware that we have         * handled this entry and it is available for reuse again.         */        rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,                                 entry->entry_idx);    } else {        rt2x00_desc_read(entry_priv->desc, 1, &word);        rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);        rt2x00_desc_write(entry_priv->desc, 1, word);    }}

static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue){	struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);	struct data_desc *txd;	unsigned int i;	u32 word;	memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));	for (i = 0; i < ring->stats.limit; i++) {		txd = ring->entry[i].priv;		rt2x00_desc_read(txd, 1, &word);		rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,				   ring->entry[i].data_dma);		rt2x00_desc_write(txd, 1, word);		rt2x00_desc_read(txd, 2, &word);		rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,				   ring->data_size);		rt2x00_desc_write(txd, 2, word);		rt2x00_desc_read(txd, 0, &word);		rt2x00_set_field32(&word, TXD_W0_VALID, 0);		rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);		rt2x00_desc_write(txd, 0, word);	}	rt2x00_ring_index_clear(ring);}

/* * Initialization functions. */static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev){	struct data_ring *ring = rt2x00dev->rx;	struct data_desc *rxd;	unsigned int i;	u32 word;	memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));	for (i = 0; i < ring->stats.limit; i++) {		rxd = ring->entry[i].priv;		rt2x00_desc_read(rxd, 2, &word);		rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,				   ring->data_size);		rt2x00_desc_write(rxd, 2, word);		rt2x00_desc_read(rxd, 1, &word);		rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,				   ring->entry[i].data_dma);		rt2x00_desc_write(rxd, 1, word);		rt2x00_desc_read(rxd, 0, &word);		rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);		rt2x00_desc_write(rxd, 0, word);	}	rt2x00_ring_index_clear(rt2x00dev->rx);}

/* * RX control handlers */static void rt2400pci_fill_rxdone(struct queue_entry *entry,				  struct rxdone_entry_desc *rxdesc){	struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;	u32 word0;	u32 word2;	u32 word3;	rt2x00_desc_read(priv_rx->desc, 0, &word0);	rt2x00_desc_read(priv_rx->desc, 2, &word2);	rt2x00_desc_read(priv_rx->desc, 3, &word3);	rxdesc->flags = 0;	if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;	if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))		rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;	/*	 * Obtain the status about this packet.	 * The signal is the PLCP value, and needs to be stripped	 * of the preamble bit (0x08).	 */	rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;	rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -	    entry->queue->rt2x00dev->rssi_offset;	rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);	rxdesc->dev_flags = RXDONE_SIGNAL_PLCP;	if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))		rxdesc->dev_flags |= RXDONE_MY_BSS;}

/* * RX control handlers */static void rt2400pci_fill_rxdone(struct data_entry *entry,				  struct rxdata_entry_desc *desc){	struct data_desc *rxd = entry->priv;	u32 word0;	u32 word2;	rt2x00_desc_read(rxd, 0, &word0);	rt2x00_desc_read(rxd, 2, &word2);	desc->flags = 0;	if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))		desc->flags |= RX_FLAG_FAILED_FCS_CRC;	if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))		desc->flags |= RX_FLAG_FAILED_PLCP_CRC;	/*	 * Obtain the status about this packet.	 */	desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);	desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -	    entry->ring->rt2x00dev->rssi_offset;	desc->ofdm = 0;	desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);}

static void rt2400pci_write_tx_desc(struct queue_entry *entry,				    struct txentry_desc *txdesc){	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	__le32 *txd = entry_priv->desc;	u32 word;	rt2x00_desc_read(txd, 1, &word);	rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);	rt2x00_desc_write(txd, 1, word);	rt2x00_desc_read(txd, 2, &word);	rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);	rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);	rt2x00_desc_write(txd, 2, word);	rt2x00_desc_read(txd, 3, &word);	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);	rt2x00_desc_write(txd, 3, word);	rt2x00_desc_read(txd, 4, &word);	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,			   txdesc->u.plcp.length_low);	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,			   txdesc->u.plcp.length_high);	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);	rt2x00_desc_write(txd, 4, word);	rt2x00_desc_read(txd, 0, &word);	rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);	rt2x00_set_field32(&word, TXD_W0_VALID, 1);	rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W0_ACK,			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W0_RTS,			   test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);	rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,			   test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));	rt2x00_desc_write(txd, 0, word);	skbdesc->desc = txd;	skbdesc->desc_len = TXD_DESC_SIZE;}

/* * RX control handlers */static void rt2400pci_fill_rxdone(struct queue_entry *entry,				  struct rxdone_entry_desc *rxdesc){	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	u32 word0;	u32 word2;	u32 word3;	u32 word4;	u64 tsf;	u32 rx_low;	u32 rx_high;	rt2x00_desc_read(entry_priv->desc, 0, &word0);	rt2x00_desc_read(entry_priv->desc, 2, &word2);	rt2x00_desc_read(entry_priv->desc, 3, &word3);	rt2x00_desc_read(entry_priv->desc, 4, &word4);	if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;	if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))		rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;	/*	 * We only get the lower 32bits from the timestamp,	 * to get the full 64bits we must complement it with	 * the timestamp from get_tsf().	 * Note that when a wraparound of the lower 32bits	 * has occurred between the frame arrival and the get_tsf()	 * call, we must decrease the higher 32bits with 1 to get	 * to correct value.	 */	tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);	rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);	rx_high = upper_32_bits(tsf);	if ((u32)tsf <= rx_low)		rx_high--;	/*	 * Obtain the status about this packet.	 * The signal is the PLCP value, and needs to be stripped	 * of the preamble bit (0x08).	 */	rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;	rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;	rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -	    entry->queue->rt2x00dev->rssi_offset;	rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);	rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;	if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))		rxdesc->dev_flags |= RXDONE_MY_BSS;}

static void rt2800pci_write_tx_desc(struct queue_entry *entry,				    struct txentry_desc *txdesc){	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	__le32 *txd = entry_priv->desc;	u32 word;	/*	 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1	 * must contains a TXWI structure + 802.11 header + padding + 802.11	 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and	 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11	 * data. It means that LAST_SEC0 is always 0.	 */	/*	 * Initialize TX descriptor	 */	rt2x00_desc_read(txd, 0, &word);	rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);	rt2x00_desc_write(txd, 0, word);	rt2x00_desc_read(txd, 1, &word);	rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);	rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,			   !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W1_BURST,			   test_bit(ENTRY_TXD_BURST, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);	rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);	rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);	rt2x00_desc_write(txd, 1, word);	rt2x00_desc_read(txd, 2, &word);	rt2x00_set_field32(&word, TXD_W2_SD_PTR1,			   skbdesc->skb_dma + TXWI_DESC_SIZE);	rt2x00_desc_write(txd, 2, word);	rt2x00_desc_read(txd, 3, &word);	rt2x00_set_field32(&word, TXD_W3_WIV,			   !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W3_QSEL, 2);	rt2x00_desc_write(txd, 3, word);	/*	 * Register descriptor details in skb frame descriptor.	 */	skbdesc->desc = txd;	skbdesc->desc_len = TXD_DESC_SIZE;}

/* * TX descriptor initialization */static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,				    struct sk_buff *skb,				    struct txentry_desc *txdesc,				    struct ieee80211_tx_control *control){	struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);	__le32 *txd = skbdesc->desc;	u32 word;	/*	 * Start writing the descriptor words.	 */	rt2x00_desc_read(txd, 2, &word);	rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);	rt2x00_desc_write(txd, 2, word);	rt2x00_desc_read(txd, 3, &word);	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);	rt2x00_desc_write(txd, 3, word);	rt2x00_desc_read(txd, 4, &word);	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);	rt2x00_desc_write(txd, 4, word);	rt2x00_desc_read(txd, 0, &word);	rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);	rt2x00_set_field32(&word, TXD_W0_VALID, 1);	rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W0_ACK,			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W0_RTS,			   test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));	rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);	rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,			   !!(control->flags &			      IEEE80211_TXCTL_LONG_RETRY_LIMIT));	rt2x00_desc_write(txd, 0, word);}

/* * Initialization functions. */static bool rt2800pci_get_entry_state(struct queue_entry *entry){	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	u32 word;	if (entry->queue->qid == QID_RX) {		rt2x00_desc_read(entry_priv->desc, 1, &word);		return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));	} else {		rt2x00_desc_read(entry_priv->desc, 1, &word);		return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));	}}

/* * Interrupt functions. */static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,			     const enum ieee80211_tx_queue queue_idx){	struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);	struct queue_entry_priv_pci_tx *priv_tx;	struct queue_entry *entry;	struct txdone_entry_desc txdesc;	u32 word;	while (!rt2x00queue_empty(queue)) {		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);		priv_tx = entry->priv_data;		rt2x00_desc_read(priv_tx->desc, 0, &word);		if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||		    !rt2x00_get_field32(word, TXD_W0_VALID))			break;		/*		 * Obtain the status about this packet.		 */		txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);		txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);		rt2x00pci_txdone(rt2x00dev, entry, &txdesc);	}}

static void rt2800usb_write_tx_desc(struct queue_entry *entry,				    struct txentry_desc *txdesc){	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	__le32 *txi = (__le32 *) entry->skb->data;	u32 word;	/*	 * Initialize TXINFO descriptor	 */	rt2x00_desc_read(txi, 0, &word);	/*	 * The size of TXINFO_W0_USB_DMA_TX_PKT_LEN is	 * TXWI + 802.11 header + L2 pad + payload + pad,	 * so need to decrease size of TXINFO and USB end pad.	 */	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,			   entry->skb->len - TXINFO_DESC_SIZE - 4);	rt2x00_set_field32(&word, TXINFO_W0_WIV,			   !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));	rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);	rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,			   test_bit(ENTRY_TXD_BURST, &txdesc->flags));	rt2x00_desc_write(txi, 0, word);	/*	 * Register descriptor details in skb frame descriptor.	 */	skbdesc->flags |= SKBDESC_DESC_IN_SKB;	skbdesc->desc = txi;	skbdesc->desc_len = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;}

/* * TX descriptor initialization */static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,				    struct sk_buff *skb,				    struct txentry_desc *txdesc){	struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);	__le32 *txi = (__le32 *)(skb->data - TXWI_DESC_SIZE - TXINFO_DESC_SIZE);	u32 word;	/*	 * Initialize TXWI descriptor	 */	rt2800_write_txwi(skb, txdesc);	/*	 * Initialize TXINFO descriptor	 */	rt2x00_desc_read(txi, 0, &word);	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,			   skb->len + TXWI_DESC_SIZE);	rt2x00_set_field32(&word, TXINFO_W0_WIV,			   !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));	rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);	rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,			   test_bit(ENTRY_TXD_BURST, &txdesc->flags));	rt2x00_desc_write(txi, 0, word);	/*	 * Register descriptor details in skb frame descriptor.	 */	skbdesc->desc = txi;	skbdesc->desc_len = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;}

static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,			     const enum data_queue_qid queue_idx){	struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);	struct queue_entry_priv_pci *entry_priv;	struct queue_entry *entry;	struct txdone_entry_desc txdesc;	u32 word;	while (!rt2x00queue_empty(queue)) {		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);		entry_priv = entry->priv_data;		rt2x00_desc_read(entry_priv->desc, 0, &word);		if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||		    !rt2x00_get_field32(word, TXD_W0_VALID))			break;		txdesc.flags = 0;		switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {		case 0: 		case 1: 			__set_bit(TXDONE_SUCCESS, &txdesc.flags);			break;		case 2: 			__set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);					default: 			__set_bit(TXDONE_FAILURE, &txdesc.flags);		}		txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);		rt2x00lib_txdone(entry, &txdesc);	}}

/* * TX data initialization */static void rt2400pci_write_beacon(struct queue_entry *entry){	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	u32 word;	u32 reg;	/*	 * Disable beaconing while we are reloading the beacon data,	 * otherwise we might be sending out invalid data.	 */	rt2x00pci_register_read(rt2x00dev, CSR14, &reg);	rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);	rt2x00_set_field32(&reg, CSR14_TBCN, 0);	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);	rt2x00pci_register_write(rt2x00dev, CSR14, reg);	/*	 * Replace rt2x00lib allocated descriptor with the	 * pointer to the _real_ hardware descriptor.	 * After that, map the beacon to DMA and update the	 * descriptor.	 */	memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);	skbdesc->desc = entry_priv->desc;	rt2x00queue_map_txskb(rt2x00dev, entry->skb);	rt2x00_desc_read(entry_priv->desc, 1, &word);	rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);	rt2x00_desc_write(entry_priv->desc, 1, word);}

/* * TX data initialization */static void rt2400pci_write_beacon(struct queue_entry *entry,				   struct txentry_desc *txdesc){	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	u32 word;	u32 reg;	/*	 * Disable beaconing while we are reloading the beacon data,	 * otherwise we might be sending out invalid data.	 */	rt2x00pci_register_read(rt2x00dev, CSR14, &reg);	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);	rt2x00pci_register_write(rt2x00dev, CSR14, reg);	rt2x00queue_map_txskb(rt2x00dev, entry->skb);	rt2x00_desc_read(entry_priv->desc, 1, &word);	rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);	rt2x00_desc_write(entry_priv->desc, 1, word);	/*	 * Enable beaconing again.	 */	rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);	rt2x00_set_field32(&reg, CSR14_TBCN, 1);	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);	rt2x00pci_register_write(rt2x00dev, CSR14, reg);}

/* * Initialization functions. */static bool rt2400pci_get_entry_state(struct queue_entry *entry){	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	u32 word;	if (entry->queue->qid == QID_RX) {		rt2x00_desc_read(entry_priv->desc, 0, &word);		return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);	} else {		rt2x00_desc_read(entry_priv->desc, 0, &word);		return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||		        rt2x00_get_field32(word, TXD_W0_VALID));	}}

/* * RX control handlers */void rt2800mmio_fill_rxdone(struct queue_entry *entry,			    struct rxdone_entry_desc *rxdesc){	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;	__le32 *rxd = entry_priv->desc;	u32 word;	word = rt2x00_desc_read(rxd, 3);	if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;	/*	 * Unfortunately we don't know the cipher type used during	 * decryption. This prevents us from correct providing	 * correct statistics through debugfs.	 */	rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);	if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {		/*		 * Hardware has stripped IV/EIV data from 802.11 frame during		 * decryption. Unfortunately the descriptor doesn't contain		 * any fields with the EIV/IV data either, so they can't		 * be restored by rt2x00lib.		 */		rxdesc->flags |= RX_FLAG_IV_STRIPPED;		/*		 * The hardware has already checked the Michael Mic and has		 * stripped it from the frame. Signal this to mac80211.		 */		rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;		if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) {			rxdesc->flags |= RX_FLAG_DECRYPTED;		} else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) {			/*			 * In order to check the Michael Mic, the packet must have			 * been decrypted.  Mac80211 doesnt check the MMIC failure 			 * flag to initiate MMIC countermeasures if the decoded flag			 * has not been set.			 */			rxdesc->flags |= RX_FLAG_DECRYPTED;			rxdesc->flags |= RX_FLAG_MMIC_ERROR;		}	}	if (rt2x00_get_field32(word, RXD_W3_MY_BSS))		rxdesc->dev_flags |= RXDONE_MY_BSS;	if (rt2x00_get_field32(word, RXD_W3_L2PAD))		rxdesc->dev_flags |= RXDONE_L2PAD;	/*	 * Process the RXWI structure that is at the start of the buffer.	 */	rt2800_process_rxwi(entry, rxdesc);}

/* * Initialization functions. */static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,				   struct queue_entry *entry){	struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;	u32 word;	rt2x00_desc_read(priv_rx->desc, 2, &word);	rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,			   entry->queue->data_size);	rt2x00_desc_write(priv_rx->desc, 2, word);	rt2x00_desc_read(priv_rx->desc, 1, &word);	rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);	rt2x00_desc_write(priv_rx->desc, 1, word);	rt2x00_desc_read(priv_rx->desc, 0, &word);	rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);	rt2x00_desc_write(priv_rx->desc, 0, word);}

static void rt2800pci_clear_entry(struct queue_entry *entry){	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	u32 word;	if (entry->queue->qid == QID_RX) {		rt2x00_desc_read(entry_priv->desc, 0, &word);		rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);		rt2x00_desc_write(entry_priv->desc, 0, word);		rt2x00_desc_read(entry_priv->desc, 1, &word);		rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);		rt2x00_desc_write(entry_priv->desc, 1, word);	} else {		rt2x00_desc_read(entry_priv->desc, 1, &word);		rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);		rt2x00_desc_write(entry_priv->desc, 1, word);	}}

static void rt2400pci_fill_rxdone(struct queue_entry *entry,				  struct rxdone_entry_desc *rxdesc){	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	u32 word0;	u32 word2;	u32 word3;	u32 word4;	u64 tsf;	u32 rx_low;	u32 rx_high;	rt2x00_desc_read(entry_priv->desc, 0, &word0);	rt2x00_desc_read(entry_priv->desc, 2, &word2);	rt2x00_desc_read(entry_priv->desc, 3, &word3);	rt2x00_desc_read(entry_priv->desc, 4, &word4);	if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;	if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))		rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;	tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);	rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);	rx_high = upper_32_bits(tsf);	if ((u32)tsf <= rx_low)		rx_high--;	rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;	rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;	rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -	    entry->queue->rt2x00dev->rssi_offset;	rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);	rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;	if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))		rxdesc->dev_flags |= RXDONE_MY_BSS;}

/* * TX control handlers */static bool rt2800usb_txdone_entry_check(struct queue_entry *entry, u32 reg){	__le32 *txwi;	u32 word;	int wcid, ack, pid;	int tx_wcid, tx_ack, tx_pid;	if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||	    !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) {		WARNING(entry->queue->rt2x00dev,			"Data pending for entry %u in queue %u/n",			entry->entry_idx, entry->queue->qid);		cond_resched();		return false;	}	wcid	= rt2x00_get_field32(reg, TX_STA_FIFO_WCID);	ack	= rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);	pid	= rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);	/*	 * This frames has returned with an IO error,	 * so the status report is not intended for this	 * frame.	 */	if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {		rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);		return false;	}	/*	 * Validate if this TX status report is intended for	 * this entry by comparing the WCID/ACK/PID fields.	 */	txwi = rt2800usb_get_txwi(entry);	rt2x00_desc_read(txwi, 1, &word);	tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);	tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);	tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);	if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {		WARNING(entry->queue->rt2x00dev,			"TX status report missed for queue %d entry %d/n",		entry->queue->qid, entry->entry_idx);		rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);		return false;	}	return true;}

/* * Interrupt functions. */static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue){	struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);	struct data_entry *entry;	struct data_desc *txd;	u32 word;	int tx_status;	int retry;	while (!rt2x00_ring_empty(ring)) {		entry = rt2x00_get_data_entry_done(ring);		txd = entry->priv;		rt2x00_desc_read(txd, 0, &word);		if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||		    !rt2x00_get_field32(word, TXD_W0_VALID))			break;		/*		 * Obtain the status about this packet.		 */		tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);		retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);		rt2x00lib_txdone(entry, tx_status, retry);		/*		 * Make this entry available for reuse.		 */		entry->flags = 0;		rt2x00_set_field32(&word, TXD_W0_VALID, 0);		rt2x00_desc_write(txd, 0, word);		rt2x00_ring_index_done_inc(ring);	}	/*	 * If the data ring was full before the txdone handler	 * we must make sure the packet queue in the mac80211 stack	 * is reenabled when the txdone handler has finished.	 */	entry = ring->entry;	if (!rt2x00_ring_full(ring))		ieee80211_wake_queue(rt2x00dev->hw,				     entry->tx_status.control.queue);}

/* * TX data handlers. */static void rt2x00usb_interrupt_txdone(struct urb *urb){	struct queue_entry *entry = (struct queue_entry *)urb->context;	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;	struct queue_entry_priv_usb_tx *priv_tx = entry->priv_data;	struct txdone_entry_desc txdesc;	__le32 *txd = (__le32 *)entry->skb->data;	u32 word;	if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags) ||	    !__test_and_clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))		return;	rt2x00_desc_read(txd, 0, &word);	/*	 * Remove the descriptor data from the buffer.	 */	skb_pull(entry->skb, entry->queue->desc_size);	/*	 * Obtain the status about this packet.	 */	txdesc.status = !urb->status ? TX_SUCCESS : TX_FAIL_RETRY;	txdesc.retry = 0;	txdesc.control = &priv_tx->control;	rt2x00lib_txdone(entry, &txdesc);	/*	 * Make this entry available for reuse.	 */	entry->flags = 0;	rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);	/*	 * If the data queue was full before the txdone handler	 * we must make sure the packet queue in the mac80211 stack	 * is reenabled when the txdone handler has finished.	 */	if (!rt2x00queue_full(entry->queue))		ieee80211_wake_queue(rt2x00dev->hw, priv_tx->control.queue);}

/* * Interrupt functions. */static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev){	struct ieee80211_conf conf = { .flags = 0 };	struct rt2x00lib_conf libconf = { .conf = &conf };	rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);}static bool rt2800pci_txdone_entry_check(struct queue_entry *entry, u32 status){	__le32 *txwi;	u32 word;	int wcid, tx_wcid;	wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);	txwi = rt2800_drv_get_txwi(entry);	rt2x00_desc_read(txwi, 1, &word);	tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);	return (tx_wcid == wcid);}

/* * Interrupt functions. */static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,			     const enum data_queue_qid queue_idx){	struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);	struct queue_entry_priv_pci *entry_priv;	struct queue_entry *entry;	struct txdone_entry_desc txdesc;	u32 word;	while (!rt2x00queue_empty(queue)) {		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);		entry_priv = entry->priv_data;		rt2x00_desc_read(entry_priv->desc, 0, &word);		if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||		    !rt2x00_get_field32(word, TXD_W0_VALID))			break;		/*		 * Obtain the status about this packet.		 */		txdesc.flags = 0;		switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {		case 0: /* Success */		case 1: /* Success with retry */			__set_bit(TXDONE_SUCCESS, &txdesc.flags);			break;		case 2: /* Failure, excessive retries */			__set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);			/* Don't break, this is a failed frame! */		default: /* Failure */			__set_bit(TXDONE_FAILURE, &txdesc.flags);		}		txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);		rt2x00lib_txdone(entry, &txdesc);	}}

/* * Interrupt functions. */static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev){	struct data_queue *queue;	struct queue_entry *entry;	struct queue_entry *entry_done;	struct queue_entry_priv_pci *entry_priv;	struct txdone_entry_desc txdesc;	u32 word;	u32 reg;	u32 old_reg;	unsigned int type;	unsigned int index;	u16 mcs, real_mcs;	/*	 * During each loop we will compare the freshly read	 * TX_STA_FIFO register value with the value read from	 * the previous loop. If the 2 values are equal then	 * we should stop processing because the chance it	 * quite big that the device has been unplugged and	 * we risk going into an endless loop.	 */	old_reg = 0;	while (1) {		rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);		if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))			break;		if (old_reg == reg)			break;		old_reg = reg;		/*		 * Skip this entry when it contains an invalid		 * queue identication number.		 */		type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;		if (type >= QID_RX)			continue;		queue = rt2x00queue_get_queue(rt2x00dev, type);		if (unlikely(!queue))			continue;		/*		 * Skip this entry when it contains an invalid		 * index number.		 */		index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;		if (unlikely(index >= queue->limit))			continue;		entry = &queue->entries[index];		entry_priv = entry->priv_data;		rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);		entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);		while (entry != entry_done) {			/*			 * Catch up.			 * Just report any entries we missed as failed.			 */			WARNING(rt2x00dev,				"TX status report missed for entry %d/n",				entry_done->entry_idx);			txdesc.flags = 0;			__set_bit(TXDONE_UNKNOWN, &txdesc.flags);			txdesc.retry = 0;			rt2x00lib_txdone(entry_done, &txdesc);			entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);		}		/*		 * Obtain the status about this packet.		 */		txdesc.flags = 0;		if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))			__set_bit(TXDONE_SUCCESS, &txdesc.flags);		else			__set_bit(TXDONE_FAILURE, &txdesc.flags);		/*		 * Ralink has a retry mechanism using a global fallback		 * table. We setup this fallback table to try immediate		 * lower rate for all rates. In the TX_STA_FIFO,		 * the MCS field contains the MCS used for the successfull		 * transmission. If the first transmission succeed,		 * we have mcs == tx_mcs. On the second transmission,		 * we have mcs = tx_mcs - 1. So the number of		 * retry is (tx_mcs - mcs).		 */		mcs = rt2x00_get_field32(word, TXWI_W0_MCS);		real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);		__set_bit(TXDONE_FALLBACK, &txdesc.flags);//.........这里部分代码省略.........

/* * RX control handlers */static void rt2800pci_fill_rxdone(struct queue_entry *entry,				  struct rxdone_entry_desc *rxdesc){	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	__le32 *rxd = entry_priv->desc;	__le32 *rxwi = (__le32 *)entry->skb->data;	u32 rxd3;	u32 rxwi0;	u32 rxwi1;	u32 rxwi2;	u32 rxwi3;	rt2x00_desc_read(rxd, 3, &rxd3);	rt2x00_desc_read(rxwi, 0, &rxwi0);	rt2x00_desc_read(rxwi, 1, &rxwi1);	rt2x00_desc_read(rxwi, 2, &rxwi2);	rt2x00_desc_read(rxwi, 3, &rxwi3);	if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;	if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {		/*		 * Unfortunately we don't know the cipher type used during		 * decryption. This prevents us from correct providing		 * correct statistics through debugfs.		 */		rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);		rxdesc->cipher_status =		    rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);	}	if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {		/*		 * Hardware has stripped IV/EIV data from 802.11 frame during		 * decryption. Unfortunately the descriptor doesn't contain		 * any fields with the EIV/IV data either, so they can't		 * be restored by rt2x00lib.		 */		rxdesc->flags |= RX_FLAG_IV_STRIPPED;		if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)			rxdesc->flags |= RX_FLAG_DECRYPTED;		else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)			rxdesc->flags |= RX_FLAG_MMIC_ERROR;	}	if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))		rxdesc->dev_flags |= RXDONE_MY_BSS;	if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) {		rxdesc->dev_flags |= RXDONE_L2PAD;		skbdesc->flags |= SKBDESC_L2_PADDED;	}	if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))		rxdesc->flags |= RX_FLAG_SHORT_GI;	if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))		rxdesc->flags |= RX_FLAG_40MHZ;	/*	 * Detect RX rate, always use MCS as signal type.	 */	rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;	rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);	rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);	/*	 * Mask of 0x8 bit to remove the short preamble flag.	 */	if (rxdesc->rate_mode == RATE_MODE_CCK)		rxdesc->signal &= ~0x8;	rxdesc->rssi =	    (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +	     rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;	rxdesc->noise =	    (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +	     rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;	rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);	/*	 * Set RX IDX in register to inform hardware that we have handled	 * this entry and it is available for reuse again.	 */	rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);	/*	 * Remove TXWI descriptor from start of buffer.	 */	skb_pull(entry->skb, RXWI_DESC_SIZE);	skb_trim(entry->skb, rxdesc->size);//.........这里部分代码省略.........