自学教程：C++ rt2x00_set_field32函数代码示例

static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,				     struct rf_channel *rf){	/*	 * Switch on tuning bits.	 */	rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);	rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);	/*	 * RF2420 chipset don't need any additional actions.	 */	if (rt2x00_rf(rt2x00dev, RF2420))		return;	/*	 * For the RT2421 chipsets we need to write an invalid	 * reference clock rate to activate auto_tune.	 * After that we set the value back to the correct channel.	 */	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);	rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);	msleep(1);	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);	rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);	msleep(1);	/*	 * Switch off tuning bits.	 */	rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);	/*	 * Clear false CRC during channel switch.	 */	rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);}

static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom){	struct rt2x00_dev *rt2x00dev = eeprom->data;	u32 reg = 0;	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,			   !!eeprom->reg_data_clock);	rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,			   !!eeprom->reg_chip_select);	rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);}

static int rt2400pci_blink_set(struct led_classdev *led_cdev,			       unsigned long *delay_on,			       unsigned long *delay_off){	struct rt2x00_led *led =	    container_of(led_cdev, struct rt2x00_led, led_dev);	u32 reg;	rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);	rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);	rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);	rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);	return 0;}

static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev){	u32 reg;	u16 word;	/*	 * Initialize all registers.	 */	if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||		     rt2800pci_init_queues(rt2x00dev) ||		     rt2800_init_registers(rt2x00dev) ||		     rt2800pci_wait_wpdma_ready(rt2x00dev) ||		     rt2800_init_bbp(rt2x00dev) ||		     rt2800_init_rfcsr(rt2x00dev)))		return -EIO;	/*	 * Send signal to firmware during boot time.	 */	rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);	/*	 * Enable RX.	 */	rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);	rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);	rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);	/*	 * Initialize LED control	 */	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);	rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,			      word & 0xff, (word >> 8) & 0xff);	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);	rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,			      word & 0xff, (word >> 8) & 0xff);	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);	rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,			      word & 0xff, (word >> 8) & 0xff);	return 0;}

/* * TX data initialization */static void rt2800pci_write_beacon(struct queue_entry *entry){	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	unsigned int beacon_base;	u32 reg;	/*	 * Disable beaconing while we are reloading the beacon data,	 * otherwise we might be sending out invalid data.	 */	rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);	/*	 * Write entire beacon with descriptor to register.	 */	beacon_base = HW_BEACON_OFFSET(entry->entry_idx);	rt2800_register_multiwrite(rt2x00dev,				      beacon_base,				      skbdesc->desc, skbdesc->desc_len);	rt2800_register_multiwrite(rt2x00dev,				      beacon_base + skbdesc->desc_len,				      entry->skb->data, entry->skb->len);	/*	 * Clean up beacon skb.	 */	dev_kfree_skb_any(entry->skb);	entry->skb = NULL;}

static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,                                    const u8 *data, const size_t len){    u32 reg;    /*     * enable Host program ram write selection     */    reg = 0;    rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);    rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);    /*     * Write firmware to device.     */    rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,                                  data, len);    rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);    rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);    rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);    rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);    return 0;}

static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev){	u32 reg;	/*	 * Disable LED	 */	rt2400pci_disable_led(rt2x00dev);	rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);	/*	 * Disable synchronisation.	 */	rt2x00pci_register_write(rt2x00dev, CSR14, 0);	/*	 * Cancel RX and TX.	 */	rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);	rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);	rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);	/*	 * Disable interrupts.	 */	rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);}

static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,				    const enum data_queue_qid qid){	u32 reg;	if (qid == QID_BEACON) {		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);		return;	}	rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));	rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);}

static void rt2400pci_brightness_set(struct led_classdev *led_cdev,				     enum led_brightness brightness){	struct rt2x00_led *led =	    container_of(led_cdev, struct rt2x00_led, led_dev);	unsigned int enabled = brightness != LED_OFF;	u32 reg;	rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);	if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)		rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);	else if (led->type == LED_TYPE_ACTIVITY)		rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);	rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);}

static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,				      struct rt2x00lib_conf *libconf){	u32 reg;	rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);	rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);	rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);	rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);	rt2x00pci_register_read(rt2x00dev, CSR12, &reg);	rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,			   libconf->conf->beacon_int * 16);	rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,			   libconf->conf->beacon_int * 16);	rt2x00pci_register_write(rt2x00dev, CSR12, reg);}

static voidrt2x00_dev_update_led(struct _rt2x00_pci *rt2x00pci, struct _rt2x00_config *config) {    u32			reg = 0x00000000;    rt2x00_register_read(rt2x00pci, LEDCSR, &reg);    rt2x00_set_field32(&reg, LEDCSR_LINK, config->led_status ? 1 : 0);    rt2x00_register_write(rt2x00pci, LEDCSR, reg);}

static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,				    const enum data_queue_qid queue){	u32 reg;	if (queue != QID_BEACON) {		rt2x00usb_kick_tx_queue(rt2x00dev, queue);		return;	}	rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);	if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);		rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);	}}

static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev){	u32 reg;	rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);	rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);	/* Wait for DMA, ignore error */	rt2800_wait_wpdma_ready(rt2x00dev);	rt2x00usb_disable_radio(rt2x00dev);}

/* * TX data initialization */static void rt2800usb_write_beacon(struct queue_entry *entry,				   struct txentry_desc *txdesc){	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;	unsigned int beacon_base;	u32 reg;	/*	 * Disable beaconing while we are reloading the beacon data,	 * otherwise we might be sending out invalid data.	 */	rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);	/*	 * Add the TXWI for the beacon to the skb.	 */	rt2800_write_txwi(entry->skb, txdesc);	skb_push(entry->skb, TXWI_DESC_SIZE);	/*	 * Write entire beacon with descriptor to register.	 */	beacon_base = HW_BEACON_OFFSET(entry->entry_idx);	rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,					    USB_VENDOR_REQUEST_OUT, beacon_base,					    entry->skb->data, entry->skb->len,					    REGISTER_TIMEOUT32(entry->skb->len));	/*	 * Enable beaconing again.	 */	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);	rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);	/*	 * Clean up the beacon skb.	 */	dev_kfree_skb(entry->skb);	entry->skb = NULL;}

static void rt2400pci_write_beacon(struct queue_entry *entry,				   struct txentry_desc *txdesc){	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;	u32 reg;	rt2x00pci_register_read(rt2x00dev, CSR14, &reg);	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);	rt2x00pci_register_write(rt2x00dev, CSR14, reg);	rt2x00queue_map_txskb(entry);	rt2400pci_write_tx_desc(entry, txdesc);	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);	rt2x00pci_register_write(rt2x00dev, CSR14, reg);}

/* * Initialization functions. */static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,				   struct queue_entry *entry){	struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;	u32 word;	rt2x00_desc_read(priv_rx->desc, 2, &word);	rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,			   entry->queue->data_size);	rt2x00_desc_write(priv_rx->desc, 2, word);	rt2x00_desc_read(priv_rx->desc, 1, &word);	rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);	rt2x00_desc_write(priv_rx->desc, 1, word);	rt2x00_desc_read(priv_rx->desc, 0, &word);	rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);	rt2x00_desc_write(priv_rx->desc, 0, word);}

static voidrt2x00_dev_update_txpower(struct _rt2x00_pci *rt2x00pci, struct _rt2x00_config *config) {    u8			txpower = rt2x00_get_txpower(&rt2x00pci->chip, config->txpower);      DEBUG("Start./n");    rt2x00_set_field32(&rt2x00pci->channel.rf3, RF3_TXPOWER, txpower);    rt2x00_rf_regwrite(rt2x00pci, rt2x00pci->channel.rf3);}

/* * Device state switch handlers. */static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,				enum dev_state state){	u32 reg;	rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);	rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,			   state == STATE_RADIO_RX_OFF);	rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);}

static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance){	struct rt2x00_dev *rt2x00dev = dev_instance;	u32 reg, mask;	rt2x00pci_register_read(rt2x00dev, CSR7, &reg);	rt2x00pci_register_write(rt2x00dev, CSR7, reg);	if (!reg)		return IRQ_NONE;	if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))		return IRQ_HANDLED;	mask = reg;	if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))		tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);	if (rt2x00_get_field32(reg, CSR7_RXDONE))		tasklet_schedule(&rt2x00dev->rxdone_tasklet);	if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||	    rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||	    rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {		tasklet_schedule(&rt2x00dev->txstatus_tasklet);		rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);		rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);		rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);	}	spin_lock(&rt2x00dev->irqmask_lock);	rt2x00pci_register_read(rt2x00dev, CSR8, &reg);	reg |= mask;	rt2x00pci_register_write(rt2x00dev, CSR8, reg);	spin_unlock(&rt2x00dev->irqmask_lock);	return IRQ_HANDLED;}

static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,				const unsigned int word, const u8 value){	u32 reg;	mutex_lock(&rt2x00dev->csr_mutex);	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {		reg = 0;		rt2x00_set_field32(&reg, BBPCSR_VALUE, value);		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);		rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);	}	mutex_unlock(&rt2x00dev->csr_mutex);}

static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance){	struct rt2x00_dev *rt2x00dev = dev_instance;	u32 reg, mask;	unsigned long flags;	/* Read status and ACK all interrupts */	rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);	rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);	if (!reg)		return IRQ_NONE;	if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))		return IRQ_HANDLED;	/*	 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits	 * for interrupts and interrupt masks we can just use the value of	 * INT_SOURCE_CSR to create the interrupt mask.	 */	mask = ~reg;	if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {		rt2800pci_txstatus_interrupt(rt2x00dev);		/*		 * Never disable the TX_FIFO_STATUS interrupt.		 */		rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);	}	if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))		tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);	if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))		tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);	if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))		tasklet_schedule(&rt2x00dev->rxdone_tasklet);	if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))		tasklet_schedule(&rt2x00dev->autowake_tasklet);	/*	 * Disable all interrupts for which a tasklet was scheduled right now,	 * the tasklet will reenable the appropriate interrupts.	 */	spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);	rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);	reg &= mask;	rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);	spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);	return IRQ_HANDLED;}

/* * Device state switch handlers. */static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,				enum dev_state state){	u32 reg;	rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,			   (state == STATE_RADIO_RX_ON) ||			   (state == STATE_RADIO_RX_ON_LINK));	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);}

static void rt2800pci_clear_entry(struct queue_entry *entry){	struct queue_entry_priv_pci *entry_priv = entry->priv_data;	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	u32 word;	if (entry->queue->qid == QID_RX) {		rt2x00_desc_read(entry_priv->desc, 0, &word);		rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);		rt2x00_desc_write(entry_priv->desc, 0, word);		rt2x00_desc_read(entry_priv->desc, 1, &word);		rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);		rt2x00_desc_write(entry_priv->desc, 1, word);	} else {		rt2x00_desc_read(entry_priv->desc, 1, &word);		rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);		rt2x00_desc_write(entry_priv->desc, 1, word);	}}

static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,			       const unsigned int word, const u32 value){	u32 reg;	mutex_lock(&rt2x00dev->csr_mutex);	if (WAIT_FOR_RF(rt2x00dev, &reg)) {		reg = 0;		rt2x00_set_field32(&reg, RFCSR_VALUE, value);		rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);		rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);		rt2x00_set_field32(&reg, RFCSR_BUSY, 1);		rt2x00pci_register_write(rt2x00dev, RFCSR, reg);		rt2x00_rf_write(rt2x00dev, word, value);	}	mutex_unlock(&rt2x00dev->csr_mutex);}

static void rt2400pci_txstatus_tasklet(unsigned long data){	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;	u32 reg;	rt2400pci_txdone(rt2x00dev, QID_ATIM);	rt2400pci_txdone(rt2x00dev, QID_AC_VO);	rt2400pci_txdone(rt2x00dev, QID_AC_VI);	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {		spin_lock_irq(&rt2x00dev->irqmask_lock);		rt2x00pci_register_read(rt2x00dev, CSR8, &reg);		rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);		rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);		rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);		rt2x00pci_register_write(rt2x00dev, CSR8, reg);		spin_unlock_irq(&rt2x00dev->irqmask_lock);	}}

/* * Configuration handlers. */static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,				    const unsigned int filter_flags){	u32 reg;	/*	 * Start configuration steps.	 * Note that the version error will always be dropped	 * since there is no filter for it at this time.	 */	rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);	rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,			   !(filter_flags & FIF_FCSFAIL));	rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,			   !(filter_flags & FIF_PLCPFAIL));	rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,			   !(filter_flags & FIF_CONTROL));	rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,			   !(filter_flags & FIF_PROMISC_IN_BSS));	rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,			   !(filter_flags & FIF_PROMISC_IN_BSS) &&			   !rt2x00dev->intf_ap_count);	rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);	rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);}

/* * TX data initialization */static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,				    const unsigned int queue){	u32 reg;	if (queue == RT2X00_BCN_QUEUE_BEACON) {		rt2x00pci_register_read(rt2x00dev, CSR14, &reg);		if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {			rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);			rt2x00_set_field32(&reg, CSR14_TBCN, 1);			rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);			rt2x00pci_register_write(rt2x00dev, CSR14, reg);		}		return;	}	rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);	rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,			   (queue == IEEE80211_TX_QUEUE_DATA0));	rt2x00_set_field32(&reg, TXCSR0_KICK_TX,			   (queue == IEEE80211_TX_QUEUE_DATA1));	rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,			   (queue == RT2X00_BCN_QUEUE_ATIM));	rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);}

/* * TX descriptor initialization */static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,				    struct sk_buff *skb,				    struct txentry_desc *txdesc){	struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);	__le32 *txi = (__le32 *)(skb->data - TXWI_DESC_SIZE - TXINFO_DESC_SIZE);	u32 word;	/*	 * Initialize TXWI descriptor	 */	rt2800_write_txwi(skb, txdesc);	/*	 * Initialize TXINFO descriptor	 */	rt2x00_desc_read(txi, 0, &word);	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,			   skb->len + TXWI_DESC_SIZE);	rt2x00_set_field32(&word, TXINFO_W0_WIV,			   !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));	rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);	rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,			   test_bit(ENTRY_TXD_BURST, &txdesc->flags));	rt2x00_desc_write(txi, 0, word);	/*	 * Register descriptor details in skb frame descriptor.	 */	skbdesc->desc = txi;	skbdesc->desc_len = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;}

static void rt2800usb_write_tx_desc(struct queue_entry *entry,				    struct txentry_desc *txdesc){	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);	__le32 *txi = (__le32 *) entry->skb->data;	u32 word;	/*	 * Initialize TXINFO descriptor	 */	rt2x00_desc_read(txi, 0, &word);	/*	 * The size of TXINFO_W0_USB_DMA_TX_PKT_LEN is	 * TXWI + 802.11 header + L2 pad + payload + pad,	 * so need to decrease size of TXINFO and USB end pad.	 */	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,			   entry->skb->len - TXINFO_DESC_SIZE - 4);	rt2x00_set_field32(&word, TXINFO_W0_WIV,			   !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));	rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);	rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,			   test_bit(ENTRY_TXD_BURST, &txdesc->flags));	rt2x00_desc_write(txi, 0, word);	/*	 * Register descriptor details in skb frame descriptor.	 */	skbdesc->flags |= SKBDESC_DESC_IN_SKB;	skbdesc->desc = txi;	skbdesc->desc_len = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;}

static void rt2400pci_kill_tx_queue(struct data_queue *queue){	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;	u32 reg;	if (queue->qid == QID_BEACON) {		rt2x00pci_register_write(rt2x00dev, CSR14, 0);	} else {		rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);		rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);		rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);	}}