自学教程：C++ snd_soc_codec_set_cache_io函数代码示例

static int cs4271_probe(struct snd_soc_codec *codec){	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);	struct cs4271_platform_data *cs4271plat = codec->dev->platform_data;	int ret;	int gpio_nreset = -EINVAL;	codec->control_data = cs4271->control_data;	if (cs4271plat && gpio_is_valid(cs4271plat->gpio_nreset))		gpio_nreset = cs4271plat->gpio_nreset;	if (gpio_nreset >= 0)		if (gpio_request(gpio_nreset, "CS4271 Reset"))			gpio_nreset = -EINVAL;	if (gpio_nreset >= 0) {		/* Reset codec */		gpio_direction_output(gpio_nreset, 0);		udelay(1);		gpio_set_value(gpio_nreset, 1);		/* Give the codec time to wake up */		udelay(1);	}	cs4271->gpio_nreset = gpio_nreset;	/*	 * In case of I2C, chip address specified in board data.	 * So cache IO operations use 8 bit codec register address.	 * In case of SPI, chip address and register address	 * passed together as 16 bit value.	 * Anyway, register address is masked with 0xFF inside	 * soc-cache code.	 */	if (cs4271->bus_type == SND_SOC_SPI)		ret = snd_soc_codec_set_cache_io(codec, 16, 8,			cs4271->bus_type);	else		ret = snd_soc_codec_set_cache_io(codec, 8, 8,			cs4271->bus_type);	if (ret) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	ret = snd_soc_update_bits(codec, CS4271_MODE2, 0,		CS4271_MODE2_PDN | CS4271_MODE2_CPEN);	if (ret < 0)		return ret;	ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0);	if (ret < 0)		return ret;	/* Power-up sequence requires 85 uS */	udelay(85);	return snd_soc_add_controls(codec, cs4271_snd_controls,		ARRAY_SIZE(cs4271_snd_controls));}

static int cs4271_probe(struct snd_soc_codec *codec){	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);	struct cs4271_platform_data *cs4271plat = codec->dev->platform_data;	int ret;	int gpio_nreset = -EINVAL;	if (cs4271plat && gpio_is_valid(cs4271plat->gpio_nreset))		gpio_nreset = cs4271plat->gpio_nreset;	if (gpio_nreset >= 0)		if (gpio_request(gpio_nreset, "CS4271 Reset"))			gpio_nreset = -EINVAL;	if (gpio_nreset >= 0) {				gpio_direction_output(gpio_nreset, 0);		udelay(1);		gpio_set_value(gpio_nreset, 1);				udelay(1);	}	cs4271->gpio_nreset = gpio_nreset;	if (cs4271->bus_type == SND_SOC_SPI)		ret = snd_soc_codec_set_cache_io(codec, 16, 8,			cs4271->bus_type);	else		ret = snd_soc_codec_set_cache_io(codec, 8, 8,			cs4271->bus_type);	if (ret) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	ret = snd_soc_update_bits(codec, CS4271_MODE2,				  CS4271_MODE2_PDN | CS4271_MODE2_CPEN,				  CS4271_MODE2_PDN | CS4271_MODE2_CPEN);	if (ret < 0)		return ret;	ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0);	if (ret < 0)		return ret;		udelay(85);	return snd_soc_add_codec_controls(codec, cs4271_snd_controls,		ARRAY_SIZE(cs4271_snd_controls));}

static int aml_pmu4_audio_probe(struct snd_soc_codec *codec){    struct aml_pmu4_audio_priv *pmu4_audio = NULL;    printk("enter %s/n",__func__);	pmu4_audio = kzalloc(sizeof(struct aml_pmu4_audio_priv), GFP_KERNEL);    if (NULL == pmu4_audio)        return -ENOMEM;	snd_soc_codec_set_drvdata(codec,pmu4_audio);#if 0    ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);    if (ret != 0) {        dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);        return ret;    }#endif		//enable LDO1V8 for audio	aml_pmu4_audio_power_init();  	//reset audio codec register    aml_pmu4_audio_reset(codec);	aml_pmu4_audio_start_up(codec);    aml_pmu4_audio_reg_init(codec);    codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;    pmu4_audio->codec = codec;    return 0;}

static int cs42l51_probe(struct snd_soc_codec *codec){	struct cs42l51_private *cs42l51 = snd_soc_codec_get_drvdata(codec);	int ret, reg;	ret = cs42l51_fill_cache(codec);	if (ret < 0) {		dev_err(codec->dev, "failed to fill register cache/n");		return ret;	}	ret = snd_soc_codec_set_cache_io(codec, 8, 8, cs42l51->control_type);	if (ret < 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	reg = CS42L51_DAC_CTL_DATA_SEL(1)		| CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0);	ret = snd_soc_write(codec, CS42L51_DAC_CTL, reg);	if (ret < 0)		return ret;	return 0;}

static int cs42l51_probe(struct snd_soc_codec *codec){	struct cs42l51_private *cs42l51 = snd_soc_codec_get_drvdata(codec);	int ret, reg;	ret = cs42l51_fill_cache(codec);	if (ret < 0) {		dev_err(codec->dev, "failed to fill register cache/n");		return ret;	}	ret = snd_soc_codec_set_cache_io(codec, 8, 8, cs42l51->control_type);	if (ret < 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	/*	 * DAC configuration	 * - Use signal processor	 * - auto mute	 * - vol changes immediate	 * - no de-emphasize	 */	reg = CS42L51_DAC_CTL_DATA_SEL(1)		| CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0);	ret = snd_soc_write(codec, CS42L51_DAC_CTL, reg);	if (ret < 0)		return ret;	return 0;}

static int wm8988_probe(struct snd_soc_codec *codec){	struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);	struct snd_soc_dapm_context *dapm = &codec->dapm;	int ret = 0;	ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8988->control_type);	if (ret < 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	ret = wm8988_reset(codec);	if (ret < 0) {		dev_err(codec->dev, "Failed to issue reset/n");		return ret;	}	/* set the update bits (we always update left then right) */	snd_soc_update_bits(codec, WM8988_RADC, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8988_RDAC, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8988_ROUT1V, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8988_ROUT2V, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8988_RINVOL, 0x0100, 0x0100);	wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	snd_soc_add_controls(codec, wm8988_snd_controls,				ARRAY_SIZE(wm8988_snd_controls));	snd_soc_dapm_new_controls(dapm, wm8988_dapm_widgets,				  ARRAY_SIZE(wm8988_dapm_widgets));	snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));	return 0;}

static int wm8776_probe(struct snd_soc_codec *codec){	struct wm8776_priv *wm8776 = snd_soc_codec_get_drvdata(codec);	int ret = 0;	ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8776->control_type);	if (ret < 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	ret = wm8776_reset(codec);	if (ret < 0) {		dev_err(codec->dev, "Failed to issue reset: %d/n", ret);		return ret;	}	wm8776_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	/* Latch the update bits; right channel only since we always	 * update both. */	snd_soc_update_bits(codec, WM8776_HPRVOL, 0x100, 0x100);	snd_soc_update_bits(codec, WM8776_DACRVOL, 0x100, 0x100);	return ret;}

static int wm5110_codec_probe(struct snd_soc_codec *codec){	struct wm5110_priv *priv = snd_soc_codec_get_drvdata(codec);	codec->control_data = priv->core.arizona->regmap;	return snd_soc_codec_set_cache_io(codec, 32, 16, SND_SOC_REGMAP);}

static int cs42l73_probe(struct snd_soc_codec *codec){	int ret;	struct cs42l73_private *cs42l73 = snd_soc_codec_get_drvdata(codec);	codec->control_data = cs42l73->regmap;	ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);	if (ret < 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	cs42l73_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	/* Set Charge Pump Frequency */	if (cs42l73->pdata.chgfreq)		snd_soc_update_bits(codec, CS42L73_CPFCHC,				    CS42L73_CHARGEPUMP_MASK,					cs42l73->pdata.chgfreq << 4);	/* MCLK1 as master clk */	cs42l73->mclksel = CS42L73_CLKID_MCLK1;	cs42l73->mclk = 0;	return ret;}

static int tas5707_probe(struct snd_soc_codec *codec){	int ret = 0;	struct tas5707_priv *tas5707 = snd_soc_codec_get_drvdata(codec);	struct tas57xx_platform_data *pdata = dev_get_platdata(codec->dev);#ifdef CONFIG_HAS_EARLYSUSPEND        early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN;        early_suspend.suspend = tas5707_early_suspend;        early_suspend.resume = tas5707_late_resume;        early_suspend.param = codec;        register_early_suspend(&early_suspend);#endif	tas5707->pdata = pdata;	//codec->control_data = tas5707->control_data;	codec->control_type = tas5707->control_type;    ret = snd_soc_codec_set_cache_io(codec, 8, 8, tas5707->control_type);    if (ret != 0) {        dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);        return ret;    }	//TODO: set the DAP	tas5707_init(codec);	return 0;}

static int ak4104_probe(struct snd_soc_codec *codec){	struct ak4104_private *ak4104 = snd_soc_codec_get_drvdata(codec);	int ret;	codec->control_data = ak4104->regmap;	ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);	if (ret != 0)		return ret;	/*                                 */	ret = snd_soc_update_bits(codec, AK4104_REG_CONTROL1,				  AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN,				  AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN);	if (ret < 0)		return ret;	/*                    */	ret = snd_soc_update_bits(codec, AK4104_REG_TX,				  AK4104_TX_TXE, AK4104_TX_TXE);	if (ret < 0)		return ret;	return 0;}

static int max9768_probe(struct snd_soc_codec *codec){	struct max9768 *max9768 = snd_soc_codec_get_drvdata(codec);	int ret;	codec->control_data = max9768->regmap;	ret = snd_soc_codec_set_cache_io(codec, 2, 6, SND_SOC_REGMAP);	if (ret)		return ret;	if (max9768->flags & MAX9768_FLAG_CLASSIC_PWM) {		ret = snd_soc_write(codec, MAX9768_CTRL, MAX9768_CTRL_PWM);		if (ret)			return ret;	}	if (gpio_is_valid(max9768->mute_gpio)) {		ret = snd_soc_add_codec_controls(codec, max9768_mute,				ARRAY_SIZE(max9768_mute));		if (ret)			return ret;	}	return 0;}

static int wm8750_probe(struct snd_soc_codec *codec){	int ret;	ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);	if (ret < 0) {		printk(KERN_ERR "wm8750: failed to set cache I/O: %d/n", ret);		return ret;	}	ret = wm8750_reset(codec);	if (ret < 0) {		printk(KERN_ERR "wm8750: failed to reset: %d/n", ret);		return ret;	}	/* charge output caps */	wm8750_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	/* set the update bits */	snd_soc_update_bits(codec, WM8750_LDAC, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8750_RDAC, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8750_LOUT1V, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8750_ROUT1V, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8750_LOUT2V, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8750_ROUT2V, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8750_LINVOL, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8750_RINVOL, 0x0100, 0x0100);	return ret;}

static int ad193x_probe(struct snd_soc_codec *codec){	struct ad193x_priv *ad193x = snd_soc_codec_get_drvdata(codec);	int ret;	codec->control_data = ad193x->regmap;	ret = snd_soc_codec_set_cache_io(codec, 0, 0, SND_SOC_REGMAP);	if (ret < 0) {		dev_err(codec->dev, "failed to set cache I/O: %d/n", ret);		return ret;	}	/* default setting for ad193x */	/* unmute dac channels */	regmap_write(ad193x->regmap, AD193X_DAC_CHNL_MUTE, 0x0);	/* de-emphasis: 48kHz, powedown dac */	regmap_write(ad193x->regmap, AD193X_DAC_CTRL2, 0x1A);	/* powerdown dac, dac in tdm mode */	regmap_write(ad193x->regmap, AD193X_DAC_CTRL0, 0x41);	/* high-pass filter enable */	regmap_write(ad193x->regmap, AD193X_ADC_CTRL0, 0x3);	/* sata delay=1, adc aux mode */	regmap_write(ad193x->regmap, AD193X_ADC_CTRL1, 0x43);	/* pll input: mclki/xi */	regmap_write(ad193x->regmap, AD193X_PLL_CLK_CTRL0, 0x99); /* mclk=24.576Mhz: 0x9D; mclk=12.288Mhz: 0x99 */	regmap_write(ad193x->regmap, AD193X_PLL_CLK_CTRL1, 0x04);	return ret;}

static int wm8988_probe(struct snd_soc_codec *codec){	struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);	int ret = 0;	codec->control_data = wm8988->regmap;	ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);	if (ret < 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	ret = wm8988_reset(codec);	if (ret < 0) {		dev_err(codec->dev, "Failed to issue reset/n");		return ret;	}	/* set the update bits (we always update left then right) */	snd_soc_update_bits(codec, WM8988_RADC, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8988_RDAC, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8988_ROUT1V, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8988_ROUT2V, 0x0100, 0x0100);	snd_soc_update_bits(codec, WM8988_RINVOL, 0x0100, 0x0100);	wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	return 0;}

static int alc5632_probe(struct snd_soc_codec *codec){	struct alc5632_priv *alc5632 = snd_soc_codec_get_drvdata(codec);	int ret;	codec->control_data = alc5632->regmap;	ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);	if (ret != 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	/*                  */	alc5632_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	switch (alc5632->id) {	case 0x5c:		snd_soc_add_codec_controls(codec, alc5632_vol_snd_controls,			ARRAY_SIZE(alc5632_vol_snd_controls));		break;	default:		return -EINVAL;	}	return ret;}

static int wm8741_probe(struct snd_soc_codec *codec){	struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec);	u16 *reg_cache = codec->reg_cache;	int ret = 0;	ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8741->control_type);	if (ret != 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	ret = wm8741_reset(codec);	if (ret < 0) {		dev_err(codec->dev, "Failed to issue reset/n");		return ret;	}	/* Change some default settings - latch VU */	reg_cache[WM8741_DACLLSB_ATTENUATION] |= WM8741_UPDATELL;	reg_cache[WM8741_DACLMSB_ATTENUATION] |= WM8741_UPDATELM;	reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERL;	reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERM;	snd_soc_add_controls(codec, wm8741_snd_controls,			     ARRAY_SIZE(wm8741_snd_controls));	wm8741_add_widgets(codec);	dev_dbg(codec->dev, "Successful registration/n");	return ret;}

static int aic32x4_probe(struct snd_soc_codec *codec){	struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);	u32 tmp_reg;	snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);	if (aic32x4->rstn_gpio >= 0) {		ndelay(10);		gpio_set_value(aic32x4->rstn_gpio, 1);	}	snd_soc_write(codec, AIC32X4_RESET, 0x01);	/* Power platform configuration */	if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {		snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |						      AIC32X4_MICBIAS_2075V);	}	if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) {		snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);	}	tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?			AIC32X4_LDOCTLEN : 0;	snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);	tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);	if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) {		tmp_reg |= AIC32X4_LDOIN_18_36;	}	if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) {		tmp_reg |= AIC32X4_LDOIN2HP;	}	snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);	/* Mic PGA routing */	if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)		snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);	else		snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_CM1L_10K);	if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)		snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);	else		snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_CM1R_10K);	aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	/*	 * Workaround: for an unknown reason, the ADC needs to be powered up	 * and down for the first capture to work properly. It seems related to	 * a HW BUG or some kind of behavior not documented in the datasheet.	 */	tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);	snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |				AIC32X4_LADC_EN | AIC32X4_RADC_EN);	snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);	return 0;}

static int cs35l32_probe(struct snd_soc_codec *codec) {	int ret;	struct cs35l32_private *cs35l32 = snd_soc_codec_get_drvdata(codec);	codec->control_data = cs35l32->regmap;		ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);	if (ret < 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	regcache_cache_only(cs35l32->regmap, false);	/* Power down the AMP */	snd_soc_update_bits(codec, CS35L32_PWRCTL1, CS35L32_PDN_AMP, 1);		/* Setup ADSP Format Config */	snd_soc_update_bits(codec, CS35L32_ADSP_CTL, CS35L32_ADSP_SHARE_MASK,			    cs35l32->pdata.sdout_share << 3); 	/* Setup ADSP Data Configuration */	snd_soc_update_bits(codec, CS35L32_ADSP_CTL, CS35L32_ADSP_DATACFG_MASK,			    cs35l32->pdata.sdout_datacfg << 4);	/* Setup VBoost Manager  */	snd_soc_update_bits(codec, CS35L32_AUDIO_LED_MNGR, CS35L32_BOOST_MASK,			    cs35l32->pdata.boost_mng);	/* Clear MCLK Error Bit since we don't have the clock yet */	snd_soc_read(codec, CS35L32_INT_STATUS_1);		return ret;}

static int wm8741_probe(struct snd_soc_codec *codec){	struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec);	int ret = 0;	int i;	for (i = 0; i < ARRAY_SIZE(wm8741->supplies); i++)		wm8741->supplies[i].supply = wm8741_supply_names[i];	ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8741->supplies),				 wm8741->supplies);	if (ret != 0) {		dev_err(codec->dev, "Failed to request supplies: %d/n", ret);		goto err;	}	ret = regulator_bulk_enable(ARRAY_SIZE(wm8741->supplies),				    wm8741->supplies);	if (ret != 0) {		dev_err(codec->dev, "Failed to enable supplies: %d/n", ret);		goto err_get;	}	ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8741->control_type);	if (ret != 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		goto err_enable;	}	ret = wm8741_reset(codec);	if (ret < 0) {		dev_err(codec->dev, "Failed to issue reset/n");		goto err_enable;	}	/* Change some default settings - latch VU */	snd_soc_update_bits(codec, WM8741_DACLLSB_ATTENUATION,			    WM8741_UPDATELL, WM8741_UPDATELL);	snd_soc_update_bits(codec, WM8741_DACLMSB_ATTENUATION,			    WM8741_UPDATELM, WM8741_UPDATELM);	snd_soc_update_bits(codec, WM8741_DACRLSB_ATTENUATION,			    WM8741_UPDATERL, WM8741_UPDATERL);	snd_soc_update_bits(codec, WM8741_DACRMSB_ATTENUATION,			    WM8741_UPDATERM, WM8741_UPDATERM);	snd_soc_add_controls(codec, wm8741_snd_controls,			     ARRAY_SIZE(wm8741_snd_controls));	wm8741_add_widgets(codec);	dev_dbg(codec->dev, "Successful registration/n");	return ret;err_enable:	regulator_bulk_disable(ARRAY_SIZE(wm8741->supplies), wm8741->supplies);err_get:	regulator_bulk_free(ARRAY_SIZE(wm8741->supplies), wm8741->supplies);err:	return ret;}

static int wm8731_probe(struct snd_soc_codec *codec){	struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);	int ret = 0, i;	codec->control_data = wm8731->regmap;	ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);	if (ret < 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	for (i = 0; i < ARRAY_SIZE(wm8731->supplies); i++)		wm8731->supplies[i].supply = wm8731_supply_names[i];	ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8731->supplies),				 wm8731->supplies);	if (ret != 0) {		dev_err(codec->dev, "Failed to request supplies: %d/n", ret);		return ret;	}	ret = regulator_bulk_enable(ARRAY_SIZE(wm8731->supplies),				    wm8731->supplies);	if (ret != 0) {		dev_err(codec->dev, "Failed to enable supplies: %d/n", ret);		goto err_regulator_get;	}	ret = wm8731_reset(codec);	if (ret < 0) {		dev_err(codec->dev, "Failed to issue reset: %d/n", ret);		goto err_regulator_enable;	}	wm8731_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	/* Latch the update bits */	snd_soc_update_bits(codec, WM8731_LOUT1V, 0x100, 0);	snd_soc_update_bits(codec, WM8731_ROUT1V, 0x100, 0);	snd_soc_update_bits(codec, WM8731_LINVOL, 0x100, 0);	snd_soc_update_bits(codec, WM8731_RINVOL, 0x100, 0);	/* Disable bypass path by default */	snd_soc_update_bits(codec, WM8731_APANA, 0x8, 0);	/* Regulators will have been enabled by bias management */	regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);	return 0;err_regulator_enable:	regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);err_regulator_get:	regulator_bulk_free(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);	return ret;}

static int ak4671_register(struct ak4671_priv *ak4671,		enum snd_soc_control_type control){	int ret;	struct snd_soc_codec *codec = &ak4671->codec;	if (ak4671_codec) {		dev_err(codec->dev, "Another AK4671 is registered/n");		ret = -EINVAL;		goto err;	}	mutex_init(&codec->mutex);	INIT_LIST_HEAD(&codec->dapm_widgets);	INIT_LIST_HEAD(&codec->dapm_paths);	codec->private_data = ak4671;	codec->name = "AK4671";	codec->owner = THIS_MODULE;	codec->bias_level = SND_SOC_BIAS_OFF;	codec->set_bias_level = ak4671_set_bias_level;	codec->dai = &ak4671_dai;	codec->num_dai = 1;	codec->reg_cache_size = AK4671_CACHEREGNUM;	codec->reg_cache = &ak4671->reg_cache;	memcpy(codec->reg_cache, ak4671_reg, sizeof(ak4671_reg));	ret = snd_soc_codec_set_cache_io(codec, 8, 8, control);	if (ret < 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		goto err;	}	ak4671_dai.dev = codec->dev;	ak4671_codec = codec;	ret = snd_soc_register_codec(codec);	if (ret != 0) {		dev_err(codec->dev, "Failed to register codec: %d/n", ret);		goto err;	}	ret = snd_soc_register_dai(&ak4671_dai);	if (ret != 0) {		dev_err(codec->dev, "Failed to register DAI: %d/n", ret);		goto err_codec;	}	return 0;err_codec:	snd_soc_unregister_codec(codec);err:	kfree(ak4671);	return ret;}

static int wm8737_probe(struct snd_soc_codec *codec){	struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);	int ret, i;	ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8737->control_type);	if (ret != 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	for (i = 0; i < ARRAY_SIZE(wm8737->supplies); i++)		wm8737->supplies[i].supply = wm8737_supply_names[i];	ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8737->supplies),				 wm8737->supplies);	if (ret != 0) {		dev_err(codec->dev, "Failed to request supplies: %d/n", ret);		return ret;	}	ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),				    wm8737->supplies);	if (ret != 0) {		dev_err(codec->dev, "Failed to enable supplies: %d/n", ret);		goto err_get;	}	ret = wm8737_reset(codec);	if (ret < 0) {		dev_err(codec->dev, "Failed to issue reset/n");		goto err_enable;	}	snd_soc_update_bits(codec, WM8737_LEFT_PGA_VOLUME, WM8737_LVU,			    WM8737_LVU);	snd_soc_update_bits(codec, WM8737_RIGHT_PGA_VOLUME, WM8737_RVU,			    WM8737_RVU);	wm8737_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	/* Bias level configuration will have done an extra enable */	regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);	snd_soc_add_controls(codec, wm8737_snd_controls,			     ARRAY_SIZE(wm8737_snd_controls));	wm8737_add_widgets(codec);	return 0;err_enable:	regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);err_get:	regulator_bulk_free(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);	return ret;}

static int cs42l52_probe(struct snd_soc_codec *codec){	struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);	int ret;	codec->control_data = cs42l52->regmap;	ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);	if (ret < 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	regcache_cache_only(cs42l52->regmap, true);	cs42l52_init_beep(codec);	cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	cs42l52->sysclk = CS42L52_DEFAULT_CLK;	cs42l52->config.format = CS42L52_DEFAULT_FORMAT;	/* Set Platform MICx CFG */	snd_soc_update_bits(codec, CS42L52_MICA_CTL,			    CS42L52_MIC_CTL_TYPE_MASK,				cs42l52->pdata.mica_cfg <<				CS42L52_MIC_CTL_TYPE_SHIFT);	snd_soc_update_bits(codec, CS42L52_MICB_CTL,			    CS42L52_MIC_CTL_TYPE_MASK,				cs42l52->pdata.micb_cfg <<				CS42L52_MIC_CTL_TYPE_SHIFT);	/* if Single Ended, Get Mic_Select */	if (cs42l52->pdata.mica_cfg)		snd_soc_update_bits(codec, CS42L52_MICA_CTL,				    CS42L52_MIC_CTL_MIC_SEL_MASK,				cs42l52->pdata.mica_sel <<				CS42L52_MIC_CTL_MIC_SEL_SHIFT);	if (cs42l52->pdata.micb_cfg)		snd_soc_update_bits(codec, CS42L52_MICB_CTL,				    CS42L52_MIC_CTL_MIC_SEL_MASK,				cs42l52->pdata.micb_sel <<				CS42L52_MIC_CTL_MIC_SEL_SHIFT);	/* Set Platform Charge Pump Freq */	snd_soc_update_bits(codec, CS42L52_CHARGE_PUMP,			    CS42L52_CHARGE_PUMP_MASK,				cs42l52->pdata.chgfreq <<				CS42L52_CHARGE_PUMP_SHIFT);	/* Set Platform Bias Level */	snd_soc_update_bits(codec, CS42L52_IFACE_CTL2,			    CS42L52_IFACE_CTL2_BIAS_LVL,				cs42l52->pdata.micbias_lvl);	return ret;}

static int wm9090_probe(struct snd_soc_codec *codec){	int ret;	ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);	if (ret != 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	ret = snd_soc_read(codec, WM9090_SOFTWARE_RESET);	if (ret < 0)		return ret;	if (ret != wm9090_reg_defaults[WM9090_SOFTWARE_RESET]) {		dev_err(codec->dev, "Device is not a WM9090, ID=%x/n", ret);		return -EINVAL;	}	ret = snd_soc_write(codec, WM9090_SOFTWARE_RESET, 0);	if (ret < 0)		return ret;	/* Configure some defaults; they will be written out when we	 * bring the bias up.	 */	snd_soc_update_bits(codec, WM9090_IN1_LINE_INPUT_A_VOLUME,			    WM9090_IN1_VU | WM9090_IN1A_ZC,			    WM9090_IN1_VU | WM9090_IN1A_ZC);	snd_soc_update_bits(codec, WM9090_IN1_LINE_INPUT_B_VOLUME,			    WM9090_IN1_VU | WM9090_IN1B_ZC,			    WM9090_IN1_VU | WM9090_IN1B_ZC);	snd_soc_update_bits(codec, WM9090_IN2_LINE_INPUT_A_VOLUME,			    WM9090_IN2_VU | WM9090_IN2A_ZC,			    WM9090_IN2_VU | WM9090_IN2A_ZC);	snd_soc_update_bits(codec, WM9090_IN2_LINE_INPUT_B_VOLUME,			    WM9090_IN2_VU | WM9090_IN2B_ZC,			    WM9090_IN2_VU | WM9090_IN2B_ZC);	snd_soc_update_bits(codec, WM9090_SPEAKER_VOLUME_LEFT,			    WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC,			    WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC);	snd_soc_update_bits(codec, WM9090_LEFT_OUTPUT_VOLUME,			    WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC,			    WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC);	snd_soc_update_bits(codec, WM9090_RIGHT_OUTPUT_VOLUME,			    WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC,			    WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC);	snd_soc_update_bits(codec, WM9090_CLOCKING_1,			    WM9090_TOCLK_ENA, WM9090_TOCLK_ENA);	wm9090_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	wm9090_add_controls(codec);	return 0;}

static int wm8961_probe(struct snd_soc_codec *codec){    struct snd_soc_dapm_context *dapm = &codec->dapm;    int ret = 0;    u16 reg;    ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);    if (ret != 0) {        dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);        return ret;    }    /* Enable class W */    reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);    reg |= WM8961_CP_DYN_PWR_MASK;    snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);    /* Latch volume update bits (right channel only, we always     * write both out) and default ZC on. */    reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);    snd_soc_write(codec, WM8961_ROUT1_VOLUME,                  reg | WM8961_LO1ZC | WM8961_OUT1VU);    snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);    reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);    snd_soc_write(codec, WM8961_ROUT2_VOLUME,                  reg | WM8961_SPKRZC | WM8961_SPKVU);    snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);    reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);    snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);    reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);    snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);    /* Use soft mute by default */    reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);    reg |= WM8961_DACSMM;    snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);    /* Use automatic clocking mode by default; for now this is all     * we support.     */    reg = snd_soc_read(codec, WM8961_CLOCKING_3);    reg &= ~WM8961_MANUAL_MODE;    snd_soc_write(codec, WM8961_CLOCKING_3, reg);    wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);    snd_soc_add_codec_controls(codec, wm8961_snd_controls,                               ARRAY_SIZE(wm8961_snd_controls));    snd_soc_dapm_new_controls(dapm, wm8961_dapm_widgets,                              ARRAY_SIZE(wm8961_dapm_widgets));    snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));    return 0;}

static int wm2000_probe(struct snd_soc_codec *codec){	struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev);	snd_soc_codec_set_cache_io(codec, 16, 8, SND_SOC_REGMAP);	/* This will trigger a transition to standby mode by default */	wm2000_anc_set_mode(wm2000);	return 0;}

static int rk610_codec_probe(struct snd_soc_codec *codec){	struct rk610_codec_priv *rk610_codec = snd_soc_codec_get_drvdata(codec);	int ret;#ifdef RK610_PROC		RK610_PROC_init();#endif		rk610_codec_codec = codec;	DBG("[%s] start/n", __FUNCTION__);	ret = snd_soc_codec_set_cache_io(codec, 8, 16, rk610_codec->control_type);	if (ret != 0) {		dev_err(codec->dev, "Failed to set cache I/O: %d/n", ret);		return ret;	}	//For RK610, i2c write&read method is special, do not use system default method.	codec->write = rk610_codec_write;	codec->read = rk610_codec_read;	codec->hw_write = (hw_write_t)i2c_master_send;	if (rk610_codec_codec == NULL) {		dev_err(codec->dev, "Codec device not registered/n");		return -ENODEV;	}	INIT_DELAYED_WORK(&rk610_codec->rk610_delayed_work, rk610_delayedwork_fun);#ifdef RK610_SPK_CTRL_PIN	rk610_codec->spk_ctrl_io = RK610_SPK_CTRL_PIN;	ret = gpio_request(rk610_codec->spk_ctrl_io, "rk610 spk_ctrl");    if (ret){        printk("rk610_control request gpio fail!/n");		return ret;    }    gpio_direction_output(rk610_codec->spk_ctrl_io, GPIO_LOW);   	gpio_pull_updown(rk610_codec->spk_ctrl_io, 1);#else	rk610_codec->spk_ctrl_io = 0;#endif	rk610_codec->hdmi_ndet = true;#if RESUME_PROBLEM		rk610_codec->rk610_workstatus = SND_SOC_DAPM_STREAM_NOP;#endif	    rk610_control_init_codec();    rk610_codec_reg_set();//	rk610_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);	schedule_delayed_work(&rk610_codec->rk610_delayed_work, msecs_to_jiffies(1000));	codec->dapm.bias_level = SND_SOC_BIAS_PREPARE;	return ret;}