自学教程：C++ snd_soc_dai_set_sysclk函数代码示例

static int bfin_eval_adau1373_hw_params(struct snd_pcm_substream *substream,                                        struct snd_pcm_hw_params *params){    struct snd_soc_pcm_runtime *rtd = substream->private_data;    struct snd_soc_dai *codec_dai = rtd->codec_dai;    int ret;    int pll_rate;    switch (params_rate(params)) {    case 48000:    case 8000:    case 12000:    case 16000:    case 24000:    case 32000:        pll_rate = 48000 * 1024;        break;    case 44100:    case 7350:    case 11025:    case 14700:    case 22050:    case 29400:        pll_rate = 44100 * 1024;        break;    default:        return -EINVAL;    }    ret = snd_soc_dai_set_pll(codec_dai, ADAU1373_PLL1,                              ADAU1373_PLL_SRC_MCLK1, 12288000, pll_rate);    if (ret)        return ret;    ret = snd_soc_dai_set_sysclk(codec_dai, ADAU1373_CLK_SRC_PLL1, pll_rate,                                 SND_SOC_CLOCK_IN);    return ret;}

static int bf5xx_ad193x_link_init(struct snd_soc_pcm_runtime *rtd){	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	int ret;	/* set the codec system clock for DAC and ADC */	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 24576000, SND_SOC_CLOCK_IN);	if (ret < 0)		return ret;	/* set codec DAI slots, 8 channels, all channels are enabled */	ret = snd_soc_dai_set_tdm_slot(codec_dai, 0xFF, 0xFF, 8, 32);	if (ret < 0)		return ret;	ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0xFF, 0xFF, 8, 32);	if (ret < 0)		return ret;	return 0;}

static int omap2evm_hw_params(struct snd_pcm_substream *substream,	struct snd_pcm_hw_params *params,	struct snd_soc_dai *dai){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;	int ret;	/* Set codec DAI configuration */	ret = snd_soc_dai_set_fmt(codec_dai,				  SND_SOC_DAIFMT_I2S |				  SND_SOC_DAIFMT_NB_NF |				  SND_SOC_DAIFMT_CBM_CFM);	if (ret < 0) {		printk(KERN_ERR "can't set codec DAI configuration/n");		return ret;	}	/* Set cpu DAI configuration */	ret = snd_soc_dai_set_fmt(cpu_dai,				  SND_SOC_DAIFMT_I2S |				  SND_SOC_DAIFMT_NB_NF |				  SND_SOC_DAIFMT_CBM_CFM);	if (ret < 0) {		printk(KERN_ERR "can't set cpu DAI configuration/n");		return ret;	}	/* Set the codec system clock for DAC and ADC */	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,					    SND_SOC_CLOCK_IN);	if (ret < 0) {		printk(KERN_ERR "can't set codec system clock/n");		return ret;	}	return 0;}

static int tegra_wm8753_hw_params(struct snd_pcm_substream *substream,					struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	struct snd_soc_codec *codec = codec_dai->codec;	struct snd_soc_card *card = codec->card;	struct tegra_wm8753 *machine = snd_soc_card_get_drvdata(card);	int srate, mclk;	int err;	srate = params_rate(params);	switch (srate) {	case 11025:	case 22050:	case 44100:	case 88200:		mclk = 11289600;		break;	default:		mclk = 12288000;		break;	}	err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);	if (err < 0) {		dev_err(card->dev, "Can't configure clocks/n");		return err;	}	err = snd_soc_dai_set_sysclk(codec_dai, WM8753_MCLK, mclk,					SND_SOC_CLOCK_IN);	if (err < 0) {		dev_err(card->dev, "codec_dai clock not set/n");		return err;	}	return 0;}

static int imx_mc13783_hifi_hw_params(struct snd_pcm_substream *substream,	struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	int ret;	ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x3, 0x3, 4, 16);	if (ret)		return ret;	ret = snd_soc_dai_set_sysclk(codec_dai, MC13783_CLK_CLIA, 26000000, 0);	if (ret)		return ret;	ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 2, 16);	if (ret)		return ret;	return 0;}

/* * Logic for a wm8731 as connected on a at91sam9g20ek board. */static int at91sam9g20ek_wm8731_init(struct snd_soc_codec *codec){	struct snd_soc_dai *codec_dai = &codec->dai[0];	int ret;	printk(KERN_DEBUG			"at91sam9g20ek_wm8731 "			": at91sam9g20ek_wm8731_init() called/n");	ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK,		MCLK_RATE, SND_SOC_CLOCK_IN);	if (ret < 0) {		printk(KERN_ERR "Failed to set WM8731 SYSCLK: %d/n", ret);		return ret;	}	/* Add specific widgets */	snd_soc_dapm_new_controls(codec, at91sam9g20ek_dapm_widgets,				  ARRAY_SIZE(at91sam9g20ek_dapm_widgets));	/* Set up specific audio path interconnects */	snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));	/* not connected */	snd_soc_dapm_nc_pin(codec, "RLINEIN");	snd_soc_dapm_nc_pin(codec, "LLINEIN");#ifdef ENABLE_MIC_INPUT	snd_soc_dapm_enable_pin(codec, "Int Mic");#else	snd_soc_dapm_nc_pin(codec, "Int Mic");#endif	/* always connected */	snd_soc_dapm_enable_pin(codec, "Ext Spk");	snd_soc_dapm_sync(codec);	return 0;}

static int a370db_hw_params(struct snd_pcm_substream *substream,			    struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	unsigned int freq;	switch (params_rate(params)) {	default:	case 44100:		freq = 11289600;		break;	case 48000:		freq = 12288000;		break;	case 96000:		freq = 24576000;		break;	}	return snd_soc_dai_set_sysclk(codec_dai, 0, freq, SND_SOC_CLOCK_IN);}

static int osk_hw_params(struct snd_pcm_substream *substream,			 struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;	int err;	/* Set codec DAI configuration */	err = snd_soc_dai_set_fmt(codec_dai,				  SND_SOC_DAIFMT_DSP_B |				  SND_SOC_DAIFMT_NB_NF |				  SND_SOC_DAIFMT_CBM_CFM);	if (err < 0) {		printk(KERN_ERR "can't set codec DAI configuration/n");		return err;	}	/* Set cpu DAI configuration */	err = snd_soc_dai_set_fmt(cpu_dai,				  SND_SOC_DAIFMT_DSP_B |				  SND_SOC_DAIFMT_NB_NF |				  SND_SOC_DAIFMT_CBM_CFM);	if (err < 0) {		printk(KERN_ERR "can't set cpu DAI configuration/n");		return err;	}	/* Set the codec system clock for DAC and ADC */	err =	    snd_soc_dai_set_sysclk(codec_dai, 0, CODEC_CLOCK, SND_SOC_CLOCK_IN);	if (err < 0) {		printk(KERN_ERR "can't set codec system clock/n");		return err;	}	return err;}

static int sdp4430_dmic_hw_params(struct snd_pcm_substream *substream,	struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;	int ret = 0;	ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_DMIC_SYSCLK_PAD_CLKS,				     19200000, SND_SOC_CLOCK_IN);	if (ret < 0) {		printk(KERN_ERR "can't set DMIC cpu system clock/n");		return ret;	}	ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_DMIC_CLKDIV, 8);	if (ret < 0) {		printk(KERN_ERR "can't set DMIC cpu clock divider/n");		return ret;	}	return 0;}

static int sunxi_sndspdif_hw_params(struct snd_pcm_substream *substream,					struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;	int ret = 0;	unsigned long rate = params_rate(params);	unsigned int fmt = 0;	u32 mclk_div=0, mpll=0, bclk_div=0, mult_fs=0;	get_clock_divder(rate, 32, &mclk_div, &mpll, &bclk_div, &mult_fs);		if (ret < 0)		return ret;#ifdef CONFIG_SND_SUNXI_SOC_SUPPORT_AUDIO_RAW	/*fmt:1:pcm; >1:rawdata*/	fmt = params_raw(params);#else	fmt = spdif_format;#endif	if(fmt > 1){		fmt = 1;	}else{		fmt = 0;	}	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);//0:pcm,1:raw data	if (ret < 0)		return ret;	ret = snd_soc_dai_set_sysclk(cpu_dai, 0 , mpll, 0);	if (ret < 0)		return ret;	ret = snd_soc_dai_set_clkdiv(cpu_dai, SUNXI_DIV_MCLK, mclk_div);	if (ret < 0)		return ret;	return 0;}

static int zoom2_hw_voice_params(struct snd_pcm_substream *substream,				struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;	int ret;	/* Set codec DAI configuration */	ret = snd_soc_dai_set_fmt(codec_dai,				SND_SOC_DAIFMT_DSP_A |				SND_SOC_DAIFMT_IB_NF |				SND_SOC_DAIFMT_CBM_CFM);	if (ret) {;		return ret;	}	/* Set cpu DAI configuration */	ret = snd_soc_dai_set_fmt(cpu_dai,				SND_SOC_DAIFMT_DSP_A |				SND_SOC_DAIFMT_IB_NF |				SND_SOC_DAIFMT_CBM_CFM);	if (ret < 0) {;		return ret;	}	/* Set the codec system clock for DAC and ADC */	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,					SND_SOC_CLOCK_IN);	if (ret < 0) {;		return ret;	}	return 0;}

static int hub_pcm_hw_params(struct snd_pcm_substream *substream,	struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;	int ret;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	int divisor;	omap3_mux_config("OMAP_MCBSP3_MASTER");	/* Set cpu DAI configuration */	ret = snd_soc_dai_set_fmt(cpu_dai,				  SND_SOC_DAIFMT_DSP_A |				  SND_SOC_DAIFMT_IB_IF |				  SND_SOC_DAIFMT_CBS_CFS);	if (ret < 0) {		printk(KERN_ERR "can't set cpu DAI configuration/n");		return ret;	}	/* Use external (CLK256FS) clock for mcBSP3 */	ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_FCLK, //iggikim 20091012 bs300 mic			0, SND_SOC_CLOCK_OUT);	if (ret < 0) {		printk(KERN_ERR "can't set mcBSP3 to external clock/n");		return ret;	}	ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_MCBSP_CLKGDV, 75); //iggikim 20091012 bs300 mic	if (ret < 0) {		printk(KERN_ERR "can't set codec clock divisor/n");		return ret;	}	return 0;}

static int speyside_set_bias_level_post(struct snd_soc_card *card,					struct snd_soc_dapm_context *dapm,					enum snd_soc_bias_level level){	struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;	int ret;	if (dapm->dev != codec_dai->dev)		return 0;	switch (level) {	case SND_SOC_BIAS_PREPARE:		if (card->dapm.bias_level == SND_SOC_BIAS_STANDBY) {			ret = snd_soc_dai_set_pll(codec_dai, 0,						  WM8996_FLL_MCLK2,						  32768, 48000 * 256);			if (ret < 0) {				pr_err("Failed to start FLL/n");				return ret;			}			ret = snd_soc_dai_set_sysclk(codec_dai,						     WM8996_SYSCLK_FLL,						     48000 * 256,						     SND_SOC_CLOCK_IN);			if (ret < 0)				return ret;		}		break;	default:		break;	}	card->dapm.bias_level = level;	return 0;}

static int cz_aif1_hw_params(struct snd_pcm_substream *substream,			     struct snd_pcm_hw_params *params){	int ret = 0;	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	ret = snd_soc_dai_set_pll(codec_dai, 0, RT5645_PLL1_S_MCLK,				  CZ_PLAT_CLK, params_rate(params) * 512);	if (ret < 0) {		dev_err(rtd->dev, "can't set codec pll: %d/n", ret);		return ret;	}	ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_PLL1,				params_rate(params) * 512, SND_SOC_CLOCK_OUT);	if (ret < 0) {		dev_err(rtd->dev, "can't set codec sysclk: %d/n", ret);		return ret;	}	return ret;}

static int t5325_hw_params(struct snd_pcm_substream *substream,		struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;	int ret;	unsigned int freq, fmt;	fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS;	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);	if (ret < 0)		return ret;	ret = snd_soc_dai_set_fmt(codec_dai, fmt);	if (ret < 0)		return ret;	freq = params_rate(params) * 256;	return snd_soc_dai_set_sysclk(codec_dai, 0, freq, SND_SOC_CLOCK_IN);}

static int byt_rt5640_hw_params(struct snd_pcm_substream *substream,				struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	int ret;	ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_PLL1,				     params_rate(params) * 256,				     SND_SOC_CLOCK_IN);	if (ret < 0) {		dev_err(codec_dai->dev, "can't set codec clock %d/n", ret);		return ret;	}	ret = snd_soc_dai_set_pll(codec_dai, 0, RT5640_PLL1_S_BCLK1,				  params_rate(params) * 64,				  params_rate(params) * 256);	if (ret < 0) {		dev_err(codec_dai->dev, "can't set codec pll: %d/n", ret);		return ret;	}	return 0;}

static void omap4_wm8994_start_fll1(struct snd_soc_dai *aif1_dai){	int ret;	dev_info(aif1_dai->dev, "Moving to audio clocking settings/n");	/* Switch the FLL */	ret = snd_soc_dai_set_pll(aif1_dai,				  WM8994_FLL1,				  WM8994_FLL_SRC_MCLK1,				  26000000, 44100 * 256);	if (ret < 0)		dev_err(aif1_dai->dev, "Unable to start FLL1: %d/n", ret);	/* Then switch AIF1CLK to it */	ret = snd_soc_dai_set_sysclk(aif1_dai,				     WM8994_SYSCLK_FLL1,				     44100 * 256,				     SND_SOC_CLOCK_IN);	if (ret < 0)		dev_err(aif1_dai->dev, "Unable to switch to FLL1: %d/n", ret);}

static int bfin_eval_adau1701_hw_params(struct snd_pcm_substream *substream,	struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	int ret;	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |			SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);	if (ret)		return ret;	ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |			SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);	if (ret)		return ret;	ret = snd_soc_dai_set_sysclk(codec_dai, ADAU1701_CLK_SRC_OSC, 12288000,			SND_SOC_CLOCK_IN);	return ret;}

static int aml_asoc_hw_params(struct snd_pcm_substream *substream,    struct snd_pcm_hw_params *params){    struct snd_soc_pcm_runtime *rtd = substream->private_data;    struct snd_soc_dai *codec_dai = rtd->codec_dai;    struct snd_soc_dai *cpu_dai = rtd->cpu_dai;    int ret;    printk(KERN_DEBUG "enter %s stream: %s rate: %d format: %d/n", __func__, (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? "playback" : "capture", params_rate(params), params_format(params));    /* set codec DAI configuration */    ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |        SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);    if (ret < 0) {        printk(KERN_ERR "%s: set codec dai fmt failed!/n", __func__);        return ret;    }    /* set cpu DAI configuration */    ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |        SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);    if (ret < 0) {        printk(KERN_ERR "%s: set cpu dai fmt failed!/n", __func__);        return ret;    }    /*set codec DAI sysclk divider,now 512fs for MCLK,sysclk divide 2  */    snd_soc_dai_set_clkdiv(codec_dai,WM8960_SYSCLKDIV,WM8960_SYSCLK_DIV_2);        /* set cpu DAI clock */    ret = snd_soc_dai_set_sysclk(cpu_dai, 0, params_rate(params) * 512, SND_SOC_CLOCK_OUT);    if (ret < 0) {        printk(KERN_ERR "%s: set cpu dai sysclk failed (rate: %d)!/n", __func__, params_rate(params));        return ret;    }    return 0;}

static int bf5xx_ssm2602_hw_params(struct snd_pcm_substream *substream,	struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	unsigned int clk = 0;	int ret = 0;	pr_debug("%s rate %d format %x/n", __func__, params_rate(params),		params_format(params));	/*	 * If you are using a crystal source which frequency is not 12MHz	 * then modify the below case statement with frequency of the crystal.	 *	 * If you are using the SPORT to generate clocking then this is	 * where to do it.	 */	switch (params_rate(params)) {	case 8000:	case 16000:	case 48000:	case 96000:	case 11025:	case 22050:	case 44100:		clk = 12000000;		break;	}	ret = snd_soc_dai_set_sysclk(codec_dai, SSM2602_SYSCLK, clk,		SND_SOC_CLOCK_IN);	if (ret < 0)		return ret;	return 0;}

static int fsl_asoc_card_late_probe(struct snd_soc_card *card){	struct fsl_asoc_card_priv *priv = snd_soc_card_get_drvdata(card);	struct snd_soc_pcm_runtime *rtd = list_first_entry(			&card->rtd_list, struct snd_soc_pcm_runtime, list);	struct snd_soc_dai *codec_dai = rtd->codec_dai;	struct codec_priv *codec_priv = &priv->codec_priv;	struct device *dev = card->dev;	int ret;	if (fsl_asoc_card_is_ac97(priv)) {#if IS_ENABLED(CONFIG_SND_AC97_CODEC)		struct snd_soc_codec *codec = rtd->codec;		struct snd_ac97 *ac97 = snd_soc_codec_get_drvdata(codec);		/*		 * Use slots 3/4 for S/PDIF so SSI won't try to enable		 * other slots and send some samples there		 * due to SLOTREQ bits for S/PDIF received from codec		 */		snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS,				     AC97_EA_SPSA_SLOT_MASK, AC97_EA_SPSA_3_4);#endif		return 0;	}	ret = snd_soc_dai_set_sysclk(codec_dai, codec_priv->mclk_id,				     codec_priv->mclk_freq, SND_SOC_CLOCK_IN);	if (ret) {		dev_err(dev, "failed to set sysclk in %s/n", __func__);		return ret;	}	return 0;}

static int __asoc_simple_card_dai_init(struct snd_soc_dai *dai,                                       struct asoc_simple_dai *set){    int ret;    if (set->fmt) {        ret = snd_soc_dai_set_fmt(dai, set->fmt);        if (ret && ret != -ENOTSUPP) {            dev_err(dai->dev, "simple-card: set_fmt error/n");            goto err;        }    }    if (set->sysclk) {        ret = snd_soc_dai_set_sysclk(dai, 0, set->sysclk, 0);        if (ret && ret != -ENOTSUPP) {            dev_err(dai->dev, "simple-card: set_sysclk error/n");            goto err;        }    }    if (set->slots) {        ret = snd_soc_dai_set_tdm_slot(dai, 0, 0,                                       set->slots,                                       set->slot_width);        if (ret && ret != -ENOTSUPP) {            dev_err(dai->dev, "simple-card: set_tdm_slot error/n");            goto err;        }    }    ret = 0;err:    return ret;}

static int rk29_rk1000_codec_init(struct snd_soc_codec *codec) {//	struct snd_soc_dai *codec_dai = &codec->dai[0];	int ret;		DBG("Enter::%s----%d/n",__FUNCTION__,__LINE__);		ret = snd_soc_dai_set_sysclk(codec_dai, 0,	                                11289600, SND_SOC_CLOCK_IN);	if (ret < 0) {	        printk(KERN_ERR "Failed to set WM8988 SYSCLK: %d/n", ret);	        return ret;	}		/* Add specific widgets */	snd_soc_dapm_new_controls(codec, rk29_dapm_widgets,			  ARRAY_SIZE(rk29_dapm_widgets));		/* Set up specific audio path audio_mapnects */	snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));		snd_soc_dapm_sync(codec);		return 0;}

static int tobermory_set_bias_level(struct snd_soc_card *card,					  struct snd_soc_dapm_context *dapm,					  enum snd_soc_bias_level level){	struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;	int ret;	if (dapm->dev != codec_dai->dev)		return 0;	switch (level) {	case SND_SOC_BIAS_PREPARE:		if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {			ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL,						  WM8962_FLL_MCLK, 32768,						  sample_rate * 512);			if (ret < 0)				pr_err("Failed to start FLL: %d/n", ret);			ret = snd_soc_dai_set_sysclk(codec_dai,						     WM8962_SYSCLK_FLL,						     sample_rate * 512,						     SND_SOC_CLOCK_IN);			if (ret < 0) {				pr_err("Failed to set SYSCLK: %d/n", ret);				return ret;			}		}		break;	default:		break;	}	return 0;}

static int cht_aif1_hw_params(struct snd_pcm_substream *substream,			     struct snd_pcm_hw_params *params){	struct snd_soc_pcm_runtime *rtd = substream->private_data;	struct snd_soc_dai *codec_dai = rtd->codec_dai;	int ret;	/* set codec PLL source to the 19.2MHz platform clock (MCLK) */	ret = snd_soc_dai_set_pll(codec_dai, 0, RT5645_PLL1_S_MCLK,				  CHT_PLAT_CLK_3_HZ, params_rate(params) * 512);	if (ret < 0) {		dev_err(rtd->dev, "can't set codec pll: %d/n", ret);		return ret;	}	ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_PLL1,				params_rate(params) * 512, SND_SOC_CLOCK_IN);	if (ret < 0) {		dev_err(rtd->dev, "can't set codec sysclk: %d/n", ret);		return ret;	}	return 0;}