自学教程：C++ wbflush函数代码示例

bt459_video_off(	struct vstate	*vstate,	user_info_t	*up){	register bt459_padded_regmap_t	*regs = vstate->regs;	unsigned char		*save;	if (vstate->off)		return;	/* Yes, this is awful */	save = (unsigned char *)up->dev_dep_2.gx.colormap;	bt459_select_reg(regs, 0);	*save++ = regs->addr_cmap;	*save++ = regs->addr_cmap;	*save++ = regs->addr_cmap;	bt459_select_reg(regs, 0);	regs->addr_cmap = 0;	wbflush();	regs->addr_cmap = 0;	wbflush();	regs->addr_cmap = 0;	wbflush();	bt459_write_reg( regs, BT459_REG_PRM, 0);	bt459_write_reg( regs, BT459_REG_CCR, 0);	vstate->off = 1;}

static void ip32_machine_power_off(void){	volatile unsigned char reg_a, xctrl_a, xctrl_b;	disable_irq(MACEISA_RTC_IRQ);	reg_a = CMOS_READ(RTC_REG_A);	/* setup for kickstart & wake-up (DS12287 Ref. Man. p. 19) */	reg_a &= ~DS_REGA_DV2;	reg_a |= DS_REGA_DV1;	CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A);	wbflush();	xctrl_b = CMOS_READ(DS_B1_XCTRL4B)		   | DS_XCTRL4B_ABE | DS_XCTRL4B_KFE;	CMOS_WRITE(xctrl_b, DS_B1_XCTRL4B);	xctrl_a = CMOS_READ(DS_B1_XCTRL4A) & ~DS_XCTRL4A_IFS;	CMOS_WRITE(xctrl_a, DS_B1_XCTRL4A);	wbflush();	/* adios amigos... */	CMOS_WRITE(xctrl_a | DS_XCTRL4A_PAB, DS_B1_XCTRL4A);	CMOS_WRITE(reg_a, RTC_REG_A);	wbflush();	while(1) {	  	printk(KERN_DEBUG "Power off!/n");	}}

bt459_video_on(	struct vstate	*vstate,	user_info_t	*up){	register bt459_padded_regmap_t	*regs = vstate->regs;	unsigned char		*save;	if (!vstate->off)		return;	/* Like I said.. */	save = (unsigned char *)up->dev_dep_2.gx.colormap;	bt459_select_reg(regs, 0);	regs->addr_cmap = *save++;	wbflush();	regs->addr_cmap = *save++;	wbflush();	regs->addr_cmap = *save++;	wbflush();	bt459_write_reg( regs, BT459_REG_PRM, 0xff);	bt459_write_reg( regs, BT459_REG_CCR, 0xc0);	vstate->off = 0;}

static longrtctime(void){	struct RTCdev *dev;	Rtc rtc;	dev = nvr.rtc;	dev->control |= RTCREAD;	wbflush();	rtc.sec = bcd2dec(dev->sec) & 0x7F;	rtc.min = bcd2dec(dev->min & 0x7F);	rtc.hour = bcd2dec(dev->hour & 0x3F);	rtc.mday = bcd2dec(dev->mday & 0x3F);	rtc.mon = bcd2dec(dev->mon & 0x3F);	rtc.year = bcd2dec(dev->year);	dev->control &= ~RTCREAD;	wbflush();	if (rtc.mon < 1 || rtc.mon > 12)		return 0;	/*	 *  the world starts Jan 1 1970	 */	if(rtc.year < 70)		rtc.year += 2000;	else		rtc.year += 1900;	return rtc2sec(&rtc);}

bt459_init_colormap(	bt459_padded_regmap_t	*regs){	register int    i;	bt459_select_reg(regs, 0);	regs->addr_cmap = 0;	wbflush();	regs->addr_cmap = 0;	wbflush();	regs->addr_cmap = 0;	wbflush();	regs->addr_cmap = 0xff;	wbflush();	regs->addr_cmap = 0xff;	wbflush();	regs->addr_cmap = 0xff;	wbflush();	bt459_select_reg(regs, 255);	regs->addr_cmap = 0xff;	wbflush();	regs->addr_cmap = 0xff;	wbflush();	regs->addr_cmap = 0xff;	wbflush();}

/* * Initalize the memory system and I/O buses. */voiddec_maxine_bus_reset(){    /*     * Reset interrupts, clear any errors from newconf probes     */    *(volatile u_int*)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0;    wbflush();    *(volatile u_int *)IOASIC_REG_INTR(ioasic_base) = 0;    wbflush();}

/* * Color map */bt459_load_colormap_entry(	bt459_padded_regmap_t	*regs,	int			entry,	color_map_t		*map){	bt459_select_reg(regs, entry & 0xff);	regs->addr_cmap = map->red;	wbflush();	regs->addr_cmap = map->green;	wbflush();	regs->addr_cmap = map->blue;	wbflush();}

inline voidau_himem_w_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t val){	*(volatile uint8_t *)(h + o) = val;	wbflush();}

static void debounce(unsigned long data){	volatile unsigned char reg_a,reg_c,xctrl_a;	reg_c = CMOS_READ(RTC_INTR_FLAGS);	CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A);	wbflush();	xctrl_a = CMOS_READ(DS_B1_XCTRL4A);	if( (xctrl_a & DS_XCTRL4A_IFS ) || ( reg_c & RTC_IRQF ) ) {		/* Interrupt still being sent. */		debounce_timer.expires = jiffies + 50;		add_timer(&debounce_timer);		/* clear interrupt source */		CMOS_WRITE( xctrl_a & ~DS_XCTRL4A_IFS, DS_B1_XCTRL4A);		CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A);		return;	}	CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A);	if (has_paniced)		ArcReboot();	enable_irq(MACEISA_RTC_IRQ);}

static voidinitialise_rda(struct sn_softc *sc){	int		i;	char 		*p_rda = 0;	uint32_t	v_rda = 0;	/* link the RDA's together into a circular list */	for (i = 0; i < (sc->sc_nrda - 1); i++) {		p_rda = (char *)sc->p_rda + (i * RXPKT_SIZE(sc));		v_rda = sc->v_rda + ((i+1) * RXPKT_SIZE(sc));		SWO(bitmode, p_rda, RXPKT_RLINK, LOWER(v_rda));		SWO(bitmode, p_rda, RXPKT_INUSE, 1);	}	p_rda = (char *)sc->p_rda + ((sc->sc_nrda - 1) * RXPKT_SIZE(sc));	SWO(bitmode, p_rda, RXPKT_RLINK, LOWER(sc->v_rda) | EOL);	SWO(bitmode, p_rda, RXPKT_INUSE, 1);	/* mark end of receive descriptor list */	sc->sc_rdamark = sc->sc_nrda - 1;	sc->sc_rxmark = 0;	NIC_PUT(sc, SNR_URDA, UPPER(sc->v_rda));	NIC_PUT(sc, SNR_CRDA, LOWER(sc->v_rda));	wbflush();}

/* * close down an interface and free its buffers * Called on final close of device, or if sninit() fails * part way through. */static int snstop(struct sn_softc *sc){	struct mtd *mtd;	int	s = splnet();	/* stick chip in reset */	NIC_PUT(sc, SNR_CR, CR_RST);	wbflush();	/* free all receive buffers (currently static so nothing to do) */	/* free all pending transmit mbufs */	while (sc->mtd_hw != sc->mtd_free) {		mtd = &sc->mtda[sc->mtd_hw];		if (mtd->mtd_mbuf)			m_freem(mtd->mtd_mbuf);		if (++sc->mtd_hw == NTDA) sc->mtd_hw = 0;	}	sc->sc_if.if_timer = 0;	sc->sc_if.if_flags &= ~(IFF_RUNNING | IFF_UP);	splx(s);	return 0;}

static voidinitialise_rra(struct sn_softc *sc){	int	i;	u_int	v;	int	bitmode = sc->bitmode;	if (bitmode)		NIC_PUT(sc, SNR_EOBC, RBASIZE(sc) / 2 - 2);	else		NIC_PUT(sc, SNR_EOBC, RBASIZE(sc) / 2 - 1);	NIC_PUT(sc, SNR_URRA, UPPER(sc->v_rra[0]));	NIC_PUT(sc, SNR_RSA, LOWER(sc->v_rra[0]));	/* rea must point just past the end of the rra space */	NIC_PUT(sc, SNR_REA, LOWER(sc->v_rea));	NIC_PUT(sc, SNR_RRP, LOWER(sc->v_rra[0]));	NIC_PUT(sc, SNR_RSC, 0);	/* fill up SOME of the rra with buffers */	for (i = 0; i < NRBA; i++) {		v = SONIC_GETDMA(sc->rbuf[i]);		SWO(bitmode, sc->p_rra[i], RXRSRC_PTRHI, UPPER(v));		SWO(bitmode, sc->p_rra[i], RXRSRC_PTRLO, LOWER(v));		SWO(bitmode, sc->p_rra[i], RXRSRC_WCHI, UPPER(PAGE_SIZE/2));		SWO(bitmode, sc->p_rra[i], RXRSRC_WCLO, LOWER(PAGE_SIZE/2));	}	sc->sc_rramark = NRBA;	NIC_PUT(sc, SNR_RWP, LOWER(sc->v_rra[sc->sc_rramark]));	wbflush();}

bt459_cursor_color(	bt459_padded_regmap_t	*regs,	color_map_t		*color){	register int    i;	bt459_select_reg_macro( regs, BT459_REG_CCOLOR_2);	for (i = 0; i < 2; i++) {		regs->addr_reg = color->red;		wbflush();		regs->addr_reg = color->green;		wbflush();		regs->addr_reg = color->blue;		wbflush();		color++;	}}

inline void__BS(barrier)(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int f){	/* XXX XXX XXX */	if ((f & BUS_SPACE_BARRIER_WRITE) != 0)		wbflush();}

inline voidau_himem_barrier(void *cookie, bus_space_handle_t bsh, bus_size_t o,    bus_size_t l, int f){	if (f & BUS_SPACE_BARRIER_WRITE)		wbflush();}

inline voidau_himem_w_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t val){	au_himem_cookie_t	*c = (au_himem_cookie_t *)v;	*(volatile uint16_t *)(h + o) = c->c_swswap ? bswap16(val) : val;	wbflush();}

void rbtx4939_machine_restart(char *command){	local_irq_disable();	reg_wr08(rbtx4939_sreset_enable_ptr, 1);	reg_wr08(rbtx4939_soft_reset_ptr, 1);	wbflush();	while (1) ;}

inline voidau_himem_ws_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t val){	au_himem_cookie_t	*c = (au_himem_cookie_t *)v;	*(volatile uint64_t *)(h + o) = c->c_hwswap ? bswap64(val) : val;	wbflush();}

static voidsetrtc(Rtc *rtc){	struct RTCdev *dev;	dev = nvr.rtc;	dev->control |= RTCWRITE;	wbflush();	dev->year = dec2bcd(rtc->year % 100);	dev->mon = dec2bcd(rtc->mon);	dev->mday = dec2bcd(rtc->mday);	dev->hour = dec2bcd(rtc->hour);	dev->min = dec2bcd(rtc->min);	dev->sec = dec2bcd(rtc->sec);	wbflush();	dev->control &= ~RTCWRITE;	wbflush();}

inline uint64_tau_himem_rs_8(void *v, bus_space_handle_t h, bus_size_t o){	uint64_t		val;	au_himem_cookie_t	*c = (au_himem_cookie_t *)v;	wbflush();	val = (*(volatile uint64_t *)(h + o));	return (c->c_hwswap ? bswap64(val) : val);}

void bt459_write_reg(	bt459_padded_regmap_t	*regs,	int			regno,	unsigned char		val){	bt459_select_reg_macro( regs, regno );	regs->addr_reg = val;	wbflush();}

voiddec_3min_os_init(){	ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC);	mips_hardware_intr = dec_3min_intr;	tc_enable_interrupt = dec_3min_enable_intr;	kmin_tc3_imask = (KMIN_INTR_CLOCK | KMIN_INTR_PSWARN |		KMIN_INTR_TIMEOUT);	/*	 * All the baseboard interrupts come through the I/O ASIC	 * (at INT_MASK_3), so  it has to be turned off for all the spls.	 * Since we don't know what kinds of devices are in the	 * turbochannel option slots, just block them all.	 */	Mach_splbio = cpu_spl3;	Mach_splnet = cpu_spl3;	Mach_spltty = cpu_spl3;	Mach_splimp = cpu_spl3;	Mach_splclock = cpu_spl3;	Mach_splstatclock = cpu_spl3;	mcclock_addr = (volatile struct chiptime *)		MIPS_PHYS_TO_KSEG1(KMIN_SYS_CLOCK);	dec_3min_mcclock_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);	/*	 * Initialize interrupts.	 */	*(u_int *)IOASIC_REG_IMSK(ioasic_base) = KMIN_IM0;	*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;	/* clear any memory errors from probes */	*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;	wbflush();	/*	 * The kmin memory hardware seems to wrap  memory addresses	 * with 4Mbyte SIMMs, which causes the physmem computation	 * to lose.  Find out how big the SIMMS are and set	 * max_	physmem accordingly.	 */	physmem_boardmax = KMIN_PHYS_MEMORY_END + 1;	if ((*(int*)(MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) &	     KMIN_MSR_SIZE_16Mb) == 0)		physmem_boardmax = physmem_boardmax >> 2;	physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax);	* (volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK) =	  kmin_tc3_imask |	  (KMIN_IM0 & ~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2));}

static void camdump(struct sn_softc *sc){	int	i;	printf("CAM entries:/n");	NIC_PUT(sc, SNR_CR, CR_RST);	wbflush();	for (i = 0; i < 16; i++) {		ushort  ap2, ap1, ap0;		NIC_PUT(sc, SNR_CEP, i);		wbflush();		ap2 = NIC_GET(sc, SNR_CAP2);		ap1 = NIC_GET(sc, SNR_CAP1);		ap0 = NIC_GET(sc, SNR_CAP0);		printf("%d: ap2=0x%x ap1=0x%x ap0=0x%x/n", i, ap2, ap1, ap0);	}	printf("CAM enable 0x%x/n", NIC_GET(sc, SNR_CEP));	NIC_PUT(sc, SNR_CR, 0);	wbflush();}

inttoshiba_rbtx4938_irq_nested(int sw_irq){	u8 level3;	level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff;	if (level3) {		/* must use fls so onboard ATA has priority */		sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;	}	wbflush();	return sw_irq;}

void __init arch_init_irq(void){	extern void tx4927_irq_init(void);	tx4927_irq_init();	toshiba_rbtx4927_irq_ioc_init();#ifdef CONFIG_TOSHIBA_FPCIB0	if (tx4927_using_backplane)		init_i8259_irqs();#endif	/* Onboard 10M Ether: High Active */	set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);	wbflush();}

void __init arch_init_irq(void){	extern void tx4927_irq_init(void);	tx4927_irq_init();	toshiba_rbtx4927_irq_ioc_init();#ifdef CONFIG_TOSHIBA_FPCIB0	{		if (tx4927_using_backplane) {			toshiba_rbtx4927_irq_isa_init();		}	}#endif	wbflush();}