自学教程：C++ ARMFunctionInfo类代码示例

voidARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,                                       unsigned BaseReg, int64_t Offset) const {  MachineInstr &MI = *I;  MachineBasicBlock &MBB = *MI.getParent();  MachineFunction &MF = *MBB.getParent();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  int Off = Offset; // ARM doesn't need the general 64-bit offsets  unsigned i = 0;  assert(!AFI->isThumb1OnlyFunction() &&         "This resolveFrameIndex does not support Thumb1!");  while (!MI.getOperand(i).isFI()) {    ++i;    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");  }  bool Done = false;  if (!AFI->isThumbFunction())    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);  else {    assert(AFI->isThumb2Function());    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);  }  assert (Done && "Unable to resolve frame index!");}

/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to/// be a pointer to FrameIdx at the beginning of the basic block.void ARMBaseRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,                             unsigned BaseReg, int FrameIdx,                             int64_t Offset) const {  ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :    (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);  MachineBasicBlock::iterator Ins = MBB->begin();  DebugLoc DL;                  // Defaults to "unknown"  if (Ins != MBB->end())    DL = Ins->getDebugLoc();  const MachineFunction &MF = *MBB->getParent();  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();  const MCInstrDesc &MCID = TII.get(ADDriOpc);  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));  MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)    .addFrameIndex(FrameIdx).addImm(Offset);  if (!AFI->isThumb1OnlyFunction())    AddDefaultCC(AddDefaultPred(MIB));}

bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {  ARMFunctionInfo *AFI =      const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();  if (AFI->getArgRegsSaveSize())    return true;  bool IsV4PopReturn = false;  for (const CalleeSavedInfo &CSI : MF.getFrameInfo()->getCalleeSavedInfo())    if (CSI.getReg() == ARM::LR)      IsV4PopReturn = true;  return IsV4PopReturn && STI.hasV4TOps() && !STI.hasV5TOps();}

bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {  ARMFunctionInfo *AFI =      const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();  if (AFI->getArgRegsSaveSize())    return true;  // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.  for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())    if (CSI.getReg() == ARM::LR)      return true;  return false;}

bool Thumb1FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,                            MachineBasicBlock::iterator MI,                            const std::vector<CalleeSavedInfo> &CSI,                            const TargetRegisterInfo *TRI) const {  if (CSI.empty())    return false;  MachineFunction &MF = *MBB.getParent();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  const TargetInstrInfo &TII = *STI.getInstrInfo();  bool isVarArg = AFI->getArgRegsSaveSize() > 0;  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();  MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));  AddDefaultPred(MIB);  bool NeedsPop = false;  for (unsigned i = CSI.size(); i != 0; --i) {    unsigned Reg = CSI[i-1].getReg();    if (Reg == ARM::LR) {      if (MBB.succ_empty()) {        // Special epilogue for vararg functions. See emitEpilogue        if (isVarArg)          continue;        // ARMv4T requires BX, see emitEpilogue        if (!STI.hasV5TOps())          continue;        Reg = ARM::PC;        (*MIB).setDesc(TII.get(ARM::tPOP_RET));        if (MI != MBB.end())          MIB.copyImplicitOps(*MI);        MI = MBB.erase(MI);      } else        // LR may only be popped into PC, as part of return sequence.        // If this isn't the return sequence, we'll need emitPopSpecialFixUp        // to restore LR the hard way.        continue;    }    MIB.addReg(Reg, getDefRegState(true));    NeedsPop = true;  }  // It's illegal to emit pop instruction without operands.  if (NeedsPop)    MBB.insert(MI, &*MIB);  else    MF.DeleteMachineInstr(MIB);  return true;}

bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {  ARMFunctionInfo *AFI =      const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();  if (AFI->getArgRegsSaveSize())    return true;  // FIXME: this doesn't make sense, and the following patch will remove it.  if (!STI.hasV4TOps()) return false;  // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.  for (const CalleeSavedInfo &CSI : MF.getFrameInfo()->getCalleeSavedInfo())    if (CSI.getReg() == ARM::LR)      return true;  return false;}

bool Thumb1FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,                            MachineBasicBlock::iterator MI,                            const std::vector<CalleeSavedInfo> &CSI,                            const TargetRegisterInfo *TRI) const {  if (CSI.empty())    return false;  MachineFunction &MF = *MBB.getParent();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  const TargetInstrInfo &TII = *STI.getInstrInfo();  bool isVarArg = AFI->getArgRegsSaveSize() > 0;  DebugLoc DL = MI->getDebugLoc();  MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));  AddDefaultPred(MIB);  bool NumRegs = false;  for (unsigned i = CSI.size(); i != 0; --i) {    unsigned Reg = CSI[i-1].getReg();    if (Reg == ARM::LR) {      // Special epilogue for vararg functions. See emitEpilogue      if (isVarArg)        continue;      // ARMv4T requires BX, see emitEpilogue      if (STI.hasV4TOps() && !STI.hasV5TOps())        continue;      Reg = ARM::PC;      (*MIB).setDesc(TII.get(ARM::tPOP_RET));      MIB.copyImplicitOps(&*MI);      MI = MBB.erase(MI);    }    MIB.addReg(Reg, getDefRegState(true));    NumRegs = true;  }  // It's illegal to emit pop instruction without operands.  if (NumRegs)    MBB.insert(MI, &*MIB);  else    MF.DeleteMachineInstr(MIB);  return true;}

void ARMBaseRegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,                              MachineBasicBlock::iterator I) const {  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();  if (!TFI->hasReservedCallFrame(MF)) {    // If we have alloca, convert as follows:    // ADJCALLSTACKDOWN -> sub, sp, sp, amount    // ADJCALLSTACKUP   -> add, sp, sp, amount    MachineInstr *Old = I;    DebugLoc dl = Old->getDebugLoc();    unsigned Amount = Old->getOperand(0).getImm();    if (Amount != 0) {      // We need to keep the stack aligned properly.  To do this, we round the      // amount of space needed for the outgoing arguments up to the next      // alignment boundary.      unsigned Align = TFI->getStackAlignment();      Amount = (Amount+Align-1)/Align*Align;      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();      assert(!AFI->isThumb1OnlyFunction() &&             "This eliminateCallFramePseudoInstr does not support Thumb1!");      bool isARM = !AFI->isThumbFunction();      // Replace the pseudo instruction with a new instruction...      unsigned Opc = Old->getOpcode();      int PIdx = Old->findFirstPredOperandIdx();      ARMCC::CondCodes Pred = (PIdx == -1)        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.        unsigned PredReg = Old->getOperand(2).getReg();        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);      } else {        // Note: PredReg is operand 3 for ADJCALLSTACKUP.        unsigned PredReg = Old->getOperand(3).getReg();        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);      }    }  }  MBB.erase(I);}

/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to/// be a pointer to FrameIdx at the beginning of the basic block.void ARMBaseRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,                             unsigned BaseReg, int FrameIdx,                             int64_t Offset) const {  ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);  MachineBasicBlock::iterator Ins = MBB->begin();  DebugLoc DL;                  // Defaults to "unknown"  if (Ins != MBB->end())    DL = Ins->getDebugLoc();  MachineInstrBuilder MIB =    BuildMI(*MBB, Ins, DL, TII.get(ADDriOpc), BaseReg)    .addFrameIndex(FrameIdx).addImm(Offset);  if (!AFI->isThumb1OnlyFunction())    AddDefaultCC(AddDefaultPred(MIB));}

bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,                                        MachineBasicBlock::iterator MI,                                        const std::vector<CalleeSavedInfo> &CSI,                                        const TargetRegisterInfo *TRI) const {  if (CSI.empty())    return false;  MachineFunction &MF = *MBB.getParent();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;  unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;  unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;  unsigned FltOpc = ARM::VLDMDIA_UPD;  emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register);  emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,              &isARMArea2Register);  emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,              &isARMArea1Register);  return true;}

bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,                                        MachineBasicBlock::iterator MI,                                        const std::vector<CalleeSavedInfo> &CSI,                                        const TargetRegisterInfo *TRI) const {  if (CSI.empty())    return false;  MachineFunction &MF = *MBB.getParent();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;  unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE;  unsigned FltOpc = ARM::VSTMDDB_UPD;  emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register,               MachineInstr::FrameSetup);  emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register,               MachineInstr::FrameSetup);  emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,               MachineInstr::FrameSetup);  return true;}

bool Thumb1InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,                            MachineBasicBlock::iterator MI,                            const std::vector<CalleeSavedInfo> &CSI) const {  MachineFunction &MF = *MBB.getParent();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  if (CSI.empty())    return false;  bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;  DebugLoc DL = MI->getDebugLoc();  MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));  AddDefaultPred(MIB);  MIB.addReg(0); // No write back.  bool NumRegs = 0;  for (unsigned i = CSI.size(); i != 0; --i) {    unsigned Reg = CSI[i-1].getReg();    if (Reg == ARM::LR) {      // Special epilogue for vararg functions. See emitEpilogue      if (isVarArg)        continue;      Reg = ARM::PC;      (*MIB).setDesc(get(ARM::tPOP_RET));      MI = MBB.erase(MI);    }    MIB.addReg(Reg, getDefRegState(true));    ++NumRegs;  }  // It's illegal to emit pop instruction without operands.  if (NumRegs)    MBB.insert(MI, &*MIB);  return true;}

voidARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,                                         int SPAdj, RegScavenger *RS) const {  unsigned i = 0;  MachineInstr &MI = *II;  MachineBasicBlock &MBB = *MI.getParent();  MachineFunction &MF = *MBB.getParent();  const ARMFrameLowering *TFI =    static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  assert(!AFI->isThumb1OnlyFunction() &&         "This eliminateFrameIndex does not support Thumb1!");  while (!MI.getOperand(i).isFI()) {    ++i;    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");  }  int FrameIndex = MI.getOperand(i).getIndex();  unsigned FrameReg;  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);  // Special handling of dbg_value instructions.  if (MI.isDebugValue()) {    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);    MI.getOperand(i+1).ChangeToImmediate(Offset);    return;  }  // Modify MI as necessary to handle as much of 'Offset' as possible  bool Done = false;  if (!AFI->isThumbFunction())    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);  else {    assert(AFI->isThumb2Function());    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);  }  if (Done)    return;  // If we get here, the immediate doesn't fit into the instruction.  We folded  // as much as possible above, handle the rest, providing a register that is  // SP+LargeImm.  assert((Offset ||          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&         "This code isn't needed if offset already handled!");  unsigned ScratchReg = 0;  int PIdx = MI.findFirstPredOperandIdx();  ARMCC::CondCodes Pred = (PIdx == -1)    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();  if (Offset == 0)    // Must be addrmode4/6.    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);  else {    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);    if (!AFI->isThumbFunction())      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,                              Offset, Pred, PredReg, TII);    else {      assert(AFI->isThumb2Function());      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,                             Offset, Pred, PredReg, TII);    }    // Update the original instruction to use the scratch register.    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);    if (MI.getOpcode() == ARM::t2ADDrSPi)      MI.setDesc(TII.get(ARM::t2ADDri));    else if (MI.getOpcode() == ARM::t2SUBrSPi)      MI.setDesc(TII.get(ARM::t2SUBri));  }}

void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {  MachineBasicBlock &MBB = MF.front();  MachineBasicBlock::iterator MBBI = MBB.begin();  MachineFrameInfo  *MFI = MF.getFrameInfo();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  const ARMBaseRegisterInfo *RegInfo =    static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());  const ARMBaseInstrInfo &TII =    *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());  assert(!AFI->isThumb1OnlyFunction() &&         "This emitPrologue does not support Thumb1!");  bool isARM = !AFI->isThumbFunction();  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();  unsigned NumBytes = MFI->getStackSize();  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();  unsigned FramePtr = RegInfo->getFrameRegister(MF);  // Determine the sizes of each callee-save spill areas and record which frame  // belongs to which callee-save spill areas.  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;  int FramePtrSpillFI = 0;  // Allocate the vararg register save area. This is not counted in NumBytes.  if (VARegSaveSize)    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,                 MachineInstr::FrameSetup);  if (!AFI->hasStackFrame()) {    if (NumBytes != 0)      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,                   MachineInstr::FrameSetup);    return;  }  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {    unsigned Reg = CSI[i].getReg();    int FI = CSI[i].getFrameIdx();    switch (Reg) {    case ARM::R4:    case ARM::R5:    case ARM::R6:    case ARM::R7:    case ARM::LR:      if (Reg == FramePtr)        FramePtrSpillFI = FI;      AFI->addGPRCalleeSavedArea1Frame(FI);      GPRCS1Size += 4;      break;    case ARM::R8:    case ARM::R9:    case ARM::R10:    case ARM::R11:      if (Reg == FramePtr)        FramePtrSpillFI = FI;      if (STI.isTargetDarwin()) {        AFI->addGPRCalleeSavedArea2Frame(FI);        GPRCS2Size += 4;      } else {        AFI->addGPRCalleeSavedArea1Frame(FI);        GPRCS1Size += 4;      }      break;    default:      AFI->addDPRCalleeSavedAreaFrame(FI);      DPRCSSize += 8;    }  }  // Move past area 1.  if (GPRCS1Size > 0) MBBI++;  // Set FP to point to the stack slot that contains the previous FP.  // For Darwin, FP is R7, which has now been stored in spill area 1.  // Otherwise, if this is not Darwin, all the callee-saved registers go  // into spill area 1, including the FP in R11.  In either case, it is  // now safe to emit this assignment.  bool HasFP = hasFP(MF);  if (HasFP) {    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;    MachineInstrBuilder MIB =      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)      .addFrameIndex(FramePtrSpillFI).addImm(0)      .setMIFlag(MachineInstr::FrameSetup);    AddDefaultCC(AddDefaultPred(MIB));  }  // Move past area 2.  if (GPRCS2Size > 0) MBBI++;  // Determine starting offsets of spill areas.  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;  if (HasFP)    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +                                NumBytes);  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);//.........这里部分代码省略.........

/// needsFrameBaseReg - Returns true if the instruction's frame index/// reference would be better served by a base register other than FP/// or SP. Used by LocalStackFrameAllocation to determine which frame index/// references it should create new base registers for.bool ARMBaseRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");  }  // It's the load/store FI references that cause issues, as it can be difficult  // to materialize the offset if it won't fit in the literal field. Estimate  // based on the size of the local frame and some conservative assumptions  // about the rest of the stack frame (note, this is pre-regalloc, so  // we don't know everything for certain yet) whether this offset is likely  // to be out of range of the immediate. Return true if so.  // We only generate virtual base registers for loads and stores, so  // return false for everything else.  unsigned Opc = MI->getOpcode();  switch (Opc) {  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:  case ARM::t2LDRi12: case ARM::t2LDRi8:  case ARM::t2STRi12: case ARM::t2STRi8:  case ARM::VLDRS: case ARM::VLDRD:  case ARM::VSTRS: case ARM::VSTRD:  case ARM::tSTRspi: case ARM::tLDRspi:    if (ForceAllBaseRegAlloc)      return true;    break;  default:    return false;  }  // Without a virtual base register, if the function has variable sized  // objects, all fixed-size local references will be via the frame pointer,  // Approximate the offset and see if it's legal for the instruction.  // Note that the incoming offset is based on the SP value at function entry,  // so it'll be negative.  MachineFunction &MF = *MI->getParent()->getParent();  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();  MachineFrameInfo *MFI = MF.getFrameInfo();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  // Estimate an offset from the frame pointer.  // Conservatively assume all callee-saved registers get pushed. R4-R6  // will be earlier than the FP, so we ignore those.  // R7, LR  int64_t FPOffset = Offset - 8;  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())    FPOffset -= 80;  // Estimate an offset from the stack pointer.  // The incoming offset is relating to the SP at the start of the function,  // but when we access the local it'll be relative to the SP after local  // allocation, so adjust our SP-relative offset by that allocation size.  Offset = -Offset;  Offset += MFI->getLocalFrameSize();  // Assume that we'll have at least some spill slots allocated.  // FIXME: This is a total SWAG number. We should run some statistics  //        and pick a real one.  Offset += 128; // 128 bytes of spill slots  // If there is a frame pointer, try using it.  // The FP is only available if there is no dynamic realignment. We  // don't know for sure yet whether we'll need that, so we guess based  // on whether there are any local variables that would trigger it.  unsigned StackAlign = TFI->getStackAlignment();  if (TFI->hasFP(MF) &&      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {    if (isFrameOffsetLegal(MI, FPOffset))      return false;  }  // If we can reference via the stack pointer, try that.  // FIXME: This (and the code that resolves the references) can be improved  //        to only disallow SP relative references in the live range of  //        the VLA(s). In practice, it's unclear how much difference that  //        would make, but it may be worth doing.  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))    return false;  // The offset likely isn't legal, we want to allocate a virtual base register.  return true;}

void ARMFrameLowering::emitEpilogue(MachineFunction &MF,                                    MachineBasicBlock &MBB) const {  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();  assert(MBBI->getDesc().isReturn() &&         "Can only insert epilog into returning blocks");  unsigned RetOpcode = MBBI->getOpcode();  DebugLoc dl = MBBI->getDebugLoc();  MachineFrameInfo *MFI = MF.getFrameInfo();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();  const ARMBaseInstrInfo &TII =    *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());  assert(!AFI->isThumb1OnlyFunction() &&         "This emitEpilogue does not support Thumb1!");  bool isARM = !AFI->isThumbFunction();  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();  int NumBytes = (int)MFI->getStackSize();  unsigned FramePtr = RegInfo->getFrameRegister(MF);  if (!AFI->hasStackFrame()) {    if (NumBytes != 0)      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);  } else {    // Unwind MBBI to point to first LDR / VLDRD.    const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();    if (MBBI != MBB.begin()) {      do        --MBBI;      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));      if (!isCSRestore(MBBI, TII, CSRegs))        ++MBBI;    }    // Move SP to start of FP callee save spill area.    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +                 AFI->getGPRCalleeSavedArea2Size() +                 AFI->getDPRCalleeSavedAreaSize());    // Reset SP based on frame pointer only if the stack frame extends beyond    // frame pointer stack slot or target is ELF and the function has FP.    if (AFI->shouldRestoreSPFromFP()) {      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;      if (NumBytes) {        if (isARM)          emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,                                  ARMCC::AL, 0, TII);        else {          // It's not possible to restore SP from FP in a single instruction.          // For Darwin, this looks like:          // mov sp, r7          // sub sp, #24          // This is bad, if an interrupt is taken after the mov, sp is in an          // inconsistent state.          // Use the first callee-saved register as a scratch register.          assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&                 "No scratch register to restore SP from FP!");          emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,                                 ARMCC::AL, 0, TII);          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),                                 ARM::SP)            .addReg(ARM::R4));        }      } else {        // Thumb2 or ARM.        if (isARM)          BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)            .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);        else          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),                                 ARM::SP)            .addReg(FramePtr));      }    } else if (NumBytes)      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);    // Increment past our save areas.    if (AFI->getDPRCalleeSavedAreaSize()) {      MBBI++;      // Since vpop register list cannot have gaps, there may be multiple vpop      // instructions in the epilogue.      while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)        MBBI++;    }    if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;    if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;  }  if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||      RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {    // Tail call return: adjust the stack pointer and jump to callee.    MBBI = MBB.getLastNonDebugInstr();    MachineOperand &JumpTarget = MBBI->getOperand(0);    // Jump to label or value in register.    if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) {      unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi)        ? (STI.isThumb() ? ARM::tTAILJMPd : ARM::TAILJMPd)        : (STI.isThumb() ? ARM::tTAILJMPdND : ARM::TAILJMPdND);      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));//.........这里部分代码省略.........

voidARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,                                         int SPAdj, unsigned FIOperandNum,                                         RegScavenger *RS) const {  MachineInstr &MI = *II;  MachineBasicBlock &MBB = *MI.getParent();  MachineFunction &MF = *MBB.getParent();  const ARMBaseInstrInfo &TII =      *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());  const ARMFrameLowering *TFI = getFrameLowering(MF);  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  assert(!AFI->isThumb1OnlyFunction() &&         "This eliminateFrameIndex does not support Thumb1!");  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();  unsigned FrameReg;  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the  // call frame setup/destroy instructions have already been eliminated.  That  // means the stack pointer cannot be used to access the emergency spill slot  // when !hasReservedCallFrame().#ifndef NDEBUG  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){    assert(TFI->hasReservedCallFrame(MF) &&           "Cannot use SP to access the emergency spill slot in "           "functions without a reserved call frame");    assert(!MF.getFrameInfo()->hasVarSizedObjects() &&           "Cannot use SP to access the emergency spill slot in "           "functions with variable sized frame objects");  }#endif // NDEBUG  assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");  // Modify MI as necessary to handle as much of 'Offset' as possible  bool Done = false;  if (!AFI->isThumbFunction())    Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);  else {    assert(AFI->isThumb2Function());    Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);  }  if (Done)    return;  // If we get here, the immediate doesn't fit into the instruction.  We folded  // as much as possible above, handle the rest, providing a register that is  // SP+LargeImm.  assert((Offset ||          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&         "This code isn't needed if offset already handled!");  unsigned ScratchReg = 0;  int PIdx = MI.findFirstPredOperandIdx();  ARMCC::CondCodes Pred = (PIdx == -1)    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();  if (Offset == 0)    // Must be addrmode4/6.    MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);  else {    ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);    if (!AFI->isThumbFunction())      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,                              Offset, Pred, PredReg, TII);    else {      assert(AFI->isThumb2Function());      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,                             Offset, Pred, PredReg, TII);    }    // Update the original instruction to use the scratch register.    MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);  }}

void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,                                   MachineBasicBlock::iterator MI,                                   const std::vector<CalleeSavedInfo> &CSI,                                   unsigned LdmOpc, unsigned LdrOpc,                                   bool isVarArg, bool NoGap,                                   bool(*Func)(unsigned, bool)) const {  MachineFunction &MF = *MBB.getParent();  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  DebugLoc DL = MI->getDebugLoc();  unsigned RetOpcode = MI->getOpcode();  bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||                     RetOpcode == ARM::TCRETURNdiND ||                     RetOpcode == ARM::TCRETURNri ||                     RetOpcode == ARM::TCRETURNriND);  SmallVector<unsigned, 4> Regs;  unsigned i = CSI.size();  while (i != 0) {    unsigned LastReg = 0;    bool DeleteRet = false;    for (; i != 0; --i) {      unsigned Reg = CSI[i-1].getReg();      if (!(Func)(Reg, STI.isTargetDarwin())) continue;      if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) {        Reg = ARM::PC;        LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;        // Fold the return instruction into the LDM.        DeleteRet = true;      }      // If NoGap is true, pop consecutive registers and then leave the rest      // for other instructions. e.g.      // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}      if (NoGap && LastReg && LastReg != Reg-1)        break;      LastReg = Reg;      Regs.push_back(Reg);    }    if (Regs.empty())      continue;    if (Regs.size() > 1 || LdrOpc == 0) {      MachineInstrBuilder MIB =        AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)                       .addReg(ARM::SP));      for (unsigned i = 0, e = Regs.size(); i < e; ++i)        MIB.addReg(Regs[i], getDefRegState(true));      if (DeleteRet) {        MIB->copyImplicitOps(&*MI);        MI->eraseFromParent();      }      MI = MIB;    } else if (Regs.size() == 1) {      // If we adjusted the reg to PC from LR above, switch it back here. We      // only do that for LDM.      if (Regs[0] == ARM::PC)        Regs[0] = ARM::LR;      MachineInstrBuilder MIB =        BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])          .addReg(ARM::SP, RegState::Define)          .addReg(ARM::SP);      // ARM mode needs an extra reg0 here due to addrmode2. Will go away once      // that refactoring is complete (eventually).      if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {        MIB.addReg(0);        MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));      } else        MIB.addImm(4);      AddDefaultPred(MIB);    }    Regs.clear();  }}

void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,                                       MachineBasicBlock &MBB) const {  MachineBasicBlock::iterator MBBI = MBB.begin();  MachineFrameInfo  *MFI = MF.getFrameInfo();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  MachineModuleInfo &MMI = MF.getMMI();  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();  const ThumbRegisterInfo *RegInfo =      static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());  const Thumb1InstrInfo &TII =      *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();  unsigned NumBytes = MFI->getStackSize();  assert(NumBytes >= ArgRegsSaveSize &&         "ArgRegsSaveSize is included in NumBytes");  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();  // Debug location must be unknown since the first debug location is used  // to determine the end of the prologue.  DebugLoc dl;    unsigned FramePtr = RegInfo->getFrameRegister(MF);  unsigned BasePtr = RegInfo->getBaseRegister();  int CFAOffset = 0;  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.  NumBytes = (NumBytes + 3) & ~3;  MFI->setStackSize(NumBytes);  // Determine the sizes of each callee-save spill areas and record which frame  // belongs to which callee-save spill areas.  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;  int FramePtrSpillFI = 0;  if (ArgRegsSaveSize) {    emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,                 MachineInstr::FrameSetup);    CFAOffset -= ArgRegsSaveSize;    unsigned CFIIndex = MMI.addFrameInst(        MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));    BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))        .addCFIIndex(CFIIndex)        .setMIFlags(MachineInstr::FrameSetup);  }  if (!AFI->hasStackFrame()) {    if (NumBytes - ArgRegsSaveSize != 0) {      emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),                   MachineInstr::FrameSetup);      CFAOffset -= NumBytes - ArgRegsSaveSize;      unsigned CFIIndex = MMI.addFrameInst(          MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))          .addCFIIndex(CFIIndex)          .setMIFlags(MachineInstr::FrameSetup);    }    return;  }  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {    unsigned Reg = CSI[i].getReg();    int FI = CSI[i].getFrameIdx();    switch (Reg) {    case ARM::R8:    case ARM::R9:    case ARM::R10:    case ARM::R11:      if (STI.isTargetMachO()) {        GPRCS2Size += 4;        break;      }      // fallthrough    case ARM::R4:    case ARM::R5:    case ARM::R6:    case ARM::R7:    case ARM::LR:      if (Reg == FramePtr)        FramePtrSpillFI = FI;      GPRCS1Size += 4;      break;    default:      DPRCSSize += 8;    }  }  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {    ++MBBI;  }  // Determine starting offsets of spill areas.  unsigned DPRCSOffset  = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;  bool HasFP = hasFP(MF);  if (HasFP)    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +                                NumBytes);  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);//.........这里部分代码省略.........

bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,                                              bool DoIt) const {  MachineFunction &MF = *MBB.getParent();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();  const TargetInstrInfo &TII = *STI.getInstrInfo();  const ThumbRegisterInfo *RegInfo =      static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());  // If MBBI is a return instruction, we may be able to directly restore  // LR in the PC.  // This is possible if we do not need to emit any SP update.  // Otherwise, we need a temporary register to pop the value  // and copy that value into LR.  auto MBBI = MBB.getFirstTerminator();  if (!ArgRegsSaveSize && MBBI != MBB.end() &&      MBBI->getOpcode() == ARM::tBX_RET) {    if (!DoIt)      return true;    MachineInstrBuilder MIB =        AddDefaultPred(            BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET)))            .addReg(ARM::PC, RegState::Define);    MIB.copyImplicitOps(&*MBBI);    // erase the old tBX_RET instruction    MBB.erase(MBBI);    return true;  }  // Look for a temporary register to use.  // First, compute the liveness information.  LivePhysRegs UsedRegs(STI.getRegisterInfo());  UsedRegs.addLiveOuts(&MBB, /*AddPristines*/ true);  // The semantic of pristines changed recently and now,  // the callee-saved registers that are touched in the function  // are not part of the pristines set anymore.  // Add those callee-saved now.  const TargetRegisterInfo *TRI = STI.getRegisterInfo();  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);  for (unsigned i = 0; CSRegs[i]; ++i)    UsedRegs.addReg(CSRegs[i]);  DebugLoc dl = DebugLoc();  if (MBBI != MBB.end()) {    dl = MBBI->getDebugLoc();    auto InstUpToMBBI = MBB.end();    // The post-decrement is on purpose here.    // We want to have the liveness right before MBBI.    while (InstUpToMBBI-- != MBBI)      UsedRegs.stepBackward(*InstUpToMBBI);  }  // Look for a register that can be directly use in the POP.  unsigned PopReg = 0;  // And some temporary register, just in case.  unsigned TemporaryReg = 0;  BitVector PopFriendly =      TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::tGPRRegClassID));  assert(PopFriendly.any() && "No allocatable pop-friendly register?!");  // Rebuild the GPRs from the high registers because they are removed  // form the GPR reg class for thumb1.  BitVector GPRsNoLRSP =      TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::hGPRRegClassID));  GPRsNoLRSP |= PopFriendly;  GPRsNoLRSP.reset(ARM::LR);  GPRsNoLRSP.reset(ARM::SP);  GPRsNoLRSP.reset(ARM::PC);  for (int Register = GPRsNoLRSP.find_first(); Register != -1;       Register = GPRsNoLRSP.find_next(Register)) {    if (!UsedRegs.contains(Register)) {      // Remember the first pop-friendly register and exit.      if (PopFriendly.test(Register)) {        PopReg = Register;        TemporaryReg = 0;        break;      }      // Otherwise, remember that the register will be available to      // save a pop-friendly register.      TemporaryReg = Register;    }  }  if (!DoIt && !PopReg && !TemporaryReg)    return false;  assert((PopReg || TemporaryReg) && "Cannot get LR");  if (TemporaryReg) {    assert(!PopReg && "Unnecessary MOV is about to be inserted");    PopReg = PopFriendly.find_first();    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))                       .addReg(TemporaryReg, RegState::Define)                       .addReg(PopReg, RegState::Kill));  }  assert(PopReg && "Do not know how to get LR");  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))      .addReg(PopReg, RegState::Define);  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);//.........这里部分代码省略.........

voidARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,                                                       RegScavenger *RS) const {  // This tells PEI to spill the FP as if it is any other callee-save register  // to take advantage the eliminateFrameIndex machinery. This also ensures it  // is spilled in the order specified by getCalleeSavedRegs() to make it easier  // to combine multiple loads / stores.  bool CanEliminateFrame = true;  bool CS1Spilled = false;  bool LRSpilled = false;  unsigned NumGPRSpills = 0;  SmallVector<unsigned, 4> UnspilledCS1GPRs;  SmallVector<unsigned, 4> UnspilledCS2GPRs;  const ARMBaseRegisterInfo *RegInfo =    static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());  const ARMBaseInstrInfo &TII =    *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  MachineFrameInfo *MFI = MF.getFrameInfo();  unsigned FramePtr = RegInfo->getFrameRegister(MF);  // Spill R4 if Thumb2 function requires stack realignment - it will be used as  // scratch register. Also spill R4 if Thumb2 function has varsized objects,  // since it's not always possible to restore sp from fp in a single  // instruction.  // FIXME: It will be better just to find spare register here.  if (AFI->isThumb2Function() &&      (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))    MF.getRegInfo().setPhysRegUsed(ARM::R4);  if (AFI->isThumb1OnlyFunction()) {    // Spill LR if Thumb1 function uses variable length argument lists.    if (AFI->getVarArgsRegSaveSize() > 0)      MF.getRegInfo().setPhysRegUsed(ARM::LR);    // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know    // for sure what the stack size will be, but for this, an estimate is good    // enough. If there anything changes it, it'll be a spill, which implies    // we've used all the registers and so R4 is already used, so not marking    // it here will be OK.  Also spill R4 if Thumb1 function requires stack    // realignment.    // FIXME: It will be better just to find spare register here.    unsigned StackSize = estimateStackSize(MF);    if (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF) ||        StackSize > 508)      MF.getRegInfo().setPhysRegUsed(ARM::R4);  }  // Spill the BasePtr if it's used.  if (RegInfo->hasBasePointer(MF))    MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());  // Don't spill FP if the frame can be eliminated. This is determined  // by scanning the callee-save registers to see if any is used.  const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();  for (unsigned i = 0; CSRegs[i]; ++i) {    unsigned Reg = CSRegs[i];    bool Spilled = false;    if (MF.getRegInfo().isPhysRegUsed(Reg)) {      Spilled = true;      CanEliminateFrame = false;    } else {      // Check alias registers too.      for (const unsigned *Aliases =             RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) {        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {          Spilled = true;          CanEliminateFrame = false;        }      }    }    if (!ARM::GPRRegisterClass->contains(Reg))      continue;    if (Spilled) {      NumGPRSpills++;      if (!STI.isTargetDarwin()) {        if (Reg == ARM::LR)          LRSpilled = true;        CS1Spilled = true;        continue;      }      // Keep track if LR and any of R4, R5, R6, and R7 is spilled.      switch (Reg) {      case ARM::LR:        LRSpilled = true;        // Fallthrough      case ARM::R4: case ARM::R5:      case ARM::R6: case ARM::R7:        CS1Spilled = true;        break;      default:        break;      }    } else {      if (!STI.isTargetDarwin()) {        UnspilledCS1GPRs.push_back(Reg);//.........这里部分代码省略.........

void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,                                   MachineBasicBlock &MBB) const {  MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();  MachineFrameInfo *MFI = MF.getFrameInfo();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  const ThumbRegisterInfo *RegInfo =      static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());  const Thumb1InstrInfo &TII =      *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();  int NumBytes = (int)MFI->getStackSize();  assert((unsigned)NumBytes >= ArgRegsSaveSize &&         "ArgRegsSaveSize is included in NumBytes");  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);  unsigned FramePtr = RegInfo->getFrameRegister(MF);  if (!AFI->hasStackFrame()) {    if (NumBytes - ArgRegsSaveSize != 0)      emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);  } else {    // Unwind MBBI to point to first LDR / VLDRD.    if (MBBI != MBB.begin()) {      do        --MBBI;      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));      if (!isCSRestore(MBBI, CSRegs))        ++MBBI;    }    // Move SP to start of FP callee save spill area.    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +                 AFI->getGPRCalleeSavedArea2Size() +                 AFI->getDPRCalleeSavedAreaSize() +                 ArgRegsSaveSize);    if (AFI->shouldRestoreSPFromFP()) {      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;      // Reset SP based on frame pointer only if the stack frame extends beyond      // frame pointer stack slot, the target is ELF and the function has FP, or      // the target uses var sized objects.      if (NumBytes) {        assert(!MFI->getPristineRegs(MF).test(ARM::R4) &&               "No scratch register to restore SP from FP!");        emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,                                  TII, *RegInfo);        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),                               ARM::SP)          .addReg(ARM::R4));      } else        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),                               ARM::SP)          .addReg(FramePtr));    } else {      if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&          &MBB.front() != MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {        MachineBasicBlock::iterator PMBBI = std::prev(MBBI);        if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))          emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);      } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))        emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);    }  }  if (needPopSpecialFixUp(MF)) {    bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);    (void)Done;    assert(Done && "Emission of the special fixup failed!?");  }}

bool Thumb1FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,                            MachineBasicBlock::iterator MI,                            std::vector<CalleeSavedInfo> &CSI,                            const TargetRegisterInfo *TRI) const {  if (CSI.empty())    return false;  MachineFunction &MF = *MBB.getParent();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  const TargetInstrInfo &TII = *STI.getInstrInfo();  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(      MF.getSubtarget().getRegisterInfo());  bool isVarArg = AFI->getArgRegsSaveSize() > 0;  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();  ARMRegSet LoRegsToRestore;  ARMRegSet HiRegsToRestore;  // Low registers (r0-r7) which can be used to restore the high registers.  ARMRegSet CopyRegs;  for (CalleeSavedInfo I : CSI) {    unsigned Reg = I.getReg();    if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {      LoRegsToRestore[Reg] = true;    } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {      HiRegsToRestore[Reg] = true;    } else {      llvm_unreachable("callee-saved register of unexpected class");    }    // If this is a low register not used as the frame pointer, we may want to    // use it for restoring the high registers.    if ((ARM::tGPRRegClass.contains(Reg)) &&        !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))      CopyRegs[Reg] = true;  }  // If this is a return block, we may be able to use some unused return value  // registers for restoring the high regs.  auto Terminator = MBB.getFirstTerminator();  if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {    CopyRegs[ARM::R0] = true;    CopyRegs[ARM::R1] = true;    CopyRegs[ARM::R2] = true;    CopyRegs[ARM::R3] = true;    for (auto Op : Terminator->implicit_operands()) {      if (Op.isReg())        CopyRegs[Op.getReg()] = false;    }  }  static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,                                         ARM::R4, ARM::R5, ARM::R6, ARM::R7};  static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);  // Find the first register to restore.  auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),                                           HiRegsToRestore, AllHighRegsEnd);  while (HiRegToRestore != AllHighRegsEnd) {    assert(!CopyRegs.none());    // Find the first low register to use.    auto CopyReg =        findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);    // Create the POP instruction.    MachineInstrBuilder PopMIB =        BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));    while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {      // Add the low register to the POP.      PopMIB.addReg(*CopyReg, RegState::Define);      // Create the MOV from low to high register.      BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))          .addReg(*HiRegToRestore, RegState::Define)          .addReg(*CopyReg, RegState::Kill)          .add(predOps(ARMCC::AL));      CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);      HiRegToRestore =          findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);    }  }  MachineInstrBuilder MIB =      BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));  bool NeedsPop = false;  for (unsigned i = CSI.size(); i != 0; --i) {    CalleeSavedInfo &Info = CSI[i-1];    unsigned Reg = Info.getReg();    // High registers (excluding lr) have already been dealt with//.........这里部分代码省略.........

void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,                                   MachineBasicBlock &MBB) const {  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();  assert((MBBI->getOpcode() == ARM::tBX_RET ||          MBBI->getOpcode() == ARM::tPOP_RET) &&         "Can only insert epilog into returning blocks");  DebugLoc dl = MBBI->getDebugLoc();  MachineFrameInfo *MFI = MF.getFrameInfo();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  const ThumbRegisterInfo *RegInfo =      static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());  const Thumb1InstrInfo &TII =      *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();  int NumBytes = (int)MFI->getStackSize();  assert((unsigned)NumBytes >= ArgRegsSaveSize &&         "ArgRegsSaveSize is included in NumBytes");  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);  unsigned FramePtr = RegInfo->getFrameRegister(MF);  if (!AFI->hasStackFrame()) {    if (NumBytes - ArgRegsSaveSize != 0)      emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);  } else {    // Unwind MBBI to point to first LDR / VLDRD.    if (MBBI != MBB.begin()) {      do        --MBBI;      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));      if (!isCSRestore(MBBI, CSRegs))        ++MBBI;    }    // Move SP to start of FP callee save spill area.    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +                 AFI->getGPRCalleeSavedArea2Size() +                 AFI->getDPRCalleeSavedAreaSize() +                 ArgRegsSaveSize);    if (AFI->shouldRestoreSPFromFP()) {      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;      // Reset SP based on frame pointer only if the stack frame extends beyond      // frame pointer stack slot, the target is ELF and the function has FP, or      // the target uses var sized objects.      if (NumBytes) {        assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&               "No scratch register to restore SP from FP!");        emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,                                  TII, *RegInfo);        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),                               ARM::SP)          .addReg(ARM::R4));      } else        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),                               ARM::SP)          .addReg(FramePtr));    } else {      if (MBBI->getOpcode() == ARM::tBX_RET &&          &MBB.front() != MBBI &&          std::prev(MBBI)->getOpcode() == ARM::tPOP) {        MachineBasicBlock::iterator PMBBI = std::prev(MBBI);        if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))          emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);      } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))        emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);    }  }  bool IsV4PopReturn = false;  for (const CalleeSavedInfo &CSI : MFI->getCalleeSavedInfo())    if (CSI.getReg() == ARM::LR)      IsV4PopReturn = true;  IsV4PopReturn &= STI.hasV4TOps() && !STI.hasV5TOps();  // Unlike T2 and ARM mode, the T1 pop instruction cannot restore  // to LR, and we can't pop the value directly to the PC since  // we need to update the SP after popping the value. So instead  // we have to emit:  //   POP {r3}  //   ADD sp, #offset  //   BX r3  // If this would clobber a return value, then generate this sequence instead:  //   MOV ip, r3  //   POP {r3}  //   ADD sp, #offset  //   MOV lr, r3  //   MOV r3, ip  //   BX lr  if (ArgRegsSaveSize || IsV4PopReturn) {    // Get the last instruction, tBX_RET    MBBI = MBB.getLastNonDebugInstr();    assert (MBBI->getOpcode() == ARM::tBX_RET);    DebugLoc dl = MBBI->getDebugLoc();    if (AFI->getReturnRegsCount() <= 3) {      // Epilogue: pop saved LR to R3 and branch off it.       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))        .addReg(ARM::R3, RegState::Define);//.........这里部分代码省略.........

void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,                                       MachineBasicBlock &MBB) const {  MachineBasicBlock::iterator MBBI = MBB.begin();  MachineFrameInfo &MFI = MF.getFrameInfo();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  MachineModuleInfo &MMI = MF.getMMI();  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();  const ThumbRegisterInfo *RegInfo =      static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());  const Thumb1InstrInfo &TII =      *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();  unsigned NumBytes = MFI.getStackSize();  assert(NumBytes >= ArgRegsSaveSize &&         "ArgRegsSaveSize is included in NumBytes");  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();  // Debug location must be unknown since the first debug location is used  // to determine the end of the prologue.  DebugLoc dl;    unsigned FramePtr = RegInfo->getFrameRegister(MF);  unsigned BasePtr = RegInfo->getBaseRegister();  int CFAOffset = 0;  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.  NumBytes = (NumBytes + 3) & ~3;  MFI.setStackSize(NumBytes);  // Determine the sizes of each callee-save spill areas and record which frame  // belongs to which callee-save spill areas.  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;  int FramePtrSpillFI = 0;  if (ArgRegsSaveSize) {    emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,                 MachineInstr::FrameSetup);    CFAOffset -= ArgRegsSaveSize;    unsigned CFIIndex = MF.addFrameInst(        MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));    BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))        .addCFIIndex(CFIIndex)        .setMIFlags(MachineInstr::FrameSetup);  }  if (!AFI->hasStackFrame()) {    if (NumBytes - ArgRegsSaveSize != 0) {      emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),                   MachineInstr::FrameSetup);      CFAOffset -= NumBytes - ArgRegsSaveSize;      unsigned CFIIndex = MF.addFrameInst(          MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))          .addCFIIndex(CFIIndex)          .setMIFlags(MachineInstr::FrameSetup);    }    return;  }  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {    unsigned Reg = CSI[i].getReg();    int FI = CSI[i].getFrameIdx();    switch (Reg) {    case ARM::R8:    case ARM::R9:    case ARM::R10:    case ARM::R11:      if (STI.splitFramePushPop(MF)) {        GPRCS2Size += 4;        break;      }      LLVM_FALLTHROUGH;    case ARM::R4:    case ARM::R5:    case ARM::R6:    case ARM::R7:    case ARM::LR:      if (Reg == FramePtr)        FramePtrSpillFI = FI;      GPRCS1Size += 4;      break;    default:      DPRCSSize += 8;    }  }  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {    ++MBBI;  }  // Determine starting offsets of spill areas.  unsigned DPRCSOffset  = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;  bool HasFP = hasFP(MF);  if (HasFP)    AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +                                NumBytes);  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);//.........这里部分代码省略.........

voidThumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,                                        int SPAdj, unsigned FIOperandNum,                                        RegScavenger *RS) const {  unsigned VReg = 0;  MachineInstr &MI = *II;  MachineBasicBlock &MBB = *MI.getParent();  MachineFunction &MF = *MBB.getParent();  const ARMBaseInstrInfo &TII =      *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  DebugLoc dl = MI.getDebugLoc();  MachineInstrBuilder MIB(*MBB.getParent(), &MI);  unsigned FrameReg = ARM::SP;  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +               MF.getFrameInfo()->getStackSize() + SPAdj;  if (MF.getFrameInfo()->hasVarSizedObjects()) {    assert(SPAdj == 0 && MF.getSubtarget().getFrameLowering()->hasFP(MF) &&           "Unexpected");    // There are alloca()'s in this function, must reference off the frame    // pointer or base pointer instead.    if (!hasBasePointer(MF)) {      FrameReg = getFrameRegister(MF);      Offset -= AFI->getFramePtrSpillOffset();    } else      FrameReg = BasePtr;  }  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the  // call frame setup/destroy instructions have already been eliminated.  That  // means the stack pointer cannot be used to access the emergency spill slot  // when !hasReservedCallFrame().#ifndef NDEBUG  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){    assert(MF.getTarget()               .getSubtargetImpl()               ->getFrameLowering()               ->hasReservedCallFrame(MF) &&           "Cannot use SP to access the emergency spill slot in "           "functions without a reserved call frame");    assert(!MF.getFrameInfo()->hasVarSizedObjects() &&           "Cannot use SP to access the emergency spill slot in "           "functions with variable sized frame objects");  }#endif // NDEBUG  // Special handling of dbg_value instructions.  if (MI.isDebugValue()) {    MI.getOperand(FIOperandNum).  ChangeToRegister(FrameReg, false /*isDef*/);    MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);    return;  }  // Modify MI as necessary to handle as much of 'Offset' as possible  assert(AFI->isThumbFunction() &&         "This eliminateFrameIndex only supports Thumb1!");  if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))    return;  // If we get here, the immediate doesn't fit into the instruction.  We folded  // as much as possible above, handle the rest, providing a register that is  // SP+LargeImm.  assert(Offset && "This code isn't needed if offset already handled!");  unsigned Opcode = MI.getOpcode();  // Remove predicate first.  int PIdx = MI.findFirstPredOperandIdx();  if (PIdx != -1)    removeOperands(MI, PIdx);  if (MI.mayLoad()) {    // Use the destination register to materialize sp + offset.    unsigned TmpReg = MI.getOperand(0).getReg();    bool UseRR = false;    if (Opcode == ARM::tLDRspi) {      if (FrameReg == ARM::SP)        emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,                                 Offset, false, TII, *this);      else {        emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);        UseRR = true;      }    } else {      emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,                                *this);    }    MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));    MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);    if (UseRR)      // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame      // register. The offset is already handled in the vreg value.      MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,                                                     false);  } else if (MI.mayStore()) {      VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);//.........这里部分代码省略.........

bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,                                              bool DoIt) const {  MachineFunction &MF = *MBB.getParent();  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();  const TargetInstrInfo &TII = *STI.getInstrInfo();  const ThumbRegisterInfo *RegInfo =      static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());  // If MBBI is a return instruction, or is a tPOP followed by a return  // instruction in the successor BB, we may be able to directly restore  // LR in the PC.  // This is only possible with v5T ops (v4T can't change the Thumb bit via  // a POP PC instruction), and only if we do not need to emit any SP update.  // Otherwise, we need a temporary register to pop the value  // and copy that value into LR.  auto MBBI = MBB.getFirstTerminator();  bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;  if (CanRestoreDirectly) {    if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)      CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||                            MBBI->getOpcode() == ARM::tPOP_RET);    else {      auto MBBI_prev = MBBI;      MBBI_prev--;      assert(MBBI_prev->getOpcode() == ARM::tPOP);      assert(MBB.succ_size() == 1);      if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)        MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.      else        CanRestoreDirectly = false;    }  }  if (CanRestoreDirectly) {    if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)      return true;    MachineInstrBuilder MIB =        BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))            .add(predOps(ARMCC::AL));    // Copy implicit ops and popped registers, if any.    for (auto MO: MBBI->operands())      if (MO.isReg() && (MO.isImplicit() || MO.isDef()))        MIB.add(MO);    MIB.addReg(ARM::PC, RegState::Define);    // Erase the old instruction (tBX_RET or tPOP).    MBB.erase(MBBI);    return true;  }  // Look for a temporary register to use.  // First, compute the liveness information.  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();  LivePhysRegs UsedRegs(TRI);  UsedRegs.addLiveOuts(MBB);  // The semantic of pristines changed recently and now,  // the callee-saved registers that are touched in the function  // are not part of the pristines set anymore.  // Add those callee-saved now.  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);  for (unsigned i = 0; CSRegs[i]; ++i)    UsedRegs.addReg(CSRegs[i]);  DebugLoc dl = DebugLoc();  if (MBBI != MBB.end()) {    dl = MBBI->getDebugLoc();    auto InstUpToMBBI = MBB.end();    while (InstUpToMBBI != MBBI)      // The pre-decrement is on purpose here.      // We want to have the liveness right before MBBI.      UsedRegs.stepBackward(*--InstUpToMBBI);  }  // Look for a register that can be directly use in the POP.  unsigned PopReg = 0;  // And some temporary register, just in case.  unsigned TemporaryReg = 0;  BitVector PopFriendly =      TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));  assert(PopFriendly.any() && "No allocatable pop-friendly register?!");  // Rebuild the GPRs from the high registers because they are removed  // form the GPR reg class for thumb1.  BitVector GPRsNoLRSP =      TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));  GPRsNoLRSP |= PopFriendly;  GPRsNoLRSP.reset(ARM::LR);  GPRsNoLRSP.reset(ARM::SP);  GPRsNoLRSP.reset(ARM::PC);  findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);  // If we couldn't find a pop-friendly register, restore LR before popping the  // other callee-saved registers, so we can use one of them as a temporary.  bool UseLDRSP = false;  if (!PopReg && MBBI != MBB.begin()) {    auto PrevMBBI = MBBI;    PrevMBBI--;    if (PrevMBBI->getOpcode() == ARM::tPOP) {      MBBI = PrevMBBI;      UsedRegs.stepBackward(*MBBI);      findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);//.........这里部分代码省略.........