自学教程：C++ CLK函数代码示例

};static struct clk ethclk = {	.name       = "stmmaceth",	.parent     = &sclk0,	.ops	    = &dummy_clk_ops,};static struct clk spiclk = {	.name       = "spi",	.parent     = &sclk1,	.ops        = &dummy_clk_ops,};static struct clk_lookup bf609_clks[] = {	CLK(sys_clkin, NULL, "SYS_CLKIN"),	CLK(pll_clk, NULL, "PLLCLK"),	CLK(cclk, NULL, "CCLK"),	CLK(cclk0, NULL, "CCLK0"),	CLK(cclk1, NULL, "CCLK1"),	CLK(sysclk, NULL, "SYSCLK"),	CLK(sclk0, NULL, "SCLK0"),	CLK(sclk1, NULL, "SCLK1"),	CLK(dclk, NULL, "DCLK"),	CLK(oclk, NULL, "OCLK"),	CLK(ethclk, NULL, "stmmaceth"),	CLK(spiclk, NULL, "spi"),};int __init clk_init(void){

static struct clk mmcsd_clk = {	.name		= "mmcsd",	.parent		= &pll0_sysclk2,	.lpsc		= DA8XX_LPSC0_MMC_SD,};static struct clk aemif_clk = {	.name		= "aemif",	.parent		= &pll0_sysclk3,	.lpsc		= DA8XX_LPSC0_EMIF25,	.flags		= ALWAYS_ENABLED,};static struct clk_lookup da850_clks[] = {	CLK(NULL,		"ref",		&ref_clk),	CLK(NULL,		"pll0",		&pll0_clk),	CLK(NULL,		"pll0_aux",	&pll0_aux_clk),	CLK(NULL,		"pll0_sysclk2",	&pll0_sysclk2),	CLK(NULL,		"pll0_sysclk3",	&pll0_sysclk3),	CLK(NULL,		"pll0_sysclk4",	&pll0_sysclk4),	CLK(NULL,		"pll0_sysclk5",	&pll0_sysclk5),	CLK(NULL,		"pll0_sysclk6",	&pll0_sysclk6),	CLK(NULL,		"pll0_sysclk7",	&pll0_sysclk7),	CLK(NULL,		"pll1",		&pll1_clk),	CLK(NULL,		"pll1_aux",	&pll1_aux_clk),	CLK(NULL,		"pll1_sysclk2",	&pll1_sysclk2),	CLK(NULL,		"pll1_sysclk3",	&pll1_sysclk3),	CLK(NULL,		"pll1_sysclk4",	&pll1_sysclk4),	CLK(NULL,		"pll1_sysclk5",	&pll1_sysclk5),	CLK(NULL,		"pll1_sysclk6",	&pll1_sysclk6),

	.name		= "ecap0_clk",	.parent		= &ecap_clk,};static struct clk ecap1_clk = {	.name		= "ecap1_clk",	.parent		= &ecap_clk,};static struct clk ecap2_clk = {	.name		= "ecap2_clk",	.parent		= &ecap_clk,};static struct clk_lookup da850_clks[] = {	CLK(NULL,		"ref",		&ref_clk),	CLK(NULL,		"pll0",		&pll0_clk),	CLK(NULL,		"pll0_aux",	&pll0_aux_clk),	CLK(NULL,		"pll0_sysclk1",	&pll0_sysclk1),	CLK(NULL,		"pll0_sysclk2",	&pll0_sysclk2),	CLK(NULL,		"pll0_sysclk3",	&pll0_sysclk3),	CLK(NULL,		"pll0_sysclk4",	&pll0_sysclk4),	CLK(NULL,		"pll0_sysclk5",	&pll0_sysclk5),	CLK(NULL,		"pll0_sysclk6",	&pll0_sysclk6),	CLK(NULL,		"pll0_sysclk7",	&pll0_sysclk7),	CLK(NULL,		"pll1",		&pll1_clk),	CLK(NULL,		"pll1_aux",	&pll1_aux_clk),	CLK(NULL,		"pll1_sysclk2",	&pll1_sysclk2),	CLK(NULL,		"pll1_sysclk3",	&pll1_sysclk3),	CLK(NULL,		"async3",	&async3_clk),	CLK("i2c_davinci.1",	NULL,		&i2c0_clk),

static struct clk timer1_clk = {	.name = "timer1",	.parent = &pll1_aux_clk,	.lpsc = DAVINCI_LPSC_TIMER1,};static struct clk timer2_clk = {	.name = "timer2",	.parent = &pll1_aux_clk,	.lpsc = DAVINCI_LPSC_TIMER2,	.usecount = 1,              /* REVISIT: why can't' this be disabled? */};static struct clk_lookup dm644x_clks[] = {	CLK(NULL, "ref", &ref_clk),	CLK(NULL, "pll1", &pll1_clk),	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),	CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),	CLK(NULL, "pll1_aux", &pll1_aux_clk),	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),	CLK(NULL, "pll2", &pll2_clk),	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),	CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),	CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),	CLK(NULL, "dsp", &dsp_clk),	CLK(NULL, "arm", &arm_clk),	CLK(NULL, "vicp", &vicp_clk),	CLK(NULL, "vpss_master", &vpss_master_clk),

#define CLK(addr)  /{ /	.clk_name=#addr, /	.clk_addr=addr, /	.clk_flag=0, /}struct clk_desc{    char* clk_name;    unsigned clk_addr;    unsigned clk_flag;} ;struct clk_desc clks[] = {	CLK(P_HHI_MPEG_CLK_CNTL),};static void uart_change_buad(unsigned reg,unsigned clk_rate){	aml_clr_reg32_mask(reg, 0x7FFFFF);	aml_set_reg32_bits(reg, (((clk_rate / (115200 * 4)) - 1) & 0x7fffff)|(1<<23), 0, 24);}static void wait_uart_empty(void){	do{		udelay(100);	}while((aml_read_reg32(P_AO_UART_STATUS) & (1<<22)) == 0);	}void clk_switch(int flag){

enum {	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */};/* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. * * Note: *  The extra column in each clock source array is used to store the mask *  bits in its register for the source. */#define CLK(x) CLOCK_ID_ ## xstatic enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {	{ CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),		MASK_BITS_31_30},	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),		MASK_BITS_31_30},	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),		MASK_BITS_31_30},	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE),		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),		MASK_BITS_31_30},	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),		MASK_BITS_31_30},	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),

static struct clk usb11_clk = {	.name		= "usb11",	.parent		= &pll0_sysclk4,	.lpsc		= DA8XX_LPSC1_USB11,	.gpsc		= 1,};static struct clk usb20_clk = {	.name		= "usb20",	.parent		= &pll0_sysclk2,	.lpsc		= DA8XX_LPSC1_USB20,	.gpsc		= 1,};static struct clk_lookup da850_clks[] = {	CLK(NULL,		"ref",		&ref_clk),	CLK(NULL,		"pll0",		&pll0_clk),	CLK(NULL,		"pll0_aux",	&pll0_aux_clk),	CLK(NULL,		"pll0_sysclk2",	&pll0_sysclk2),	CLK(NULL,		"pll0_sysclk3",	&pll0_sysclk3),	CLK(NULL,		"pll0_sysclk4",	&pll0_sysclk4),	CLK(NULL,		"pll0_sysclk5",	&pll0_sysclk5),	CLK(NULL,		"pll0_sysclk6",	&pll0_sysclk6),	CLK(NULL,		"pll0_sysclk7",	&pll0_sysclk7),	CLK(NULL,		"pll1",		&pll1_clk),	CLK(NULL,		"pll1_aux",	&pll1_aux_clk),	CLK(NULL,		"pll1_sysclk2",	&pll1_sysclk2),	CLK(NULL,		"pll1_sysclk3",	&pll1_sysclk3),	CLK(NULL,		"pll1_sysclk4",	&pll1_sysclk4),	CLK(NULL,		"pll1_sysclk5",	&pll1_sysclk5),	CLK(NULL,		"pll1_sysclk6",	&pll1_sysclk6),

};enum {	CLOCK_MAX_MUX	= 4	/* number of source options for each clock */};/* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS * is special as it has 5 sources. Since it also has a different number of * bits in its register for the source, we just handle it with a special * case in the code. */#define CLK(x) CLOCK_ID_ ## xstatic enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC)	},	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO)	},	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC)	},	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE)	},	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(XCPU),	CLK(OSC)	},	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC)	},};/* * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is * not in the header file since it is for purely internal use - we want * callers to use the PERIPH_ID for all access to peripheral clocks to avoid * confusion bewteen PERIPH_ID_... and PERIPHC_... *

static struct clk i2c_ick = {	.name		= "i2c_ick",	.ops		= &clkops_null,	.flags		= CLOCK_NO_IDLE_PARENT,	.parent		= &armper_ck.clk,	.recalc		= &followparent_recalc,};/* * clkdev integration */static struct omap_clk omap_clks[] = {	/* non-ULPD clocks */	CLK(NULL,	"ck_ref",	&ck_ref,	CK_16XX | CK_1510 | CK_310 | CK_7XX),	CLK(NULL,	"ck_dpll1",	&ck_dpll1,	CK_16XX | CK_1510 | CK_310 | CK_7XX),	/* CK_GEN1 clocks */	CLK(NULL,	"ck_dpll1out",	&ck_dpll1out.clk, CK_16XX),	CLK(NULL,	"ck_sossi",	&sossi_ck,	CK_16XX),	CLK(NULL,	"arm_ck",	&arm_ck,	CK_16XX | CK_1510 | CK_310),	CLK(NULL,	"armper_ck",	&armper_ck.clk,	CK_16XX | CK_1510 | CK_310),	CLK("omap_gpio.0", "ick",	&arm_gpio_ck,	CK_1510 | CK_310),	CLK(NULL,	"armxor_ck",	&armxor_ck.clk,	CK_16XX | CK_1510 | CK_310 | CK_7XX),	CLK(NULL,	"armtim_ck",	&armtim_ck.clk,	CK_16XX | CK_1510 | CK_310),	CLK("omap_wdt",	"fck",		&armwdt_ck.clk,	CK_16XX | CK_1510 | CK_310),	CLK("omap_wdt",	"ick",		&armper_ck.clk,	CK_16XX),	CLK("omap_wdt", "ick",		&dummy_ck,	CK_1510 | CK_310),	CLK(NULL,	"arminth_ck",	&arminth_ck1510, CK_1510 | CK_310),	CLK(NULL,	"arminth_ck",	&arminth_ck16xx, CK_16XX),	/* CK_GEN2 clocks */

/*===================================================================*/void K6502_Step( WORD wClocks ){/* *  Only the specified number of the clocks execute Op. * *  Parameters *    WORD wClocks              (Read) *      The number of the clocks */  BYTE byCode;  WORD wA0;  BYTE byD0;  BYTE byD1;  WORD wD0;  // Dispose of it if there is an interrupt requirement  if ( NMI_State != NMI_Wiring )  {    // NMI Interrupt    NMI_State = NMI_Wiring;    CLK( 7 );    PUSHW( PC );    PUSH( F & ~FLAG_B );    RSTF( FLAG_D );    SETF( FLAG_I );    PC = K6502_ReadW( VECTOR_NMI );  }  else  if ( IRQ_State != IRQ_Wiring )  {    // IRQ Interrupt    // Execute IRQ if an I flag isn't being set    if ( !( F & FLAG_I ) )    {      IRQ_State = IRQ_Wiring;      CLK( 7 );      PUSHW( PC );      PUSH( F & ~FLAG_B );      RSTF( FLAG_D );      SETF( FLAG_I );          PC = K6502_ReadW( VECTOR_IRQ );    }  }  // It has a loop until a constant clock passes  while ( g_wPassedClocks < wClocks )  {    // Read an instruction    byCode = K6502_Read( PC++ );    // Execute an instruction.    switch ( byCode )    {      case 0x00:  // BRK        ++PC; PUSHW( PC ); SETF( FLAG_B ); PUSH( F ); SETF( FLAG_I ); RSTF( FLAG_D ); PC = K6502_ReadW( VECTOR_IRQ ); CLK( 7 );        break;      case 0x01:  // ORA (Zpg,X)        ORA( A_IX ); CLK( 6 );        break;      case 0x05:  // ORA Zpg        ORA( A_ZP ); CLK( 3 );        break;      case 0x06:  // ASL Zpg        ASL( AA_ZP ); CLK( 5 );        break;      case 0x08:  // PHP        SETF( FLAG_B ); PUSH( F ); CLK( 3 );        break;      case 0x09:  // ORA #Oper        ORA( A_IMM ); CLK( 2 );        break;      case 0x0A:  // ASL A        ASLA; CLK( 2 );        break;      case 0x0D:  // ORA Abs        ORA( A_ABS ); CLK( 4 );        break;      case 0x0e:  // ASL Abs         ASL( AA_ABS ); CLK( 6 );        break;      case 0x10: // BPL Oper        BRA( !( F & FLAG_N ) );//.........这里部分代码省略.........

lpsc_clk(usb0,		clk_usbss,		USB0);lpsc_clk(usb1,		clk_usbss,		USB1);lpsc_clk(ethss_rgmii,	eth_250mhz_clk,		ETHSS_RGMII);lpsc_clk(imcop,		sys_dsp_clk,		IMCOP);lpsc_clk(spare,		sys_half_clk,		SPARE);/*                                                       */__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE);/*                                                              */static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec };static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec };static struct clk_lookup clks[] = {	CLK(NULL,		"pll_sys_clk",		&pll_sys_clk),	CLK(NULL,		"pll_eth_clk",		&pll_eth_clk),	CLK(NULL,		"pll_tdm_clk",		&pll_tdm_clk),	CLK(NULL,		"sys_arm1176_clk",	&sys_arm1176_clk),	CLK(NULL,		"sys_dsp_clk",		&sys_dsp_clk),	CLK(NULL,		"sys_ddr_clk",		&sys_ddr_clk),	CLK(NULL,		"sys_full_clk",		&sys_full_clk),	CLK(NULL,		"sys_lcd_clk",		&sys_lcd_clk),	CLK(NULL,		"sys_vlynq_ref_clk",	&sys_vlynq_ref_clk),	CLK(NULL,		"sys_tsc_clk",		&sys_tsc_clk),	CLK(NULL,		"sys_half_clk",		&sys_half_clk),	CLK(NULL,		"eth_5mhz_clk",		&eth_5mhz_clk),	CLK(NULL,		"eth_50mhz_clk",	&eth_50mhz_clk),	CLK(NULL,		"eth_125mhz_clk",	&eth_125mhz_clk),	CLK(NULL,		"eth_250mhz_clk",	&eth_250mhz_clk),	CLK(NULL,		"eth_25mhz_clk",	&eth_25mhz_clk),

// (Indirect),Ystatic inline BYTE K6502_ReadIY(){ WORD wA0, wA1; wA0 = K6502_ReadZpW( K6502_Read( PC++ ) ); wA1 = wA0 + Y; CLK( ( wA0 & 0x0100 ) != ( wA1 & 0x0100 ) ); return K6502_Read( wA1 ); };

// Absolute,Ystatic inline BYTE K6502_ReadAbsY(){ WORD wA0, wA1; wA0 = AA_ABS; wA1 = wA0 + Y; CLK( ( wA0 & 0x0100 ) != ( wA1 & 0x0100 ) ); return K6502_Read( wA1 ); };

static struct clk vpif0_clk = {	.name = "vpif0",	.parent = &ref_clk,	.lpsc = DM646X_LPSC_VPSSMSTR,	.flags = ALWAYS_ENABLED,};static struct clk vpif1_clk = {	.name = "vpif1",	.parent = &ref_clk,	.lpsc = DM646X_LPSC_VPSSSLV,	.flags = ALWAYS_ENABLED,};struct davinci_clk dm646x_clks[] = {	CLK(NULL, "ref", &ref_clk),	CLK(NULL, "aux", &aux_clkin),	CLK(NULL, "pll1", &pll1_clk),	CLK(NULL, "pll1_sysclk", &pll1_sysclk1),	CLK(NULL, "pll1_sysclk", &pll1_sysclk2),	CLK(NULL, "pll1_sysclk", &pll1_sysclk3),	CLK(NULL, "pll1_sysclk", &pll1_sysclk4),	CLK(NULL, "pll1_sysclk", &pll1_sysclk5),	CLK(NULL, "pll1_sysclk", &pll1_sysclk6),	CLK(NULL, "pll1_sysclk", &pll1_sysclk8),	CLK(NULL, "pll1_sysclk", &pll1_sysclk9),	CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),	CLK(NULL, "pll1_aux", &pll1_aux_clk),	CLK(NULL, "pll2", &pll2_clk),	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),	CLK(NULL, "dsp", &dsp_clk),

#define CLK(dev, con, ck, cp) 		/	{				/		 .cpu = cp,		/		.lk = {			/			.dev_id = dev,	/			.con_id = con,	/			.clk = ck,	/		},			/	}#define CK_243X			RATE_IN_243X#define CK_242X			RATE_IN_242Xstatic struct omap_clk omap24xx_clks[] = {	/* external root sources */	CLK(NULL,	"func_32k_ck",	&func_32k_ck,	CK_243X | CK_242X),	CLK(NULL,	"secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),	CLK(NULL,	"osc_ck",	&osc_ck,	CK_243X | CK_242X),	CLK(NULL,	"sys_ck",	&sys_ck,	CK_243X | CK_242X),	CLK(NULL,	"alt_ck",	&alt_ck,	CK_243X | CK_242X),	/* internal analog sources */	CLK(NULL,	"dpll_ck",	&dpll_ck,	CK_243X | CK_242X),	CLK(NULL,	"apll96_ck",	&apll96_ck,	CK_243X | CK_242X),	CLK(NULL,	"apll54_ck",	&apll54_ck,	CK_243X | CK_242X),	/* internal prcm root sources */	CLK(NULL,	"func_54m_ck",	&func_54m_ck,	CK_243X | CK_242X),	CLK(NULL,	"core_ck",	&core_ck,	CK_243X | CK_242X),	CLK(NULL,	"func_96m_ck",	&func_96m_ck,	CK_243X | CK_242X),	CLK(NULL,	"func_48m_ck",	&func_48m_ck,	CK_243X | CK_242X),	CLK(NULL,	"func_12m_ck",	&func_12m_ck,	CK_243X | CK_242X),	CLK(NULL,	"ck_wdt1_osc",	&wdt1_osc_ck,	CK_243X | CK_242X),

	.hw	= {		.clk	= &wdt1_fck,	},	.clkdm_name	= "l4_wkup_clkdm",	.clksel		= wdt_clkmux_sel,	.clksel_reg	= AM33XX_CLKSEL_WDT1_CLK,	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,};DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);/* * clkdev */static struct omap_clk am33xx_clks[] = {	CLK(NULL,	"clk_32768_ck",		&clk_32768_ck),	CLK(NULL,	"clk_rc32k_ck",		&clk_rc32k_ck),	CLK(NULL,	"virt_19200000_ck",	&virt_19200000_ck),	CLK(NULL,	"virt_24000000_ck",	&virt_24000000_ck),	CLK(NULL,	"virt_25000000_ck",	&virt_25000000_ck),	CLK(NULL,	"virt_26000000_ck",	&virt_26000000_ck),	CLK(NULL,	"sys_clkin_ck",		&sys_clkin_ck),	CLK(NULL,	"tclkin_ck",		&tclkin_ck),	CLK(NULL,	"dpll_core_ck",		&dpll_core_ck),	CLK(NULL,	"dpll_core_x2_ck",	&dpll_core_x2_ck),	CLK(NULL,	"dpll_core_m4_ck",	&dpll_core_m4_ck),	CLK(NULL,	"dpll_core_m5_ck",	&dpll_core_m5_ck),	CLK(NULL,	"dpll_core_m6_ck",	&dpll_core_m6_ck),	CLK(NULL,	"dpll_mpu_ck",		&dpll_mpu_ck),	CLK("cpu0",	NULL,			&dpll_mpu_ck),	CLK(NULL,	"dpll_mpu_m2_ck",	&dpll_mpu_m2_ck),

};static struct clk rto_clk = {	.name		= "rto",	.parent		= &pll1_sysclk4,	.lpsc		= DM365_LPSC_RTO,};static struct clk mjcp_clk = {	.name		= "mjcp",	.parent		= &pll1_sysclk3,	.lpsc		= DM365_LPSC_MJCP,};static struct clk_lookup dm365_clks[] = {	CLK(NULL, "ref", &ref_clk),	CLK(NULL, "pll1", &pll1_clk),	CLK(NULL, "pll1_aux", &pll1_aux_clk),	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),	CLK(NULL, "clkout0", &clkout0_clk),	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),	CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),	CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),	CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),	CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),	CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),	CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),	CLK(NULL, "pll2", &pll2_clk),	CLK(NULL, "pll2_aux", &pll2_aux_clk),

			CLK_HALT_STATEA_REG, HALT, 13, 0x4D4F),	CLK_MND16(MI2S_CODEC_TX_M, MI2S_TX_NS_REG, B(12), B(11),				clk_tbl_mi2s_codec, NONE, chld_mi2s_codec_tx,				CLK_HALT_STATEC_REG, HALT, 8, 0x4D50),	CLK_SLAVE(MI2S_CODEC_TX_S, MI2S_TX_NS_REG, B(9), MI2S_CODEC_TX_M,			CLK_HALT_STATEA_REG, HALT, 11, 0x17),	CLK_MND16(MI2S_M, MI2S_NS_REG, B(12), B(11),			clk_tbl_mi2s, NONE, chld_mi2s, CLK_HALT_STATEC_REG,			HALT, 4, 0x0D),	CLK_SLAVE(MI2S_S, MI2S_NS_REG, B(9), MI2S_M, CLK_HALT_STATEC_REG,			HALT, 3, 0),	CLK(GRP_2D, BASIC, GRP_2D_NS_REG, GRP_2D_NS_REG, NULL, NULL, 0,			CLK_HALT_STATEA_REG, HALT, 31, B(7), B(11),			F_MASK_BASIC | (7 << 12), 0, set_rate_basic,			clk_tbl_grp, NULL, AXI_GRP_2D, NULL, 0x5C00),	CLK(GRP_3D_SRC, BASIC, GRP_NS_REG, GRP_NS_REG, NULL, NULL, 0,			NULL, NOCHECK, 0, 0, B(11), F_MASK_BASIC | (7 << 12),			0, set_rate_basic, clk_tbl_grp, NULL, AXI_LI_GRP,			chld_grp_3d_src, 0),	CLK_SLAVE(GRP_3D, GRP_NS_REG, B(7), GRP_3D_SRC, CLK_HALT_STATEB_REG,			HALT, 18, 0x5E00),	CLK_SLAVE(IMEM, GRP_NS_REG, B(9), GRP_3D_SRC, CLK_HALT_STATEB_REG,			HALT, 19, 0x5F00),	CLK(LPA_CODEC, BASIC, LPA_NS_REG, LPA_NS_REG, NULL, NULL, 0,			CLK_HALT_STATEC_REG, HALT, 6, B(9), 0, BM(1, 0), 0,			set_rate_basic,	clk_tbl_lpa_codec, NULL, NONE, NULL,			0x0F),	CLK_MND8(CSI0, CSI_NS_REG, 24, 17, B(9), B(11), clk_tbl_csi, NULL,

};static struct clk clk_48 = {	.rate = 48 * 1000 * 1000,};static struct clk clk_default;#define CLK(_clk, dev)				/	{					/		.clk		= _clk,		/		.dev_id		= dev,		/	}static struct clk_lookup lookups[] = {	CLK(&clk_24, "mtu0"),	CLK(&clk_24, "mtu1"),	CLK(&clk_48, "uart0"),	CLK(&clk_48, "uart1"),	CLK(&clk_default, "gpio.0"),	CLK(&clk_default, "gpio.1"),	CLK(&clk_default, "gpio.2"),	CLK(&clk_default, "gpio.3"),	CLK(&clk_default, "rng"),};int __init clk_init(void){	clkdev_add_table(lookups, ARRAY_SIZE(lookups));	return 0;}

};static struct clk rto_clk = {	.name = "rto",	.parent = &pll1_aux_clk,	.lpsc = DM355_LPSC_RTO,};static struct clk usb_clk = {	.name = "usb",	.parent = &pll1_sysclk2,	.lpsc = DAVINCI_LPSC_USB,};static struct clk_lookup dm355_clks[] = {	CLK(NULL, "ref", &ref_clk),	CLK(NULL, "pll1", &pll1_clk),	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),	CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),	CLK(NULL, "pll1_aux", &pll1_aux_clk),	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),	CLK(NULL, "vpss_dac", &vpss_dac_clk),	CLK(NULL, "vpss_master", &vpss_master_clk),	CLK(NULL, "vpss_slave", &vpss_slave_clk),	CLK(NULL, "clkout1", &clkout1_clk),	CLK(NULL, "clkout2", &clkout2_clk),	CLK(NULL, "pll2", &pll2_clk),	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),	CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),

int sc_main (int argc, char **argv){  sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);   int NVAL;  if (argc != 2)  {    printf("Use: %s <N>/n", argv[0]);    return 1;  }  NVAL = atoi(argv[1]);  sc_signal<bool> RST_n_tb; /// asynchronous reset  sc_signal<bool> CLEAR_tb; /// synchronous clear port  sc_signal< sc_int<Cbit> > C0_tb;   sc_signal< sc_int<Cbit> > C1_tb;  sc_signal< sc_int<Abit> > A0_tb;  sc_signal< sc_int<Abit> > A1_tb;  sc_signal< sc_int<Abit> > A2_tb;  sc_signal< sc_int<Abit> > A3_tb;  sc_clock CLK("CLK", TB_CLK_PERIOD);  starter sta("sta", TB_CLK_PERIOD, TB_TPD);  data_gen dg("dg", TB_CLK_PERIOD, TB_TPD, NVAL);  data_writer dw("dw", TB_CLK_PERIOD, NVAL);  ACS4 uut("uut", TB_TPD, TB_TCO);  /// starter  sta.CLK(CLK);  sta.RST_n(RST_n_tb);  /// data gen  dg.CLK(CLK);  dg.CLEAR(CLEAR_tb);  dg.C0(C0_tb);  dg.C1(C1_tb);  /// uut  uut.CLK(CLK);  uut.RST_n(RST_n_tb);  uut.CLEAR(CLEAR_tb);  uut.C0(C0_tb);  uut.C1(C1_tb);  uut.A0(A0_tb);  uut.A1(A1_tb);  uut.A2(A2_tb);  uut.A3(A3_tb);	  /// write results  dw.CLK(CLK);  dw.A1(A1_tb);  dw.A2(A2_tb);  dw.A3(A3_tb);  dw.A0(A0_tb);  sc_trace_file *tf = sc_create_vcd_trace_file("uut");  ((vcd_trace_file*)tf)->sc_set_vcd_time_unit(-9);  sc_trace(tf, CLK, "CLK");  sc_trace(tf, RST_n_tb, "RST_n_tb");  sc_trace(tf, CLEAR_tb, "CLEAR_tb");  sc_trace(tf, C0_tb, "C0_tb");  sc_trace(tf, C1_tb, "C1_tb");  sc_trace(tf, A0_tb, "A0_tb");  sc_trace(tf, A1_tb, "A1_tb");  sc_trace(tf, A2_tb, "A2_tb");  sc_trace(tf, A3_tb, "A3_tb");  sc_start((NVAL+SIM_CYCLES_OFFSET)*TB_CLK_PERIOD, SC_NS);  sc_close_vcd_trace_file(tf);  return 0;}

struct clk c6x_mcbsp1_clk = {	.name = "mcbsp1",};struct clk c6x_mcbsp2_clk = {	.name = "mcbsp2",};struct clk c6x_mdio_clk = {	.name = "mdio",};#ifdef CONFIG_SOC_TMS320C6455static struct clk_lookup c6455_clks[] = {	CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),	CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),	CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),	CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),	CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),	CLK(NULL, "core", &c6x_core_clk),	CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),	CLK("watchdog", NULL, &c6x_watchdog_clk),	CLK("2c81800.mdio", NULL, &c6x_mdio_clk),	CLK("", NULL, NULL)};static void __init c6455_setup_clocks(struct device_node *node){	struct pll_data *pll = &c6x_soc_pll1;	struct clk *sysclks = pll->sysclks;

			HALT, 13, 0x7000),	CLK_SLAVE(CSI0_VFE, CSI_NS_REG, BIT(15), VFE, CLK_HALT_STATEC_REG,			HALT, 16, 0),	CLK_MND16(SDAC, SDAC_NS_REG, BIT(9), BIT(11), clk_tbl_sdac,			NONE, chld_sdac, CLK_HALT_STATEA_REG, HALT, 2, 0x4D60),	CLK_SLAVE(SDAC_M, SDAC_NS_REG, BIT(12), SDAC, CLK_HALT_STATEB_REG,			HALT, 17, 0x4D66),	CLK_MND16(MDP_LCDC_PCLK, MDP_LCDC_NS_REG, BIT(9), BIT(11),			clk_tbl_mdp_lcdc, NONE, chld_mdp_lcdc_p,			CLK_HALT_STATEB_REG, HALT, 28, 0x4200),	CLK_SLAVE(MDP_LCDC_PAD_PCLK, MDP_LCDC_NS_REG, BIT(12), MDP_LCDC_PCLK,			CLK_HALT_STATEB_REG, HALT, 29, 0x4100),	CLK(MDP_VSYNC, BASIC, MDP_VSYNC_REG, MDP_VSYNC_REG, NULL, NULL, 0,			CLK_HALT_STATEB_REG, HALT, 30, BIT(0), 0, BM(3, 2), 0,			set_rate_nop, clk_tbl_mdp_vsync, NULL, NONE, NULL,			0x4D53),	CLK_MND16(MI2S_CODEC_RX_M, MI2S_RX_NS_REG, BIT(12), BIT(11),				clk_tbl_mi2s_codec, NONE, chld_mi2s_codec_rx,				CLK_HALT_STATEA_REG, HALT, 12, 0x4D4E),	CLK_SLAVE(MI2S_CODEC_RX_S, MI2S_RX_NS_REG, BIT(9), MI2S_CODEC_RX_M,			CLK_HALT_STATEA_REG, HALT, 13, 0x4D4F),	CLK_MND16(MI2S_CODEC_TX_M, MI2S_TX_NS_REG, BIT(12), BIT(11),				clk_tbl_mi2s_codec, NONE, chld_mi2s_codec_tx,				CLK_HALT_STATEC_REG, HALT, 8, 0x4D50),	CLK_SLAVE(MI2S_CODEC_TX_S, MI2S_TX_NS_REG, BIT(9), MI2S_CODEC_TX_M,			CLK_HALT_STATEA_REG, HALT, 11, 0x17),	CLK_MND16(MI2S_M, MI2S_NS_REG, BIT(12), BIT(11),

#define CLK(dev, con, ck, cp) 		/	{				/		 .cpu = cp,		/		.lk = {			/			.dev_id = dev,	/			.con_id = con,	/			.clk = ck,	/		},			/	}#define CK_343X		(1 << 0)#define CK_3430ES1	(1 << 1)#define CK_3430ES2	(1 << 2)static struct omap_clk omap34xx_clks[] = {	CLK(NULL,	"omap_32k_fck",	&omap_32k_fck,	CK_343X),	CLK(NULL,	"virt_12m_ck",	&virt_12m_ck,	CK_343X),	CLK(NULL,	"virt_13m_ck",	&virt_13m_ck,	CK_343X),	CLK(NULL,	"virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),	CLK(NULL,	"virt_19_2m_ck", &virt_19_2m_ck, CK_343X),	CLK(NULL,	"virt_26m_ck",	&virt_26m_ck,	CK_343X),	CLK(NULL,	"virt_38_4m_ck", &virt_38_4m_ck, CK_343X),	CLK(NULL,	"osc_sys_ck",	&osc_sys_ck,	CK_343X),	CLK(NULL,	"sys_ck",	&sys_ck,	CK_343X),	CLK(NULL,	"sys_altclk",	&sys_altclk,	CK_343X),	CLK(NULL,	"mcbsp_clks",	&mcbsp_clks,	CK_343X),	CLK(NULL,	"sys_clkout1",	&sys_clkout1,	CK_343X),	CLK(NULL,	"dpll1_ck",	&dpll1_ck,	CK_343X),	CLK(NULL,	"dpll1_x2_ck",	&dpll1_x2_ck,	CK_343X),	CLK(NULL,	"dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),	CLK(NULL,	"dpll2_ck",	&dpll2_ck,	CK_343X),

	.mask       = CGU0_DIV_DSEL_MASK,	.shift       = CGU0_DIV_DSEL_SHIFT,	.parent     = &sys_clkin,	.ops	    = &sys_clk_ops,};static struct clk oclk = {	.name       = "OCLK",	.rate       = 500000000,	.mask       = CGU0_DIV_OSEL_MASK,	.shift      = CGU0_DIV_OSEL_SHIFT,	.parent     = &pll_clk,};static struct clk_lookup bf609_clks[] = {	CLK(sys_clkin, NULL, "SYS_CLKIN"),	CLK(pll_clk, NULL, "PLLCLK"),	CLK(cclk, NULL, "CCLK"),	CLK(cclk0, NULL, "CCLK0"),	CLK(cclk1, NULL, "CCLK1"),	CLK(sysclk, NULL, "SYSCLK"),	CLK(sclk0, NULL, "SCLK0"),	CLK(sclk1, NULL, "SCLK1"),	CLK(dclk, NULL, "DCLK"),	CLK(oclk, NULL, "OCLK"),};int __init clk_init(void){	int i;	struct clk *clkp;