自学教程：C++ CONST_INT_P函数代码示例

static boolaarch_rev16_p_1 (rtx lhs, rtx rhs, enum machine_mode mode){  if (GET_CODE (lhs) == AND         && GET_CODE (XEXP (lhs, 0)) == ASHIFT            && CONST_INT_P (XEXP (XEXP (lhs, 0), 1))            && INTVAL (XEXP (XEXP (lhs, 0), 1)) == 8            && REG_P (XEXP (XEXP (lhs, 0), 0))         && CONST_INT_P (XEXP (lhs, 1))      && GET_CODE (rhs) == AND         && GET_CODE (XEXP (rhs, 0)) == LSHIFTRT            && REG_P (XEXP (XEXP (rhs, 0), 0))            && CONST_INT_P (XEXP (XEXP (rhs, 0), 1))            && INTVAL (XEXP (XEXP (rhs, 0), 1)) == 8         && CONST_INT_P (XEXP (rhs, 1))      && REGNO (XEXP (XEXP (rhs, 0), 0)) == REGNO (XEXP (XEXP (lhs, 0), 0)))    {      rtx lhs_mask = XEXP (lhs, 1);      rtx rhs_mask = XEXP (rhs, 1);      return aarch_rev16_shright_mask_imm_p (rhs_mask, mode)             && aarch_rev16_shleft_mask_imm_p (lhs_mask, mode);    }  return false;}

static rtxnds32_gen_dup_4_byte_to_word_value_aux (rtx value, rtx value4word){  gcc_assert (GET_MODE (value) == QImode || CONST_INT_P (value));  if (CONST_INT_P (value))    {      unsigned HOST_WIDE_INT val = UINTVAL (value) & GET_MODE_MASK(QImode);      rtx new_val = gen_int_mode (val | (val << 8)				  | (val << 16) | (val << 24), SImode);      /* Just calculate at here if it's constant value.  */      emit_move_insn (value4word, new_val);    }  else    {      if (NDS32_EXT_DSP_P ())	{	  /* ! prepare word	     insb    $tmp, $value, 1         ! $tmp  <- 0x0000abab	     pkbb16  $tmp6, $tmp2, $tmp2   ! $value4word  <- 0xabababab */	  rtx tmp = gen_reg_rtx (SImode);	  convert_move (tmp, value, true);	  emit_insn (	    gen_insvsi_internal (tmp, gen_int_mode (0x8, SImode), tmp));	  emit_insn (gen_pkbbsi_1 (value4word, tmp, tmp));	}      else	{	  /* ! prepare word	     andi    $tmp1, $value, 0xff       ! $tmp1  <- 0x000000ab	     slli    $tmp2, $tmp1, 8           ! $tmp2  <- 0x0000ab00	     or      $tmp3, $tmp1, $tmp2       ! $tmp3  <- 0x0000abab	     slli    $tmp4, $tmp3, 16          ! $tmp4  <- 0xabab0000	     or      $val4word, $tmp3, $tmp4   ! $value4word  <- 0xabababab  */	  rtx tmp1, tmp2, tmp3, tmp4;	  tmp1 = expand_binop (SImode, and_optab, value,			       gen_int_mode (0xff, SImode),			       NULL_RTX, 0, OPTAB_WIDEN);	  tmp2 = expand_binop (SImode, ashl_optab, tmp1,			       gen_int_mode (8, SImode),			       NULL_RTX, 0, OPTAB_WIDEN);	  tmp3 = expand_binop (SImode, ior_optab, tmp1, tmp2,			       NULL_RTX, 0, OPTAB_WIDEN);	  tmp4 = expand_binop (SImode, ashl_optab, tmp3,			       gen_int_mode (16, SImode),			       NULL_RTX, 0, OPTAB_WIDEN);	  emit_insn (gen_iorsi3 (value4word, tmp3, tmp4));	}    }  return value4word;}

static inline intlocal_symbolic_operand_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)#line 442 "../.././gcc/config/i386/predicates.md"{  if (GET_CODE (op) == CONST      && GET_CODE (XEXP (op, 0)) == PLUS      && CONST_INT_P (XEXP (XEXP (op, 0), 1)))    op = XEXP (XEXP (op, 0), 0);  if (GET_CODE (op) == LABEL_REF)    return 1;  if (GET_CODE (op) != SYMBOL_REF)    return 0;  if (SYMBOL_REF_TLS_MODEL (op) != 0)    return 0;  if (SYMBOL_REF_LOCAL_P (op))    return 1;  /* There is, however, a not insubstantial body of code in the rest of     the compiler that assumes it can just stick the results of     ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done.  */  /* ??? This is a hack.  Should update the body of the compiler to     always create a DECL an invoke targetm.encode_section_info.  */  if (strncmp (XSTR (op, 0), internal_label_prefix,	       internal_label_prefix_len) == 0)    return 1;  return 0;}

static inline intpic_symbolic_operand_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)#line 412 "../.././gcc/config/i386/predicates.md"{  op = XEXP (op, 0);  if (TARGET_64BIT)    {      if (GET_CODE (op) == UNSPEC	  && XINT (op, 1) == UNSPEC_GOTPCREL)	return 1;      if (GET_CODE (op) == PLUS	  && GET_CODE (XEXP (op, 0)) == UNSPEC	  && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL)	return 1;    }  else    {      if (GET_CODE (op) == UNSPEC)	return 1;      if (GET_CODE (op) != PLUS	  || !CONST_INT_P (XEXP (op, 1)))	return 0;      op = XEXP (op, 0);      if (GET_CODE (op) == UNSPEC	  && XINT (op, 1) != UNSPEC_MACHOPIC_OFFSET)	return 1;    }  return 0;}

static voidadjust_frame_related_expr (rtx last_sp_set, rtx insn,			   HOST_WIDE_INT this_adjust){  rtx note = find_reg_note (last_sp_set, REG_FRAME_RELATED_EXPR, NULL_RTX);  rtx new_expr = NULL_RTX;  if (note == NULL_RTX && RTX_FRAME_RELATED_P (insn))    return;  if (note      && GET_CODE (XEXP (note, 0)) == SEQUENCE      && XVECLEN (XEXP (note, 0), 0) >= 2)    {      rtx expr = XEXP (note, 0);      rtx last = XVECEXP (expr, 0, XVECLEN (expr, 0) - 1);      int i;      if (GET_CODE (last) == SET	  && RTX_FRAME_RELATED_P (last) == RTX_FRAME_RELATED_P (insn)	  && SET_DEST (last) == stack_pointer_rtx	  && GET_CODE (SET_SRC (last)) == PLUS	  && XEXP (SET_SRC (last), 0) == stack_pointer_rtx	  && CONST_INT_P (XEXP (SET_SRC (last), 1)))	{	  XEXP (SET_SRC (last), 1)	    = GEN_INT (INTVAL (XEXP (SET_SRC (last), 1)) + this_adjust);	  return;	}      new_expr = gen_rtx_SEQUENCE (VOIDmode,				   rtvec_alloc (XVECLEN (expr, 0) + 1));      for (i = 0; i < XVECLEN (expr, 0); i++)	XVECEXP (new_expr, 0, i) = XVECEXP (expr, 0, i);    }  else    {      new_expr = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2));      if (note)	XVECEXP (new_expr, 0, 0) = XEXP (note, 0);      else	{	  rtx expr = copy_rtx (single_set_for_csa (last_sp_set));	  XEXP (SET_SRC (expr), 1)	    = GEN_INT (INTVAL (XEXP (SET_SRC (expr), 1)) - this_adjust);	  RTX_FRAME_RELATED_P (expr) = 1;	  XVECEXP (new_expr, 0, 0) = expr;	}    }  XVECEXP (new_expr, 0, XVECLEN (new_expr, 0) - 1)    = copy_rtx (single_set_for_csa (insn));  RTX_FRAME_RELATED_P (XVECEXP (new_expr, 0, XVECLEN (new_expr, 0) - 1))    = RTX_FRAME_RELATED_P (insn);  if (note)    XEXP (note, 0) = new_expr;  else    add_reg_note (last_sp_set, REG_FRAME_RELATED_EXPR, new_expr);}

boolaarch_rev16_shleft_mask_imm_p (rtx val, enum machine_mode mode){  return CONST_INT_P (val)         && INTVAL (val)            == trunc_int_for_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff00),                                   mode);}

boolnds32_expand_strlen (rtx result, rtx str,		     rtx target_char, rtx align ATTRIBUTE_UNUSED){  rtx base_reg, backup_base_reg;  rtx ffb_result;  rtx target_char_ptr, length;  rtx loop_label, tmp;  if (optimize_size || optimize < 3)    return false;  gcc_assert (MEM_P (str));  gcc_assert (CONST_INT_P (target_char) || REG_P (target_char));  base_reg = copy_to_mode_reg (SImode, XEXP (str, 0));  loop_label = gen_label_rtx ();  ffb_result = gen_reg_rtx (Pmode);  tmp = gen_reg_rtx (SImode);  backup_base_reg = gen_reg_rtx (SImode);  /* Emit loop version of strlen.       move  $backup_base, $base     .Lloop:       lmw.bim $tmp, [$base], $tmp, 0       ffb   $ffb_result, $tmp, $target_char   ! is there $target_char?       beqz  $ffb_result, .Lloop       add   $last_char_ptr, $base, $ffb_result       sub   $length, $last_char_ptr, $backup_base  */  /* move  $backup_base, $base  */  emit_move_insn (backup_base_reg, base_reg);  /* .Lloop:  */  emit_label (loop_label);  /* lmw.bim $tmp, [$base], $tmp, 0  */  emit_insn (gen_unaligned_load_update_base_w (base_reg, tmp, base_reg));  /*  ffb   $ffb_result, $tmp, $target_char   ! is there $target_char?  */  emit_insn (gen_unspec_ffb (ffb_result, tmp, target_char));  /* beqz  $ffb_result, .Lloop  */  emit_cmp_and_jump_insns (ffb_result, const0_rtx, EQ, NULL,			   SImode, 1, loop_label);  /* add   $target_char_ptr, $base, $ffb_result   */  target_char_ptr = expand_binop (Pmode, add_optab, base_reg,				ffb_result, NULL_RTX, 0, OPTAB_WIDEN);  /* sub   $length, $target_char_ptr, $backup_base  */  length = expand_binop (Pmode, sub_optab, target_char_ptr,			 backup_base_reg, NULL_RTX, 0, OPTAB_WIDEN);  emit_move_insn (result, length);  return true;}

static inline intaligned_operand_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)#line 825 "../.././gcc/config/i386/predicates.md"{  struct ix86_address parts;  int ok;  /* Registers and immediate operands are always "aligned".  */  if (GET_CODE (op) != MEM)    return 1;  /* All patterns using aligned_operand on memory operands ends up     in promoting memory operand to 64bit and thus causing memory mismatch.  */  if (TARGET_MEMORY_MISMATCH_STALL && !optimize_size)    return 0;  /* Don't even try to do any aligned optimizations with volatiles.  */  if (MEM_VOLATILE_P (op))    return 0;  if (MEM_ALIGN (op) >= 32)    return 1;  op = XEXP (op, 0);  /* Pushes and pops are only valid on the stack pointer.  */  if (GET_CODE (op) == PRE_DEC      || GET_CODE (op) == POST_INC)    return 1;  /* Decode the address.  */  ok = ix86_decompose_address (op, &parts);  gcc_assert (ok);  /* Look for some component that isn't known to be aligned.  */  if (parts.index)    {      if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)	return 0;    }  if (parts.base)    {      if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)	return 0;    }  if (parts.disp)    {      if (!CONST_INT_P (parts.disp)	  || (INTVAL (parts.disp) & 3) != 0)	return 0;    }  /* Didn't find one -- this must be an aligned address.  */  return 1;}

/* Expand an AArch64 AdvSIMD builtin(intrinsic).  */rtxaarch64_simd_expand_builtin (int fcode, tree exp, rtx target){  aarch64_simd_builtin_datum *d =		&aarch64_simd_builtin_data[fcode - (AARCH64_SIMD_BUILTIN_BASE + 1)];  enum insn_code icode = d->code;  builtin_simd_arg args[SIMD_MAX_BUILTIN_ARGS];  int num_args = insn_data[d->code].n_operands;  int is_void = 0;  int k;  is_void = !!(d->qualifiers[0] & qualifier_void);  num_args += is_void;  for (k = 1; k < num_args; k++)    {      /* We have four arrays of data, each indexed in a different fashion.	 qualifiers - element 0 always describes the function return type.	 operands - element 0 is either the operand for return value (if	   the function has a non-void return type) or the operand for the	   first argument.	 expr_args - element 0 always holds the first argument.	 args - element 0 is always used for the return type.  */      int qualifiers_k = k;      int operands_k = k - is_void;      int expr_args_k = k - 1;      if (d->qualifiers[qualifiers_k] & qualifier_lane_index)	args[k] = SIMD_ARG_LANE_INDEX;      else if (d->qualifiers[qualifiers_k] & qualifier_immediate)	args[k] = SIMD_ARG_CONSTANT;      else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate)	{	  rtx arg	    = expand_normal (CALL_EXPR_ARG (exp,					    (expr_args_k)));	  /* Handle constants only if the predicate allows it.  */	  bool op_const_int_p =	    (CONST_INT_P (arg)	     && (*insn_data[icode].operand[operands_k].predicate)		(arg, insn_data[icode].operand[operands_k].mode));	  args[k] = op_const_int_p ? SIMD_ARG_CONSTANT : SIMD_ARG_COPY_TO_REG;	}      else	args[k] = SIMD_ARG_COPY_TO_REG;    }  args[k] = SIMD_ARG_STOP;  /* The interface to aarch64_simd_expand_args expects a 0 if     the function is void, and a 1 if it is not.  */  return aarch64_simd_expand_args	  (target, icode, !is_void, exp, &args[1]);}

boolshared_const_p (const_rtx orig){  gcc_assert (GET_CODE (orig) == CONST);  /* CONST can be shared if it contains a SYMBOL_REF.  If it contains     a LABEL_REF, it isn't sharable.  */  return (GET_CODE (XEXP (orig, 0)) == PLUS	  && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF	  && CONST_INT_P(XEXP (XEXP (orig, 0), 1)));}

static boolnds32_expand_movmemsi_loop (rtx dstmem, rtx srcmem,			    rtx size, rtx alignment){  if (CONST_INT_P (size))    return nds32_expand_movmemsi_loop_known_size (dstmem, srcmem,						  size, alignment);  else    return nds32_expand_movmemsi_loop_unknown_size (dstmem, srcmem,						    size, alignment);}

/* Compute the sum of X and Y, making canonicalizations assumed in an   address, namely: sum constant integers, surround the sum of two   constants with a CONST, put the constant as the second operand, and   group the constant on the outermost sum.   This routine assumes both inputs are already in canonical form.  */static rtxform_sum (rtx x, rtx y){  machine_mode mode = GET_MODE (x);  if (mode == VOIDmode)    mode = GET_MODE (y);  if (mode == VOIDmode)    mode = Pmode;  if (CONST_INT_P (x))    return plus_constant (mode, y, INTVAL (x));  else if (CONST_INT_P (y))    return plus_constant (mode, x, INTVAL (y));  else if (CONSTANT_P (x))    std::swap (x, y);  if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1)))    return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y));  /* Note that if the operands of Y are specified in the opposite     order in the recursive calls below, infinite recursion will     occur.  */  if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1)))    return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1));  /* If both constant, encapsulate sum.	 Otherwise, just form sum.  A     constant will have been placed second.  */  if (CONSTANT_P (x) && CONSTANT_P (y))    {      if (GET_CODE (x) == CONST)	x = XEXP (x, 0);      if (GET_CODE (y) == CONST)	y = XEXP (y, 0);      return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y));    }  return gen_rtx_PLUS (mode, x, y);}

static voidsdbout_reg_parms (tree parms){  for (; parms; parms = TREE_CHAIN (parms))    if (DECL_NAME (parms))      {	const char *name = IDENTIFIER_POINTER (DECL_NAME (parms));	/* Report parms that live in registers during the function	   but were passed in memory.  */	if (REG_P (DECL_RTL (parms))	    && REGNO (DECL_RTL (parms)) < FIRST_PSEUDO_REGISTER	    && PARM_PASSED_IN_MEMORY (parms))	  {	    if (name == 0 || *name == 0)	      name = gen_fake_label ();	    PUT_SDB_DEF (name);	    PUT_SDB_INT_VAL (DBX_REGISTER_NUMBER (REGNO (DECL_RTL (parms))));	    PUT_SDB_SCL (C_REG);	    PUT_SDB_TYPE (plain_type (TREE_TYPE (parms)));	    PUT_SDB_ENDEF;	  }	/* Report parms that live in memory but not where they were passed.  */	else if (MEM_P (DECL_RTL (parms))		 && GET_CODE (XEXP (DECL_RTL (parms), 0)) == PLUS		 && CONST_INT_P (XEXP (XEXP (DECL_RTL (parms), 0), 1))		 && PARM_PASSED_IN_MEMORY (parms)		 && ! rtx_equal_p (DECL_RTL (parms), DECL_INCOMING_RTL (parms)))	  {#if 0 /* ??? It is not clear yet what should replace this.  */	    int offset = DECL_OFFSET (parms) / BITS_PER_UNIT;	    /* A parm declared char is really passed as an int,	       so it occupies the least significant bytes.	       On a big-endian machine those are not the low-numbered ones.  */	    if (BYTES_BIG_ENDIAN		&& offset != -1		&& TREE_TYPE (parms) != DECL_ARG_TYPE (parms))	      offset += (GET_MODE_SIZE (TYPE_MODE (DECL_ARG_TYPE (parms)))			 - GET_MODE_SIZE (GET_MODE (DECL_RTL (parms))));	    if (INTVAL (XEXP (XEXP (DECL_RTL (parms), 0), 1)) != offset) {...}#endif	      {		if (name == 0 || *name == 0)		  name = gen_fake_label ();		PUT_SDB_DEF (name);		PUT_SDB_INT_VAL (DEBUGGER_AUTO_OFFSET				 (XEXP (DECL_RTL (parms), 0)));		PUT_SDB_SCL (C_AUTO);		PUT_SDB_TYPE (plain_type (TREE_TYPE (parms)));		PUT_SDB_ENDEF;	      }	  }      }

/* Return TRUE if X is either an arithmetic shift left, or   is a multiplication by a power of two.  */boolarm_rtx_shift_left_p (rtx x){  enum rtx_code code = GET_CODE (x);  if (code == MULT && CONST_INT_P (XEXP (x, 1))      && exact_log2 (INTVAL (XEXP (x, 1))) > 0)    return true;  if (code == ASHIFT)    return true;  return false;}

voiddw2_assemble_integer (int size, rtx x){  const char *op = integer_asm_op (size, FALSE);  if (op)    {      fputs (op, asm_out_file);      if (CONST_INT_P (x))	fprint_whex (asm_out_file, (unsigned HOST_WIDE_INT) INTVAL (x));      else	output_addr_const (asm_out_file, x);    }  else    assemble_integer (x, size, BITS_PER_UNIT, 1);}

/* Find offset equivalence note for reg WHAT in INSN and return the   found elmination offset.  If the note is not found, return NULL.   Remove the found note.  */static rtxremove_reg_equal_offset_note (rtx_insn *insn, rtx what){  rtx link, *link_loc;  for (link_loc = &REG_NOTES (insn);       (link = *link_loc) != NULL_RTX;       link_loc = &XEXP (link, 1))    if (REG_NOTE_KIND (link) == REG_EQUAL	&& GET_CODE (XEXP (link, 0)) == PLUS	&& XEXP (XEXP (link, 0), 0) == what	&& CONST_INT_P (XEXP (XEXP (link, 0), 1)))      {	*link_loc = XEXP (link, 1);	return XEXP (XEXP (link, 0), 1);      }  return NULL_RTX;}

static voidmoxie_print_operand_address (FILE *file, machine_mode, rtx x){  switch (GET_CODE (x))    {    case REG:      fprintf (file, "(%s)", reg_names[REGNO (x)]);      break;          case PLUS:      switch (GET_CODE (XEXP (x, 1)))	{	case CONST_INT:	  fprintf (file, "%ld(%s)", 		   INTVAL(XEXP (x, 1)), reg_names[REGNO (XEXP (x, 0))]);	  break;	case SYMBOL_REF:	  output_addr_const (file, XEXP (x, 1));	  fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);	  break;	case CONST:	  {	    rtx plus = XEXP (XEXP (x, 1), 0);	    if (GET_CODE (XEXP (plus, 0)) == SYMBOL_REF 		&& CONST_INT_P (XEXP (plus, 1)))	      {		output_addr_const(file, XEXP (plus, 0));		fprintf (file,"+%ld(%s)", INTVAL (XEXP (plus, 1)),			 reg_names[REGNO (XEXP (x, 0))]);	      }	    else	      abort();	  }	  break;	default:	  abort();	}      break;    default:      output_addr_const (file, x);      break;    }}

static inline intpic_32bit_operand_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)#line 339 "../.././gcc/config/i386/predicates.md"{  if (!flag_pic)    return 0;  /* Rule out relocations that translate into 64bit constants.  */  if (TARGET_64BIT && GET_CODE (op) == CONST)    {      op = XEXP (op, 0);      if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))	op = XEXP (op, 0);      if (GET_CODE (op) == UNSPEC	  && (XINT (op, 1) == UNSPEC_GOTOFF	      || XINT (op, 1) == UNSPEC_GOT))	return 0;    }  return symbolic_operand (op, mode);}

static rtxpropagate_rtx (rtx x, machine_mode mode, rtx old_rtx, rtx new_rtx,	       bool speed){  rtx tem;  bool collapsed;  int flags;  if (REG_P (new_rtx) && REGNO (new_rtx) < FIRST_PSEUDO_REGISTER)    return NULL_RTX;  flags = 0;  if (REG_P (new_rtx)      || CONSTANT_P (new_rtx)      || (GET_CODE (new_rtx) == SUBREG	  && REG_P (SUBREG_REG (new_rtx))	  && (GET_MODE_SIZE (mode)	      <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (new_rtx))))))    flags |= PR_CAN_APPEAR;  if (!varying_mem_p (new_rtx))    flags |= PR_HANDLE_MEM;  if (speed)    flags |= PR_OPTIMIZE_FOR_SPEED;  tem = x;  collapsed = propagate_rtx_1 (&tem, old_rtx, copy_rtx (new_rtx), flags);  if (tem == x || !collapsed)    return NULL_RTX;  /* gen_lowpart_common will not be able to process VOIDmode entities other     than CONST_INTs.  */  if (GET_MODE (tem) == VOIDmode && !CONST_INT_P (tem))    return NULL_RTX;  if (GET_MODE (tem) == VOIDmode)    tem = rtl_hooks.gen_lowpart_no_emit (mode, tem);  else    gcc_assert (GET_MODE (tem) == mode);  return tem;}

static inline intsymbolic_operand_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)#line 369 "../.././gcc/config/i386/predicates.md"{  switch (GET_CODE (op))    {    case SYMBOL_REF:    case LABEL_REF:      return 1;    case CONST:      op = XEXP (op, 0);      if (GET_CODE (op) == SYMBOL_REF	  || GET_CODE (op) == LABEL_REF	  || (GET_CODE (op) == UNSPEC	      && (XINT (op, 1) == UNSPEC_GOT		  || XINT (op, 1) == UNSPEC_GOTOFF		  || XINT (op, 1) == UNSPEC_GOTPCREL)))	return 1;      if (GET_CODE (op) != PLUS	  || !CONST_INT_P (XEXP (op, 1)))	return 0;      op = XEXP (op, 0);      if (GET_CODE (op) == SYMBOL_REF	  || GET_CODE (op) == LABEL_REF)	return 1;      /* Only @GOTOFF gets offsets.  */      if (GET_CODE (op) != UNSPEC	  || XINT (op, 1) != UNSPEC_GOTOFF)	return 0;      op = XVECEXP (op, 0, 0);      if (GET_CODE (op) == SYMBOL_REF	  || GET_CODE (op) == LABEL_REF)	return 1;      return 0;    default:      gcc_unreachable ();    }}

static boolmoxie_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED,			    rtx x, bool strict_p,			    addr_space_t as){  gcc_assert (ADDR_SPACE_GENERIC_P (as));  if (GET_CODE(x) == PLUS      && REG_P (XEXP (x, 0))      && moxie_reg_ok_for_base_p (XEXP (x, 0), strict_p)      && CONST_INT_P (XEXP (x, 1))      && IN_RANGE (INTVAL (XEXP (x, 1)), -32768, 32767))    return true;  if (REG_P (x) && moxie_reg_ok_for_base_p (x, strict_p))    return true;  if (GET_CODE (x) == SYMBOL_REF      || GET_CODE (x) == LABEL_REF      || GET_CODE (x) == CONST)    return true;  return false;}

static voidcanonicalize_address (rtx x){  for (;;)    switch (GET_CODE (x))      {      case ASHIFT:        if (CONST_INT_P (XEXP (x, 1))            && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (GET_MODE (x))            && INTVAL (XEXP (x, 1)) >= 0)	  {	    HOST_WIDE_INT shift = INTVAL (XEXP (x, 1));	    PUT_CODE (x, MULT);	    XEXP (x, 1) = gen_int_mode (HOST_WIDE_INT_1 << shift,					GET_MODE (x));	  }	x = XEXP (x, 0);        break;      case PLUS:        if (GET_CODE (XEXP (x, 0)) == PLUS	    || GET_CODE (XEXP (x, 0)) == ASHIFT	    || GET_CODE (XEXP (x, 0)) == CONST)	  canonicalize_address (XEXP (x, 0));	x = XEXP (x, 1);        break;      case CONST:	x = XEXP (x, 0);        break;      default:        return;      }}

voidubsan_expand_si_overflow_addsub_check (tree_code code, gimple stmt){  rtx res, op0, op1;  tree lhs, fn, arg0, arg1;  rtx_code_label *done_label, *do_error;  rtx target = NULL_RTX;  lhs = gimple_call_lhs (stmt);  arg0 = gimple_call_arg (stmt, 0);  arg1 = gimple_call_arg (stmt, 1);  done_label = gen_label_rtx ();  do_error = gen_label_rtx ();  do_pending_stack_adjust ();  op0 = expand_normal (arg0);  op1 = expand_normal (arg1);  machine_mode mode = TYPE_MODE (TREE_TYPE (arg0));  if (lhs)    target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);  enum insn_code icode    = optab_handler (code == PLUS_EXPR ? addv4_optab : subv4_optab, mode);  if (icode != CODE_FOR_nothing)    {      struct expand_operand ops[4];      rtx_insn *last = get_last_insn ();      res = gen_reg_rtx (mode);      create_output_operand (&ops[0], res, mode);      create_input_operand (&ops[1], op0, mode);      create_input_operand (&ops[2], op1, mode);      create_fixed_operand (&ops[3], do_error);      if (maybe_expand_insn (icode, 4, ops))	{	  last = get_last_insn ();	  if (profile_status_for_fn (cfun) != PROFILE_ABSENT	      && JUMP_P (last)	      && any_condjump_p (last)	      && !find_reg_note (last, REG_BR_PROB, 0))	    add_int_reg_note (last, REG_BR_PROB, PROB_VERY_UNLIKELY);	  emit_jump (done_label);        }      else	{	  delete_insns_since (last);	  icode = CODE_FOR_nothing;	}    }  if (icode == CODE_FOR_nothing)    {      rtx_code_label *sub_check = gen_label_rtx ();      int pos_neg = 3;      /* Compute the operation.  On RTL level, the addition is always	 unsigned.  */      res = expand_binop (mode, code == PLUS_EXPR ? add_optab : sub_optab,			  op0, op1, NULL_RTX, false, OPTAB_LIB_WIDEN);      /* If we can prove one of the arguments (for MINUS_EXPR only	 the second operand, as subtraction is not commutative) is always	 non-negative or always negative, we can do just one comparison	 and conditional jump instead of 2 at runtime, 3 present in the	 emitted code.  If one of the arguments is CONST_INT, all we	 need is to make sure it is op1, then the first	 emit_cmp_and_jump_insns will be just folded.  Otherwise try	 to use range info if available.  */      if (code == PLUS_EXPR && CONST_INT_P (op0))	{	  rtx tem = op0;	  op0 = op1;	  op1 = tem;	}      else if (CONST_INT_P (op1))	;      else if (code == PLUS_EXPR && TREE_CODE (arg0) == SSA_NAME)	{	  wide_int arg0_min, arg0_max;	  if (get_range_info (arg0, &arg0_min, &arg0_max) == VR_RANGE)	    {	      if (!wi::neg_p (arg0_min, TYPE_SIGN (TREE_TYPE (arg0))))		pos_neg = 1;	      else if (wi::neg_p (arg0_max, TYPE_SIGN (TREE_TYPE (arg0))))		pos_neg = 2;	    }	  if (pos_neg != 3)	    {	      rtx tem = op0;	      op0 = op1;	      op1 = tem;	    }	}      if (pos_neg == 3 && !CONST_INT_P (op1) && TREE_CODE (arg1) == SSA_NAME)	{	  wide_int arg1_min, arg1_max;	  if (get_range_info (arg1, &arg1_min, &arg1_max) == VR_RANGE)	    {	      if (!wi::neg_p (arg1_min, TYPE_SIGN (TREE_TYPE (arg1))))		pos_neg = 1;//.........这里部分代码省略.........

intnds32_address_cost_impl (rtx address,			 enum machine_mode mode ATTRIBUTE_UNUSED,			 addr_space_t as ATTRIBUTE_UNUSED,			 bool speed){  rtx plus0, plus1;  enum rtx_code code;  code = GET_CODE (address);  /* According to 'speed', goto suitable cost model section.  */  if (speed)    goto performance_cost;  else    goto size_cost;performance_cost:  /* This is section for performance cost model.  */  /* FALLTHRU, currently we use same cost model as size_cost.  */size_cost:  /* This is section for size cost model.  */  switch (code)    {    case POST_MODIFY:    case POST_INC:    case POST_DEC:      /* We encourage that rtx contains         POST_MODIFY/POST_INC/POST_DEC behavior.  */      return 0;    case SYMBOL_REF:      /* We can have gp-relative load/store for symbol_ref.         Have it 4-byte cost.  */      return COSTS_N_INSNS (1);    case CONST:      /* It is supposed to be the pattern (const (plus symbol_ref const_int)).         Have it 4-byte cost.  */      return COSTS_N_INSNS (1);    case REG:      /* Simply return 4-byte costs.  */      return COSTS_N_INSNS (1);    case PLUS:      /* We do not need to check if the address is a legitimate address,         because this hook is never called with an invalid address.         But we better check the range of         const_int value for cost, if it exists.  */      plus0 = XEXP (address, 0);      plus1 = XEXP (address, 1);      if (REG_P (plus0) && CONST_INT_P (plus1))        {	  /* If it is possible to be lwi333/swi333 form,	     make it 2-byte cost.  */	  if (satisfies_constraint_Iu05 (plus1))	    return (COSTS_N_INSNS (1) - 2);	  else	    return COSTS_N_INSNS (1);	}      /* For other 'plus' situation, make it cost 4-byte.  */      return COSTS_N_INSNS (1);    default:      break;    }  return COSTS_N_INSNS (4);}

static rtxaarch64_simd_expand_args (rtx target, int icode, int have_retval,			  tree exp, builtin_simd_arg *args){  rtx pat;  tree arg[SIMD_MAX_BUILTIN_ARGS];  rtx op[SIMD_MAX_BUILTIN_ARGS];  machine_mode tmode = insn_data[icode].operand[0].mode;  machine_mode mode[SIMD_MAX_BUILTIN_ARGS];  int argc = 0;  if (have_retval      && (!target	  || GET_MODE (target) != tmode	  || !(*insn_data[icode].operand[0].predicate) (target, tmode)))    target = gen_reg_rtx (tmode);  for (;;)    {      builtin_simd_arg thisarg = args[argc];      if (thisarg == SIMD_ARG_STOP)	break;      else	{	  arg[argc] = CALL_EXPR_ARG (exp, argc);	  op[argc] = expand_normal (arg[argc]);	  mode[argc] = insn_data[icode].operand[argc + have_retval].mode;	  switch (thisarg)	    {	    case SIMD_ARG_COPY_TO_REG:	      if (POINTER_TYPE_P (TREE_TYPE (arg[argc])))		op[argc] = convert_memory_address (Pmode, op[argc]);	      /*gcc_assert (GET_MODE (op[argc]) == mode[argc]); */	      if (!(*insn_data[icode].operand[argc + have_retval].predicate)		  (op[argc], mode[argc]))		op[argc] = copy_to_mode_reg (mode[argc], op[argc]);	      break;	    case SIMD_ARG_LANE_INDEX:	      /* Must be a previous operand into which this is an index.  */	      gcc_assert (argc > 0);	      if (CONST_INT_P (op[argc]))		{		  enum machine_mode vmode = mode[argc - 1];		  aarch64_simd_lane_bounds (op[argc],					    0, GET_MODE_NUNITS (vmode));		  /* Keep to GCC-vector-extension lane indices in the RTL.  */		  op[argc] = GEN_INT (ENDIAN_LANE_N (vmode, INTVAL (op[argc])));		}	      /* Fall through - if the lane index isn't a constant then		 the next case will error.  */	    case SIMD_ARG_CONSTANT:	      if (!(*insn_data[icode].operand[argc + have_retval].predicate)		  (op[argc], mode[argc]))	      {		error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "		       "expected %<const int%>", argc + 1);		return const0_rtx;	      }	      break;	    case SIMD_ARG_STOP:	      gcc_unreachable ();	    }	  argc++;	}    }  if (have_retval)    switch (argc)      {      case 1:	pat = GEN_FCN (icode) (target, op[0]);	break;      case 2:	pat = GEN_FCN (icode) (target, op[0], op[1]);	break;      case 3:	pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);	break;      case 4:	pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);	break;      case 5:	pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]);	break;      default:	gcc_unreachable ();      }  else    switch (argc)      {//.........这里部分代码省略.........

static boolfind_call_stack_args (rtx_call_insn *call_insn, bool do_mark, bool fast,		      bitmap arg_stores){  rtx p;  rtx_insn *insn, *prev_insn;  bool ret;  HOST_WIDE_INT min_sp_off, max_sp_off;  bitmap sp_bytes;  gcc_assert (CALL_P (call_insn));  if (!ACCUMULATE_OUTGOING_ARGS)    return true;  if (!do_mark)    {      gcc_assert (arg_stores);      bitmap_clear (arg_stores);    }  min_sp_off = INTTYPE_MAXIMUM (HOST_WIDE_INT);  max_sp_off = 0;  /* First determine the minimum and maximum offset from sp for     stored arguments.  */  for (p = CALL_INSN_FUNCTION_USAGE (call_insn); p; p = XEXP (p, 1))    if (GET_CODE (XEXP (p, 0)) == USE	&& MEM_P (XEXP (XEXP (p, 0), 0)))      {	rtx mem = XEXP (XEXP (p, 0), 0), addr;	HOST_WIDE_INT off = 0, size;	if (!MEM_SIZE_KNOWN_P (mem))	  return false;	size = MEM_SIZE (mem);	addr = XEXP (mem, 0);	if (GET_CODE (addr) == PLUS	    && REG_P (XEXP (addr, 0))	    && CONST_INT_P (XEXP (addr, 1)))	  {	    off = INTVAL (XEXP (addr, 1));	    addr = XEXP (addr, 0);	  }	if (addr != stack_pointer_rtx)	  {	    if (!REG_P (addr))	      return false;	    /* If not fast, use chains to see if addr wasn't set to	       sp + offset.  */	    if (!fast)	      {		df_ref use;		struct df_link *defs;		rtx set;		FOR_EACH_INSN_USE (use, call_insn)		  if (rtx_equal_p (addr, DF_REF_REG (use)))		    break;		if (use == NULL)		  return false;		for (defs = DF_REF_CHAIN (use); defs; defs = defs->next)		  if (! DF_REF_IS_ARTIFICIAL (defs->ref))		    break;		if (defs == NULL)		  return false;		set = single_set (DF_REF_INSN (defs->ref));		if (!set)		  return false;		if (GET_CODE (SET_SRC (set)) != PLUS		    || XEXP (SET_SRC (set), 0) != stack_pointer_rtx		    || !CONST_INT_P (XEXP (SET_SRC (set), 1)))		  return false;		off += INTVAL (XEXP (SET_SRC (set), 1));	      }	    else	      return false;