自学教程：C++ CSR_READ_4函数代码示例

static voidpnphy_status(struct mii_softc *sc){	struct mii_data *mii = sc->mii_pdata;	int reg;	struct dc_softc		*dc_sc;	dc_sc = mii->mii_ifp->if_softc;	mii->mii_media_status = IFM_AVALID;	mii->mii_media_active = IFM_ETHER;	reg = CSR_READ_4(dc_sc, DC_ISR);	if (!(reg & DC_ISR_LINKFAIL))		mii->mii_media_status |= IFM_ACTIVE;	if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)		mii->mii_media_active |= IFM_10_T;	else		mii->mii_media_active |= IFM_100_TX;	if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)		mii->mii_media_active |= IFM_FDX;	else		mii->mii_media_active |= IFM_HDX;}

static voidbfe_core_reset( struct bfe_softc * sc ){	u_int32_t val;	/* Disable the core */	bfe_core_disable(sc);	/* and bring it back up */	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));	CSR_READ_4(sc, BFE_SBTMSLOW);	DELAY(10);	/* Chip bug, clear SERR, IB and TO if they are set. */	if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)		CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);	val = CSR_READ_4(sc, BFE_SBIMSTATE);	if (val & (BFE_IBE | BFE_TO))		CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));	/* Clear reset and allow it to move through the core */	CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));	CSR_READ_4(sc, BFE_SBTMSLOW);	DELAY(10);	/* Leave the clock set */	CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);	CSR_READ_4(sc, BFE_SBTMSLOW);	DELAY(10);}

/* Set a specific pin's in/out state. */static intaml8726_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags){	struct aml8726_gpio_softc *sc = device_get_softc(dev);	uint32_t mask = 1U << pin;	if (pin >= sc->npins)		return (EINVAL);	AML_GPIO_LOCK(sc);	if ((flags & GPIO_PIN_OUTPUT) != 0) {		/* Output.  Turn on driver.  */		CSR_WRITE_4(sc, AML_GPIO_OE_N_REG,		    (CSR_READ_4(sc, AML_GPIO_OE_N_REG) & ~mask));	} else {		/* Input.  Turn off driver. */		CSR_WRITE_4(sc, AML_GPIO_OE_N_REG,		    (CSR_READ_4(sc, AML_GPIO_OE_N_REG) | mask));	}			AML_GPIO_UNLOCK(sc);	return (0);}

static intkr_miibus_writereg(device_t dev, int phy, int reg, int data){	struct kr_softc * sc = device_get_softc(dev);	int i;	i = KR_MII_TIMEOUT;	while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)		i--;	if (i == 0)		device_printf(dev, "phy mii is busy %d:%d/n", phy, reg);	CSR_WRITE_4(sc, KR_MIIMADDR, (phy << 8) | reg);	i = KR_MII_TIMEOUT;	while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)		i--;	if (i == 0)		device_printf(dev, "phy mii is busy %d:%d/n", phy, reg);	CSR_WRITE_4(sc, KR_MIIMWTD, data);	i = KR_MII_TIMEOUT;	while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)		i--;	if (i == 0)		device_printf(dev, "phy mii is busy %d:%d/n", phy, reg);	return (0);}

static voidpcn_getfactaddr(pcn_t *pcnp){	uint32_t addr[2];	addr[0] = CSR_READ_4(pcnp, PCN_IO32_APROM00);	addr[1] = CSR_READ_4(pcnp, PCN_IO32_APROM01);	bcopy(&addr[0], &pcnp->pcn_addr[0], sizeof (pcnp->pcn_addr));}

static voiddcphy_status(struct mii_softc *sc){	struct mii_data *mii = sc->mii_pdata;	int reg, anlpar, tstat = 0;	struct dc_softc		*dc_sc;	dc_sc = mii->mii_ifp->if_softc;	mii->mii_media_status = IFM_AVALID;	mii->mii_media_active = IFM_ETHER;	if ((mii->mii_ifp->if_flags & IFF_UP) == 0)		return;	reg = CSR_READ_4(dc_sc, DC_10BTSTAT);	if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))		mii->mii_media_status |= IFM_ACTIVE;	if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {		/* Erg, still trying, I guess... */		tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);		if ((tstat & DC_TSTAT_ANEGSTAT) != DC_ASTAT_AUTONEGCMP) {			if ((DC_IS_MACRONIX(dc_sc) || DC_IS_PNICII(dc_sc)) &&			    (tstat & DC_TSTAT_ANEGSTAT) == DC_ASTAT_DISABLE)				goto skip;			mii->mii_media_active |= IFM_NONE;			return;		}		if (tstat & DC_TSTAT_LP_CAN_NWAY) {			anlpar = tstat >> 16;			if (anlpar & ANLPAR_TX_FD &&			    sc->mii_capabilities & BMSR_100TXFDX)				mii->mii_media_active |= IFM_100_TX | IFM_FDX;			else if (anlpar & ANLPAR_T4 &&			    sc->mii_capabilities & BMSR_100T4)				mii->mii_media_active |= IFM_100_T4 | IFM_HDX;			else if (anlpar & ANLPAR_TX &&			    sc->mii_capabilities & BMSR_100TXHDX)				mii->mii_media_active |= IFM_100_TX | IFM_HDX;			else if (anlpar & ANLPAR_10_FD)				mii->mii_media_active |= IFM_10_T | IFM_FDX;			else if (anlpar & ANLPAR_10)				mii->mii_media_active |= IFM_10_T | IFM_HDX;			else				mii->mii_media_active |= IFM_NONE;			if (DC_IS_INTEL(dc_sc))				DC_CLRBIT(dc_sc, DC_10BTCTRL,				    DC_TCTL_AUTONEGENBL);			return;		}

/* special I/O functions */static __inline u_int32_t_bs_r(void *v, bus_space_handle_t ioh, bus_size_t off, u_int32_t be){	u_int32_t data;	CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);	CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);	data = CSR_READ_4(PCI_NP_RDATA);	if (CSR_READ_4(PCI_ISR) & ISR_PFE)		CSR_WRITE_4(PCI_ISR, ISR_PFE);	return data;}

static voiddump_regs(Environ *e, Self *s){	dprintf("/n");	dprintf("ethxpro: scb_rus/scb_cus: %#x/n", CSR_READ_1(s, CSR_SCB_RUSCUS));	dprintf("ethxpro: scb_statack: %#x/n", CSR_READ_1(s, CSR_SCB_STATACK));	dprintf("ethxpro: scb_command: %#x/n", CSR_READ_1(s, CSR_SCB_COMMAND));	dprintf("ethxpro: scb_intrcntl: %#x/n", CSR_READ_1(s, CSR_SCB_INTRCNTL));	dprintf("ethxpro: scb_general: %#x/n", CSR_READ_4(s, CSR_SCB_GENERAL));	dprintf("ethxpro: port: %#x/n", CSR_READ_4(s, CSR_PORT));	dprintf("ethxpro: flash control: %#x/n", CSR_READ_2(s, CSR_FLASHCONTROL));	dprintf("ethxpro: eeprom ctrl: %#x/n", CSR_READ_2(s, CSR_EEPROMCONTROL));	dprintf("ethxpro: mdi control: %#x/n", CSR_READ_4(s, CSR_MDICONTROL));}

static voidaml8726_rng_harvest(void *arg){	struct aml8726_rng_softc *sc = arg;	uint32_t rn[2];	rn[0] = CSR_READ_4(sc, AML_RNG_0_REG);	rn[1] = CSR_READ_4(sc, AML_RNG_1_REG);	random_harvest(rn, sizeof(rn), sizeof(rn) * NBBY / 2,	    RANDOM_PURE_AML8726);	callout_reset(&sc->co, sc->ticks, aml8726_rng_harvest, sc);}

static void bfe_clear_stats( struct bfe_softc * sc ){	u_long reg;	BFE_LOCK(sc);	CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);	for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)		CSR_READ_4(sc, reg);	for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)		CSR_READ_4(sc, reg);	BFE_UNLOCK(sc);}

static intaml8726_usb_phy_detach(device_t dev){	struct aml8726_usb_phy_softc *sc = device_get_softc(dev);	uint32_t i;	uint32_t value;	/*	 * Disable by issuing a power on reset.	 */	value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG);	value |= (AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR);	CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);	CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);	/* Turn off power */	i = sc->npwr_en;	while (i-- != 0) {		(void)GPIO_PIN_SET(sc->pwr_en[i].dev, sc->pwr_en[i].pin,		    PIN_OFF_FLAG(sc->pwr_en[i].pol));	}	free (sc->pwr_en, M_DEVBUF);	sc->pwr_en = NULL;	bus_release_resources(dev, aml8726_usb_phy_spec, sc->res);	return (0);}

static intbfe_wait_bit( struct bfe_softc * sc, u_int32_t reg, u_int32_t bit,               u_long timeout, const int clear ){	u_long i;    int use_sleep = 0;    /* [email
C++ CSR_WRITE_2函数代码示例
C++ CSPUTILSLOG函数代码示例