这篇教程C++ CY_SET_XTND_REG8函数代码示例写得很实用，希望能帮到您。
本文整理汇总了C++中CY_SET_XTND_REG8函数的典型用法代码示例。如果您正苦于以下问题：C++ CY_SET_XTND_REG8函数的具体用法？C++ CY_SET_XTND_REG8怎么用？C++ CY_SET_XTND_REG8使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。 在下文中一共展示了CY_SET_XTND_REG8函数的30个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的C++代码示例。 示例1: cyfitter_cfg/******************************************************************************** Function Name: cyfitter_cfg********************************************************************************* Summary:* This function is called by the start-up code for the selected device. It* performs all of the necessary device configuration based on the design* settings. This includes settings from the Design Wide Resources (DWR) such* as Clocks and Pins as well as any component configuration that is necessary.** Parameters: * void** Return:* void********************************************************************************/CY_CFG_SECTIONvoid cyfitter_cfg(void){ /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (uint32)(ms->size)); } /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xFF000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x000FEEFFu); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x000000C0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00D80000u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000011u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00006D8Eu); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:e2forlife，项目名称:PSoC-W5100-Example1，代码行数:76，
示例2: cyfitter_cfg/******************************************************************************** Function Name: cyfitter_cfg********************************************************************************* Summary:* This function is called by the start-up code for the selected device. It* performs all of the necessary device configuration based on the design* settings. This includes settings from the Design Wide Resources (DWR) such* as Clocks and Pins as well as any component configuration that is necessary.** Parameters: * void** Return:* void********************************************************************************/CY_CFG_SECTIONvoid cyfitter_cfg(void){ /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00036C00u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:iwabuchiken，项目名称:WS_E2，代码行数:75，
示例3: AnalogSetDefaultstatic void AnalogSetDefault(void){ CY_SET_XTND_REG16((void CYFAR *)CYREG_PM_ACT_CFG10, 0x0310u); CY_SET_XTND_REG8((void CYFAR *)CYREG_DAC0_CR0, 0x1Eu); CY_SET_XTND_REG8((void CYFAR *)CYREG_DAC1_CR0, 0x1Eu); CY_SET_XTND_REG8((void CYFAR *)CYREG_DAC2_CR0, 0x1Eu); CY_SET_XTND_REG8((void CYFAR *)CYREG_DAC3_CR0, 0x1Eu); CY_SET_XTND_REG8((void CYFAR *)CYREG_SAR0_CSR0, 0xC0u); CY_SET_XTND_REG8((void CYFAR *)CYREG_SAR0_CSR3, 0x0Cu); CY_SET_XTND_REG8((void CYFAR *)CYREG_SAR1_CSR0, 0xC0u); CY_SET_XTND_REG8((void CYFAR *)CYREG_SAR1_CSR3, 0x0Cu); CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);}
开发者ID:kLabUM，项目名称:IoT，代码行数:13，
示例4: SetAnalogRoutingPumps/******************************************************************************** Function Name: SetAnalogRoutingPumps********************************************************************************** Summary:* Enables or disables the analog pumps feeding analog routing switches.* Intended to be called at startup, based on the Vdda system configuration;* may be called during operation when the user informs us that the Vdda voltage* crossed the pump threshold.** Parameters:* enabled - 1 to enable the pumps, 0 to disable the pumps** Return:* void********************************************************************************/void SetAnalogRoutingPumps(uint8 enabled){ uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0); if (enabled != 0u) { regValue |= 0x22u; } else { regValue &= (uint8)~0x22u; } CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);}
开发者ID:greglandry，项目名称:PSoC，代码行数:30，
示例5: cfg_write_bytes32static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]){ /* For 32-bit little-endian architectures */ uint32 i, j = 0u; for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) { uint32 baseAddr = addr_table[i]; uint8 count = (uint8)baseAddr; baseAddr &= 0xFFFFFF00u; while (count != 0u) { CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value); j++; count--; } }}
开发者ID:gsgill112，项目名称:PSoC4_CY8CKIT-049_Tutorial，代码行数:17，
示例6: cyfitter_cfg/******************************************************************************** Function Name: cyfitter_cfg********************************************************************************* Summary:* This function is called by the start-up code for the selected device. It* performs all of the necessary device configuration based on the design* settings. This includes settings from the Design Wide Resources (DWR) such* as Clocks and Pins as well as any component configuration that is necessary.** Parameters: * void** Return:* void********************************************************************************/CY_CFG_SECTIONvoid cyfitter_cfg(void){ /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F4003u, /* Base address: 0x400F4000 Count: 3 */ 0x400F4105u, /* Base address: 0x400F4100 Count: 5 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x00u, 0x08u}, {0x04u, 0x02u}, {0xC0u, 0x30u}, {0x48u, 0x04u}, {0x4Cu, 0x01u}, {0x90u, 0x02u}, {0xA0u, 0x04u}, {0xD2u, 0x30u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00000189u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00000006u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000E00F0u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults *///.........这里部分代码省略.........
开发者ID:rcxking，项目名称:wpi_sample_return_challenge_2015，代码行数:101，
示例7: cyfitter_cfg//.........这里部分代码省略......... CYPACKED typedef struct { void CYFAR *dest; const void CYCODE *src; uint16 size; } CYPACKED_ATTR cfg_memcpy_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 128u}, {(void CYFAR *)(CYDEV_UDB_P0_ROUTE_BASE), 768u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; /* UDB_0_1_1_CONFIG Address: CYDEV_UDB_P0_U1_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_0_1_1_CONFIG_VAL[] = { 0x04u, 0x40u, 0x00u, 0x00u, 0x07u, 0x40u, 0x38u, 0x00u, 0x60u, 0x00u, 0x00u, 0x40u, 0x56u, 0x40u, 0x09u, 0x00u, 0x01u, 0x40u, 0x00u, 0x00u, 0x00u, 0x03u, 0x04u, 0x3Cu, 0x0Au, 0x15u, 0x10u, 0x6Au, 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0x79u, 0x00u, 0x06u, 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0x10u, 0x00u, 0x60u, 0x00u, 0x02u, 0x00u, 0x0Du, 0x7Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x0Fu, 0x02u, 0x00u, 0x00u, 0xA0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x35u, 0x01u, 0x40u, 0x00u, 0x02u, 0x0Eu, 0xFDu, 0xCBu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ {(void CYFAR *)(CYDEV_UDB_P0_U1_BASE), BS_UDB_0_1_1_CONFIG_VAL, 128u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (uint32)(ms->size)); } /* Copy device configuration data into registers */ for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) { const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; void * CYDATA destPtr = mc->dest; const void CYCODE * CYDATA srcPtr = mc->src; uint16 CYDATA numBytes = mc->size; CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00EE0000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0300EE03u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000030u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00024000u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00040000u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000041u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00186D86u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000002u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000002u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x20000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x30030000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:JordenLuke，项目名称:Desktop_Tool_Emulator.cydsn，代码行数:101，
示例8: cyfitter_cfg//.........这里部分代码省略......... {0xE2u, 0x08u}, {0xE4u, 0x08u}, {0xEAu, 0x04u}, {0x10u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000030u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x000000E0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0002EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x0000000Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL7), 0x000000EEu); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x02000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x000C0000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x00A20000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x02000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG12), 0x00000200u); /* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000EEE1Eu); /* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x00000001u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
开发者ID:tslator，项目名称:DualBoard-043，代码行数:67，
示例9: cyfitter_cfg//.........这里部分代码省略......... {0xCAu, 0x60u}, {0xCCu, 0x20u}, {0xCEu, 0xE8u}, {0xD0u, 0x21u}, {0xDEu, 0x82u}, {0xE4u, 0x04u}, {0x38u, 0x01u}, {0x3Cu, 0x01u}, {0x80u, 0x01u}, {0xCEu, 0xC0u}, {0xE2u, 0x80u}, {0x5Du, 0x08u}, {0xD6u, 0x01u}, {0x5Au, 0x01u}, {0x5Cu, 0x08u}, {0x80u, 0x08u}, {0x8Au, 0x01u}, {0x8Du, 0x08u}, {0x9Du, 0x08u}, {0xD6u, 0x03u}, {0xE0u, 0x02u}, {0xE4u, 0x01u}, {0x01u, 0x01u}, {0x10u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* PWR_BG_CONFIG Starting address: CYDEV_PWR_BG_CONFIG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PWR_BG_CONFIG), 0x00040000u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xEE000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x03000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x33000000u); /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00D80000u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_DR), 0x0000007Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00040000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x0000003Eu); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_DR), 0x000000C0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00240000u); /* IOPINS0_4 Starting address: CYDEV_GPIO_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_DR), 0x00000001u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_PC2), 0x00000001u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x10000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x40000000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:Magnetovore，项目名称:PSoC-LED-and-Slider，代码行数:101，
示例10: cyfitter_cfg//.........这里部分代码省略......... 0x400F4107u, /* Base address: 0x400F4100 Count: 7 */ 0x400F4201u, /* Base address: 0x400F4200 Count: 1 */ 0x400F430Bu, /* Base address: 0x400F4300 Count: 11 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0xE2u, 0x02u}, {0xE2u, 0x01u}, {0xE6u, 0x20u}, {0xEEu, 0x02u}, {0x52u, 0x20u}, {0x56u, 0x80u}, {0x5Bu, 0x20u}, {0x5Fu, 0x80u}, {0x87u, 0x20u}, {0xD4u, 0xE0u}, {0xD6u, 0x20u}, {0xE2u, 0x40u}, {0x83u, 0x80u}, {0x8Au, 0x80u}, {0x9Eu, 0x80u}, {0x9Fu, 0x80u}, {0xAEu, 0x20u}, {0xE2u, 0x80u}, {0xEEu, 0x40u}, {0x86u, 0x04u}, {0x18u, 0x01u}, {0x1Bu, 0x08u}, {0x1Cu, 0x80u}, {0x1Eu, 0x04u}, {0x80u, 0x01u}, {0x88u, 0x40u}, {0x96u, 0x04u}, {0xA7u, 0x08u}, {0xAFu, 0x08u}, {0xC6u, 0x0Fu}, {0xE6u, 0x04u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00003333u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000009u); /* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL3 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00000000u); /* IOPINS0_3 Starting address: CYDEV_PRT3_PC */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000000u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00870000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT0_BASE), 0x0000000Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00000DB6u); /* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000001u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:f16falcona46，项目名称:PSoC，代码行数:101，
示例11: cyfitter_cfg//.........这里部分代码省略......... {0xAFu, 0x20u}, {0xB4u, 0x40u}, {0x0Fu, 0x04u}, {0x6Eu, 0x80u}, {0x73u, 0x08u}, {0x86u, 0x40u}, {0xC2u, 0x80u}, {0xDAu, 0x80u}, {0xDCu, 0x20u}, {0xE6u, 0x40u}, {0x23u, 0x08u}, {0x9Fu, 0x08u}, {0xAFu, 0x04u}, {0xC8u, 0x10u}, {0xE8u, 0x40u}, {0x01u, 0x08u}, {0xC0u, 0x08u}, {0xB5u, 0x08u}, {0xEAu, 0x02u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE99u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x0000FFFFu); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x80000000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x00020000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000005u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00200006u); /* IOPINS0_2 Starting address: CYDEV_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00000001u); /* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT3_BASE), 0x00000002u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000DB1u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC2), 0x00000002u); /* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT4_BASE), 0x0000000Du); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000D8Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x0000000Du); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:remixvit，项目名称:USB_NRF_Dongle，代码行数:101，
示例12: AnalogSetDefaultstatic void AnalogSetDefault(void){ uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u)); CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); CY_SET_XTND_REG8((void CYFAR *)CYREG_PRT2_AG, 0x10u); CY_SET_XTND_REG8((void CYFAR *)CYREG_DAC1_SW0, 0x02u); CY_SET_XTND_REG8((void CYFAR *)CYREG_DAC2_SW0, 0x10u); CY_SET_XTND_REG8((void CYFAR *)CYREG_DAC3_SW0, 0x10u); CY_SET_XTND_REG8((void CYFAR *)CYREG_CMP0_SW0, 0x41u); CY_SET_XTND_REG8((void CYFAR *)CYREG_CMP0_SW4, 0x10u); CY_SET_XTND_REG8((void CYFAR *)CYREG_CMP1_SW0, 0x40u); CY_SET_XTND_REG8((void CYFAR *)CYREG_CMP1_SW4, 0x10u); CY_SET_XTND_REG8((void CYFAR *)CYREG_CMP3_SW0, 0x40u); CY_SET_XTND_REG8((void CYFAR *)CYREG_CMP3_SW4, 0x02u); CY_SET_XTND_REG8((void CYFAR *)CYREG_BUS_SW0, 0x40u); CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);}
开发者ID:greglandry，项目名称:PSoC，代码行数:18，
示例13: cyfitter_cfgvoid cyfitter_cfg(void){#ifdef CYGlobalIntDisable /* Disable interrupts by default. Let user enable if/when they want. */ CYGlobalIntDisable#endif /* Enable/Disable Debug functionality based on settings from System DWR */ CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u)); { CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT0_DR), 32u}, {(void CYFAR *)(CYREG_PRT3_DR), 32u}, {(void CYFAR *)(CYREG_PRT12_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_LUT0_CR), 0x0003u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_LUT1_CR), 0x0103u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_LUT3_CR), 0x0303u); /* Enable digital routing */ CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u); CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ CYCONFIGCPY((void CYFAR *)(CYREG_PRT15_DR), (const void CYFAR *)(BS_IOPINS0_8_VAL), 10u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DR), (const void CYFAR *)(BS_IOPINS0_2_VAL), 10u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT5_DM0), (const void CYFAR *)(BS_IOPINS0_5_VAL), 8u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DR), (const void CYFAR *)(BS_IOPINS0_6_VAL), 10u); /* Switch Boost to the precision bandgap reference from its internal reference */ CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u)); /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u)); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Set Flash Cycles based on newly configured 12.00MHz Bus Clock. */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x41u : 0x40u)); CY_SET_XTND_REG8((void CYFAR *)(CYREG_PANTHER_WAITPIPE), 0x01u); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); /* Configure alternate active mode */ CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);}
开发者ID:greglandry，项目名称:PSoC，代码行数:78，
示例14: cyfitter_cfg//.........这里部分代码省略......... {0xC0u, 0x0Cu}, {0xE2u, 0x04u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00990067u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x000000EEu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL6), 0x00000800u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x00A00000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00500000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x00AA0000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0xA00A0000u); /* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000EEE1Eu); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT0_BASE), 0x00000023u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x001B1C40u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC2), 0x00000023u); /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000080u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00000249u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000080u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x0000003Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00180000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x0000003Fu); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x000000C0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x004B6D8Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_INTR_CFG), 0x0000F000u); /* IOPINS0_4 Starting address: CYDEV_GPIO_PRT4_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT4_BASE), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_PC), 0x001B6024u); /* IOPINS0_6 Starting address: CYDEV_GPIO_PRT6_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT6_BASE), 0x00000004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT6_PC), 0x000300C0u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:tslator，项目名称:DualBoard-043，代码行数:101，
示例15: cyfitter_cfg//.........这里部分代码省略......... {0xE0u, 0x01u}, {0xE2u, 0x04u}, {0xE4u, 0x0Eu}, {0x10u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000333u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x33000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x3000EE33u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00C80000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0xAA000000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0xC5000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0xC1090000u); /* TCPWM_CNT1 Starting address: CYDEV_TCPWM_CNT1_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT1_TR_CTRL0), 0x00060030u); /* TCPWM_CNT2 Starting address: CYDEV_TCPWM_CNT2_TR_CTRL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT2_TR_CTRL0), 0x00020080u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
开发者ID:CoroBot，项目名称:Spark_Firmware，代码行数:66，
示例16: cyfitter_cfg//.........这里部分代码省略......... {0xC0u, 0x40u}, {0xC2u, 0xA0u}, {0xC4u, 0x90u}, {0xCCu, 0xA0u}, {0xCEu, 0xC0u}, {0xD0u, 0x40u}, {0xD2u, 0x10u}, {0xD6u, 0xF0u}, {0xE2u, 0x40u}, {0x59u, 0x10u}, {0x63u, 0x08u}, {0x81u, 0x10u}, {0x8Fu, 0x04u}, {0xD4u, 0x80u}, {0xD8u, 0x40u}, {0xE6u, 0x20u}, {0x10u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x03990300u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00EE0000u); /* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL0), 0x00000000u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x20200000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0xA0A00000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00C36DB6u); /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000064u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00DB1DB6u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000020u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00C30000u); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x00000030u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00264240u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:mcisek，项目名称:balancing_robot，代码行数:101，
示例17: cyfitter_cfg//.........这里部分代码省略......... {(void CYFAR *)(CYDEV_UDB_P1_ROUTE_BASE), 256u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; /* UDB_0_0_0_CONFIG Address: CYDEV_UDB_P1_U1_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_0_0_0_CONFIG_VAL[] = { 0x00u, 0x60u, 0x33u, 0x00u, 0x03u, 0x00u, 0x00u, 0x04u, 0x4Fu, 0x18u, 0x30u, 0x00u, 0x01u, 0x1Cu, 0x00u, 0xE2u, 0x5Cu, 0x10u, 0x23u, 0x00u, 0x7Fu, 0xE7u, 0x00u, 0x18u, 0x73u, 0x08u, 0x0Cu, 0x00u, 0x08u, 0x00u, 0x00u, 0x63u, 0x00u, 0x40u, 0x00u, 0x00u, 0x04u, 0xFFu, 0x00u, 0x00u, 0x0Cu, 0x1Cu, 0x00u, 0xE1u, 0x02u, 0x24u, 0x00u, 0x00u, 0x40u, 0x1Fu, 0x2Cu, 0x60u, 0x0Fu, 0x00u, 0x1Cu, 0x80u, 0x00u, 0x80u, 0x28u, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x23u, 0x06u, 0x01u, 0x00u, 0x05u, 0x00u, 0xC0u, 0xE0u, 0x28u, 0xFFu, 0xFFu, 0xFFu, 0x62u, 0xA0u, 0xF0u, 0x41u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x13u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x02u, 0x00u, 0x10u, 0x30u, 0x10u, 0x00u, 0x10u, 0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ {(void CYFAR *)(CYDEV_UDB_P1_U1_BASE), BS_UDB_0_0_0_CONFIG_VAL, 128u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } /* Copy device configuration data into registers */ for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) { const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; void * CYDATA destPtr = mc->dest; const void CYCODE * CYDATA srcPtr = mc->src; uint16 CYDATA numBytes = mc->size; CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00300000u); /* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL0), 0x00000000u); /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_PC */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00000000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x20000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x04000000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x0000000Eu); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x0000000Eu); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000020u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00070003u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x000000C0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00480000u); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x000000C0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00480000u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:andrey-mcs，项目名称:start-finish-system，代码行数:101，
示例18: cyfitter_cfg//.........这里部分代码省略......... {0x2Eu, 0x40u}, {0x2Fu, 0x80u}, {0x31u, 0x0Au}, {0x32u, 0x40u}, {0x37u, 0x20u}, {0x38u, 0x09u}, {0x3Au, 0x10u}, {0x3Cu, 0x01u}, {0x3Fu, 0x84u}, {0x41u, 0x08u}, {0x42u, 0x80u}, {0x43u, 0x80u}, {0x44u, 0x40u}, {0x47u, 0x81u}, {0x49u, 0x01u}, {0x4Bu, 0x04u}, {0x50u, 0x04u}, {0x54u, 0x20u}, {0x55u, 0x40u}, {0x56u, 0x90u}, {0x57u, 0x40u}, {0x58u, 0x41u}, {0x59u, 0x25u}, {0x65u, 0x20u}, {0x67u, 0x04u}, {0x8Eu, 0x48u}, {0x8Fu, 0x20u}, {0xC0u, 0x99u}, {0xC2u, 0xDDu}, {0xC4u, 0x47u}, {0xCAu, 0x91u}, {0xCCu, 0x2Bu}, {0xCEu, 0xD7u}, {0xD0u, 0x1Bu}, {0xD6u, 0x0Fu}, {0xE2u, 0x40u}, {0x63u, 0x08u}, {0x8Fu, 0x04u}, {0xD8u, 0x40u}, {0x01u, 0x01u}, {0x10u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x30000000u); /* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL3 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00000000u); /* IOPINS0_3 Starting address: CYDEV_PRT3_PC */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x80000000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000080u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00C00000u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:JP7FKF，项目名称:PSoC，代码行数:101，
示例19: cyfitter_cfgvoid cyfitter_cfg(void){#ifdef CYGlobalIntDisable /* Disable interrupts by default. Let user enable if/when they want. */ CYGlobalIntDisable#endif /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x00u : 0x01u)); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Set Flash Cycles based on newly configured 24.00MHz Bus Clock. */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x80u : 0x81u)); /* Disable DMA channels so they can be configured for chip initialization */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_PHUB_CH0_BASIC_CFG), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_PHUB_CH1_BASIC_CFG), 0x00u); /* Enable analog pulldown switches */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_ANAIF_CFG_MISC_CR0), 0x01u); /* Enable/Disable Debug functionality based on settings from System DWR */ CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DBG_DBE, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DBG_DBE) | 0x01u)); { typedef struct { void CYFAR *address; uint16 size; } CYPACKED cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYREG_I2C_XCFG), 20u}, {(void CYFAR *)(CYREG_PRT0_DR), 16u}, {(void CYFAR *)(CYREG_PRT4_DR), 48u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT0_BASE), 7u); CYCONFIGCPY8((void CYFAR *)(CYDEV_PRTDSI_PRT1_BASE), (const void CYFAR *)(BS_IOPORT_1_VAL), 7u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT2_BASE), 7u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT3_BASE), 7u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT4_BASE), 7u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT5_BASE), 7u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT6_BASE), 7u); CYCONFIGCPY8((void CYFAR *)(CYDEV_PRTDSI_PRT12_BASE), (const void CYFAR *)(BS_IOPORT_7_VAL), 6u); CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT15_BASE), 7u); /* Enable digital routing */ CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u); CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ CYCONFIGCPY8((void CYFAR *)(CYREG_PRT12_DR), (const void CYFAR *)(BS_IOPINS0_7_VAL), 10u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT15_DR), (const void CYFAR *)(BS_IOPINS0_8_VAL), 10u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT1_DR), (const void CYFAR *)(BS_IOPINS0_1_VAL), 10u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DR), (const void CYFAR *)(BS_IOPINS0_2_VAL), 10u); CYCONFIGCPY((void CYFAR *)(CYREG_PRT3_DR), (const void CYFAR *)(BS_IOPINS0_3_VAL), 10u); /* Perform basic analog initialization to defaults */ AnalogSetDefault(); /* Configure alternate active mode */ CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 12u); CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_STBY_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_STBY_CFG0) & (uint8)~0x02u); /* Disable CPU */}
开发者ID:kLabUM，项目名称:IoT，代码行数:89，
示例20: cyfitter_cfg//.........这里部分代码省略......... {0x1Eu, 0x80u}, {0x46u, 0x82u}, {0x4Du, 0x04u}, {0x4Fu, 0x01u}, {0x56u, 0x02u}, {0x5Du, 0x04u}, {0x5Eu, 0x80u}, {0x5Fu, 0x01u}, {0x67u, 0x80u}, {0x87u, 0x40u}, {0x9Au, 0x80u}, {0x9Bu, 0x80u}, {0x9Eu, 0x02u}, {0xC0u, 0x80u}, {0xC4u, 0x80u}, {0xD0u, 0x90u}, {0xD6u, 0xD0u}, {0xD8u, 0x80u}, {0xE2u, 0x80u}, {0x53u, 0x04u}, {0x6Fu, 0x02u}, {0xD4u, 0x20u}, {0xDAu, 0x80u}, {0x87u, 0x02u}, {0x8Bu, 0x04u}, {0x97u, 0x08u}, {0xA7u, 0x02u}, {0xE2u, 0x10u}, {0x19u, 0x08u}, {0x89u, 0x08u}, {0xC6u, 0x08u}, {0xE2u, 0x01u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00993000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000001u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000028u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00031C00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x00000020u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:eshamidi，项目名称:PSoC2016，代码行数:101，
示例21: ClockSetupstatic void ClockSetup(void){ /* Configure Digital Clocks based on settings from Clock DWR */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0077u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x19u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x002Fu); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x19u); /* Configure ILO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x02u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_CR), 0x08u); /* Configure IMO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_12MHZ))); /* Configure Bus/Master Clock based on settings from Clock DWR */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0000u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x03u)));}
开发者ID:greglandry，项目名称:PSoC，代码行数:28，
示例22: cyfitter_cfg//.........这里部分代码省略......... {0x09u, 0x01u}, {0xC2u, 0x08u}, {0xB5u, 0x01u}, {0xEAu, 0x08u}, {0x10u, 0x0Au}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0A00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x00800000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x02000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000002u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x0000002Au); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x000319B6u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_INTCFG), 0x000000C0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x00000020u); /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00180DB6u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x00000080u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00D81D80u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC2), 0x00000003u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00C00D80u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000002u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000002u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:shrutidevasenapathy，项目名称:myAtoms，代码行数:101，
示例23: cyfitter_cfg//.........这里部分代码省略......... {0xD2u, 0x08u}, {0xD6u, 0x0Bu}, {0xE2u, 0x02u}, {0x6Cu, 0x20u}, {0x80u, 0x20u}, {0xDAu, 0x80u}, {0xE2u, 0x80u}, {0x07u, 0x80u}, {0x54u, 0x02u}, {0x87u, 0x80u}, {0x8Cu, 0x02u}, {0xC0u, 0x04u}, {0xD6u, 0x04u}, {0xE4u, 0x02u}, {0x01u, 0x01u}, {0x10u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xEE9900EEu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00003000u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x00C00000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x00000002u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT0_BASE), 0x00000023u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00DB1DA4u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC2), 0x00000020u); /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000090u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x009B6006u); /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x00000021u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x0003618Au); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x0000000Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00036C90u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC2), 0x00000001u); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:andrey-mcs，项目名称:start-finish-system，代码行数:101，
示例24: ClockSetupstatic void ClockSetup(void){ /* Configure ILO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x02u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_CR), 0x08u); /* Configure IMO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x03u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_3MHZ))); /* Configure PLL based on settings from Clock DWR */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0008u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1051u); /* Wait 250us for the PLL to lock */ CyDelayCycles(250u * 12u); /* Delay 250us based on 12MHz clock */ /* Configure Bus/Master Clock based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x03u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR1), 0x01u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);}
开发者ID:kLabUM，项目名称:IoT，代码行数:28，
示例25: cyfitter_cfg//.........这里部分代码省略......... } CYPACKED_ATTR cfg_memset_t; CYPACKED typedef struct { void CYFAR *dest; const void CYCODE *src; uint16 size; } CYPACKED_ATTR cfg_memcpy_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 512u}, {(void CYFAR *)(CYDEV_UDB_P1_U1_BASE), 384u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; /* UDB_0_0_1_CONFIG Address: CYDEV_UDB_P1_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_0_0_1_CONFIG_VAL[] = { 0x00u, 0x10u, 0xF3u, 0x00u, 0x1Cu, 0x08u, 0xE3u, 0x00u, 0xF3u, 0x18u, 0x0Cu, 0x00u, 0x0Fu, 0x04u, 0xF0u, 0x80u, 0x00u, 0x00u, 0x00u, 0x03u, 0xC3u, 0x3Cu, 0x00u, 0x42u, 0x82u, 0x7Fu, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x04u, 0x08u, 0x00u, 0x00u, 0x00u, 0x04u, 0x67u, 0x00u, 0x18u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x41u, 0x3Cu, 0x00u, 0x41u, 0x2Cu, 0x80u, 0x1Cu, 0x40u, 0x0Fu, 0x1Fu, 0xC0u, 0x20u, 0x00u, 0x08u, 0x22u, 0x20u, 0x00u, 0x00u, 0x00u, 0x40u, 0x35u, 0x06u, 0x02u, 0x00u, 0x04u, 0x00u, 0xE0u, 0x0Cu, 0x18u, 0xFFu, 0xFFu, 0xFFu, 0x62u, 0xA0u, 0xF0u, 0x41u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x13u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x02u, 0x00u, 0x10u, 0x30u, 0x10u, 0x00u, 0x10u, 0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ {(void CYFAR *)(CYDEV_UDB_P1_U0_BASE), BS_UDB_0_0_1_CONFIG_VAL, 128u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } /* Copy device configuration data into registers */ for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) { const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; void * CYDATA destPtr = mc->dest; const void CYCODE * CYDATA srcPtr = mc->src; uint16 CYDATA numBytes = mc->size; CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000030u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000002u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00000031u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000C36u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x00020000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00080000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000005u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000006u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:Rensselaer-Motorsport，项目名称:Deprecated，代码行数:101，
示例26: cyfitter_cfg//.........这里部分代码省略......... {0x88u, 0x20u}, {0x8Au, 0x81u}, {0x8Bu, 0x10u}, {0x8Du, 0x08u}, {0xB0u, 0x30u}, {0xB2u, 0x80u}, {0xB5u, 0x04u}, {0xB7u, 0x04u}, {0xC0u, 0x0Cu}, {0xC2u, 0x0Bu}, {0xE2u, 0x07u}, {0xE6u, 0x05u}, {0xEAu, 0x03u}, {0xEEu, 0x07u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x0000FFFFu); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x55550000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x24050000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x55550000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0x51050000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x000000FFu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00249249u); /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000044u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x0008ED89u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_INTCFG), 0x00001000u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000FFu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00249249u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000020u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00261D89u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x0000000Du); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000D8Eu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x0000000Du); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:VWarlock，项目名称:uknc_sd_fdd，代码行数:101，
示例27: cyfitter_cfg/******************************************************************************** Function Name: cyfitter_cfg********************************************************************************* Summary:* This function is called by the start-up code for the selected device. It* performs all of the necessary device configuration based on the design* settings. This includes settings from the Design Wide Resources (DWR) such* as Clocks and Pins as well as any component configuration that is necessary.** Parameters: * void** Return:* void********************************************************************************/CY_CFG_SECTIONvoid cyfitter_cfg(void){ /* Disable interrupts by default. Let user enable if/when they want. */ CyGlobalIntDisable; CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u); { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x400F4202u, /* Base address: 0x400F4200 Count: 2 */ 0x400F4303u, /* Base address: 0x400F4300 Count: 3 */ 0x400F6002u, /* Base address: 0x400F6000 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x0Cu, 0x10u}, {0xC2u, 0x01u}, {0x58u, 0x10u}, {0x98u, 0x10u}, {0xD4u, 0x01u}, {0x02u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00000003u); /* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL0 */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL0), 0x00000000u); /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_PC */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00000000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x80000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x00020000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x00000081u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00400000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_INTR_CFG), 0x00008000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x00000001u); /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x000000C1u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00D80006u);//.........这里部分代码省略.........
开发者ID:AH9Harris，项目名称:ECE9407Lab03，代码行数:101，
示例28: cyfitter_cfg//.........这里部分代码省略......... {0x9Bu, 0x08u}, {0xA2u, 0x80u}, {0xB3u, 0x01u}, {0xB7u, 0x08u}, {0xD6u, 0x03u}, {0xECu, 0x06u}, {0x10u, 0x01u}, {0x11u, 0x01u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x33000000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0330EE00u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000083u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x0040004Eu); /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000019u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00000036u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x00000038u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000C1u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00D80000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC2), 0x00000001u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000060u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x001B0D80u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x80280000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00020000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x00030000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x20000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x10000000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x0000000Du); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x0000000Eu); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u)); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u)); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:stuffekarl，项目名称:KingFunk2，代码行数:101，
示例29: cyfitter_cfg//.........这里部分代码省略......... {0x5Fu, 0x01u}, {0x18u, 0x01u}, {0xB4u, 0x01u}, {0xE2u, 0x10u}, {0xE6u, 0x08u}, {0x63u, 0x02u}, {0x66u, 0x08u}, {0x87u, 0x01u}, {0x8Eu, 0x08u}, {0xD6u, 0x40u}, {0xD8u, 0x80u}, {0xE6u, 0x10u}, {0x6Cu, 0x40u}, {0x70u, 0x08u}, {0xDCu, 0x03u}, {0x1Au, 0x80u}, {0x22u, 0x80u}, {0x61u, 0x02u}, {0x86u, 0x80u}, {0x8Eu, 0x40u}, {0xA1u, 0x02u}, {0xB4u, 0x48u}, {0xB5u, 0x02u}, {0xC6u, 0x08u}, {0xC8u, 0x08u}, {0xD8u, 0x02u}, {0xE2u, 0x08u}, {0xECu, 0x08u}, }; CYPACKED typedef struct { void CYFAR *address; uint16 size; } CYPACKED_ATTR cfg_memset_t; static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x03300000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x000000FFu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x000000FFu); /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000061u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00DB0000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x00000001u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x0000000Fu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x0000000Fu); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x30000000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x20000000u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xF3u) | 0x04u); CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:gsgill112，项目名称:PSoC4_CY8CKIT-049_Tutorial，代码行数:101，
示例30: cyfitter_cfg//.........这里部分代码省略......... static const uint8 CYCODE BS_UDB_0_0_0_CONFIG_VAL[] = { 0x04u, 0x00u, 0x41u, 0x02u, 0x45u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x33u, 0x00u, 0x08u, 0x00u, 0x00u, 0x01u, 0xF1u, 0x02u, 0x04u, 0x4Du, 0x30u, 0xB2u, 0x4Cu, 0xBAu, 0x88u, 0x45u, 0x00u, 0x40u, 0x10u, 0x80u, 0x20u, 0x45u, 0x00u, 0x00u, 0x08u, 0x45u, 0x08u, 0x00u, 0x00u, 0x55u, 0x20u, 0x8Au, 0x10u, 0x22u, 0x00u, 0x00u, 0x00u, 0x03u, 0x0Fu, 0x3Cu, 0x0Fu, 0x08u, 0xC0u, 0xC0u, 0x30u, 0x08u, 0x00u, 0x82u, 0xA0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x63u, 0x02u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x0Bu, 0xF0u, 0x26u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x40u, 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, 0x99u, 0x09u, 0x00u, 0x01u, 0xF0u, 0x00u, 0x40u, 0x02u, 0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ {(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), BS_UDB_0_1_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYDEV_UDB_P1_U1_BASE), BS_UDB_0_0_0_CONFIG_VAL, 128u}, }; uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) { const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; CYMEMZERO(ms->address, (uint32)(ms->size)); } /* Copy device configuration data into registers */ for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) { const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; void * CYDATA destPtr = mc->dest; const void CYCODE * CYDATA srcPtr = mc->src; uint16 CYDATA numBytes = mc->size; CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); } cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* HSIOM Starting address: CYDEV_HSIOM_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x30000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000003u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x33033333u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x3330EE00u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u); /* IOPINS0_0 Starting address: CYDEV_PRT0_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000081u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00C00006u); /* IOPINS0_1 Starting address: CYDEV_PRT1_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000001u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00000006u); /* IOPINS0_2 Starting address: CYDEV_PRT2_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000DFu); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00D86DB6u); /* IOPINS0_3 Starting address: CYDEV_PRT3_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x000000E0u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00DB0D80u); /* IOPINS0_4 Starting address: CYDEV_PRT4_DR */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000002u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u); /* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x40020000u); /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x00010000u); /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x311B0000u); /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u); CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0xD0000000u); /* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000001u); /* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u); /* Enable digital routing */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u); /* Enable UDB array */ CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u); } /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Perform basic analog initialization to defaults */ AnalogSetDefault();}
开发者ID:antoniorohit，项目名称:PSoC_Projects，代码行数:101，
注：本文中的CY_SET_XTND_REG8函数示例整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。
C++ C_函数代码示例
C++ CY_SET_REG8函数代码示例 |
