自学教程：C++ CyDelayUs函数代码示例

bool NRF24L01p::Receive(uint8_t* data, uint8_t size){    NRF24L01p_CE_Write(1); //Start listening.    CyDelay(2); //Give it some time to receive the package.	uint8_t status = ReadRegister(NRF24L01p_REGISTER_ADDRESS_STATUS);    if(status&(0b1<<NRF24L01p_MNEMONIC_STATUS_RX_DR)) //Check if we received a package.    {        WriteRegister(NRF24L01p_REGISTER_ADDRESS_STATUS, 0b1<<NRF24L01p_MNEMONIC_STATUS_RX_DR); //Clear the bit that says we received a package.        NRF24L01p_CS_Write(0);        NRF24L01p_SPI_CONTROLLER_WriteTxData(NRF24L01p_INSTRUCTION_R_RX_PAYLOAD); //Prepare to read the payload.        CyDelayUs(5);                for(uint8_t c=0; c<size; c++) //Receive the data.        {            NRF24L01p_SPI_CONTROLLER_WriteTxData(NRF24L01p_INSTRUCTION_NOP); //Sending NOPs all day long. Sending NOPs while I sing this song.            CyDelayUs(5); //Give the received data some time to settle in.            data[c] = NRF24L01p_SPI_INPUT_REG_ReadRegValue();        }                CyDelayUs(10); //TODO: Check why this one is here.        NRF24L01p_CS_Write(1);        NRF24L01p_CE_Write(0);                NRF24L01p_SPI_CONTROLLER_WriteTxData(NRF24L01p_INSTRUCTION_FLUSH_RX); //Clean up any other packets.        CyDelayUs(5);                return true;    }        NRF24L01p_CE_Write(0);        return false;}

void NRF24L01p::Transmit(uint8_t* data, uint8_t size){    uint8_t reg = 0;    reg = ReadRegister(NRF24L01p_REGISTER_ADDRESS_CONFIG);	reg &= ~((uint8_t)(0b1<<NRF24L01p_MNEMONIC_CONFIG_PRIM_RX)); //Put the device in TX mode.	WriteRegister(NRF24L01p_REGISTER_ADDRESS_CONFIG, reg);    CyDelayUs(150); //Wait for the device to switch to TX mode.    uint8_t buffer[33] = {0};	buffer[0] = NRF24L01p_INSTRUCTION_W_TX_PAYLOAD_NO_ACK;	memcpy(&buffer[1], data, size);    NRF24L01p_CS_Write(0);	NRF24L01p_SPI_CONTROLLER_PutArray(buffer, size+1);    CyDelayUs(10);	NRF24L01p_CS_Write(1);	NRF24L01p_CE_Write(1); //Make the NRF24L01p transmit the data.	CyDelayUs(10);	NRF24L01p_CE_Write(0);	reg |= 0b1<<NRF24L01p_MNEMONIC_CONFIG_PRIM_RX; //Put the device in RX mode.    CyDelayUs(1400);	WriteRegister(NRF24L01p_REGISTER_ADDRESS_CONFIG, reg);}

void main(){	settings = &settings_data;	    CyGlobalIntEnable;	Backlight_Write(1);		disp_reset_Write(0);	CyDelayUs(10);	disp_reset_Write(1);	CyDelayUs(10);	Display_Start();	Display_SetContrast(settings->lcd_contrast);		#ifdef USE_SPLASHSCREEN	load_splashscreen();	#endif		IDAC_High_Start();	IDAC_Low_Start();	set_output_mode(OUTPUT_MODE_FEEDBACK);			start_adc();	setup();		xTaskCreate(vTaskUI, (signed portCHAR *) "UI", 178, NULL, tskIDLE_PRIORITY + 2, &ui_task);	xTaskCreate(vTaskComms, (signed portCHAR *) "UART", 141, NULL, tskIDLE_PRIORITY + 2, &comms_task);		prvHardwareSetup();	vTaskStartScheduler();}

/********************************************************************************  Function Name: CharLCD_1_WrDatNib********************************************************************************** Summary:*  Writes a data nibble to the LCD module.** Parameters:*  nibble:  Byte containing nibble in the least significant nibble to be*           written to the LCD module.** Return:*  None.********************************************************************************/static void CharLCD_1_WrDatNib(uint8 nibble) {    /* RS should be low to select data register */    CharLCD_1_PORT_DR_REG |= CharLCD_1_RS;    /* Reset RW for write operation */    CharLCD_1_PORT_DR_REG &= ((uint8)(~CharLCD_1_RW));    /* Guaranteed delay between Setting RS and RW and setting E bits */    CyDelayUs(0u);        /* Clear data pins */    CharLCD_1_PORT_DR_REG &= ((uint8)(~CharLCD_1_DATA_MASK));    /* Write data, bring E high */    #if(0u != CharLCD_1_PORT_SHIFT) /* MISRA forbids shift by 0 so need to handle that */        CharLCD_1_PORT_DR_REG |=             (CharLCD_1_E | ((uint8)(((uint8) nibble) << CharLCD_1_PORT_SHIFT)));    #else        CharLCD_1_PORT_DR_REG |= (CharLCD_1_E | nibble);    #endif /* (0u != CharLCD_1_PORT_SHIFT) */    /* Minimum of 230 ns delay */    CyDelayUs(1u);    CharLCD_1_PORT_DR_REG &= ((uint8)(~CharLCD_1_E));}

//Read a single worduint16 as5047_read_single(uint16 reg){	//Clear buffers to start in a known state:	SPIM_1_ClearTxBuffer();	SPIM_1_ClearRxBuffer();    CyDelayUs(10);	//Send 1st byte (reg addr)	spidata_mosi2[0] = add_even_parity_msb(AS5047_READ | reg);	SPIM_1_PutArray(spidata_mosi2, 1);		CyDelayUs(10);    spidata_miso[0] = SPIM_1_ReadRxData();		//Send 2nd byte (empty, used to read)	spidata_mosi2[0] = add_even_parity_msb(AS5047_READ | AS5047_REG_NOP);	SPIM_1_PutArray(spidata_mosi2, 1);		CyDelayUs(10);    spidata_miso[1] = SPIM_1_ReadRxData();			//spidata_miso[1] contains the answer. Remove parity and return value	//ToDo: ignore word if wrong parity	last_as5047_word = (spidata_miso[1] & 0x3FFF);	as5047_angle = last_as5047_word;	return last_as5047_word;}

/******************************************************************************** Function Name: USBUART_Resume********************************************************************************** Summary:*  This function enables the USBFS block after power down mode.** Parameters:*  None.** Return:*  None.** Global variables:*  USBUART_backup - checked.** Reentrant:*  No.********************************************************************************/void USBUART_Resume(void) {    uint8 enableInterrupts;    enableInterrupts = CyEnterCriticalSection();    if(USBUART_backup.enableState != 0u)    {        #if(USBUART_DP_ISR_REMOVE == 0u)            CyIntDisable(USBUART_DP_INTC_VECT_NUM);        #endif /*  USBUART_DP_ISR_REMOVE */        /* Enable USB block */        USBUART_PM_ACT_CFG_REG |= USBUART_PM_ACT_EN_FSUSB;        /* Enable USB block for Standby Power Mode */        USBUART_PM_STBY_CFG_REG |= USBUART_PM_STBY_EN_FSUSB;        /* Enable core clock */        USBUART_USB_CLK_EN_REG |= USBUART_USB_CLK_ENABLE;        /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/        USBUART_PM_USB_CR0_REG |= USBUART_PM_USB_CR0_REF_EN;        /* The reference will be available ~40us after power restored */        CyDelayUs(40u);        /* Return VRegulator*/        USBUART_CR1_REG |= USBUART_backup.mode;        CyDelayUs(0u);  /*~50ns delay */        /* Enable USBIO */        USBUART_PM_USB_CR0_REG |= USBUART_PM_USB_CR0_PD_N;        CyDelayUs(2u);        /* Set the USBIO pull-up enable */        USBUART_PM_USB_CR0_REG |= USBUART_PM_USB_CR0_PD_PULLUP_N;        /* Re-init Arbiter configuration for DMA transfers */        #if(USBUART_EP_MM != USBUART__EP_MANUAL)            /* Usb arb interrupt enable */            USBUART_ARB_INT_EN_REG = USBUART_ARB_INT_MASK;            #if(USBUART_EP_MM == USBUART__EP_DMAMANUAL)                USBUART_ARB_CFG_REG = USBUART_ARB_CFG_MANUAL_DMA;            #endif   /*  USBUART_EP_MM == USBUART__EP_DMAMANUAL */            #if(USBUART_EP_MM == USBUART__EP_DMAAUTO)                /*Set cfg cmplt this rises DMA request when the full configuration is done */                USBUART_ARB_CFG_REG = USBUART_ARB_CFG_AUTO_DMA | USBUART_ARB_CFG_AUTO_MEM;            #endif   /*  USBUART_EP_MM == USBUART__EP_DMAAUTO */        #endif   /*  USBUART_EP_MM != USBUART__EP_MANUAL */        /* STALL_IN_OUT */        CY_SET_REG8(USBUART_EP0_CR_PTR, USBUART_MODE_STALL_IN_OUT);        /* Enable the SIE with a last address */        USBUART_CR0_REG |= USBUART_CR0_ENABLE;        CyDelayCycles(1u);        /* Finally, Enable d+ pullup and select iomode to USB mode*/        CY_SET_REG8(USBUART_USBIO_CR1_PTR, USBUART_USBIO_CR1_USBPUEN);        /* Restore USB register settings */        USBUART_RestoreConfig();    }    CyExitCriticalSection(enableInterrupts);}

/****************************************************************************** Function Name: BatteryLevel_Measure()******************************************************************************* Summary:* Measures the current battery level.** Parameters:* None** Return:* None** Theory:* The function checks if the battery measurement enable flag is set in the * ADC ISR, and then measures the current battery level.** Side Effects:* None** Note:******************************************************************************/void BatteryLevel_Measure(void){    uint16 adcCountsVref;    static uint32 vddaVoltageMv;        /* Disconnect the VREF pin from the chip and lose its existing voltage */    CY_SET_REG32(CYREG_SAR_CTRL, CY_GET_REG32(CYREG_SAR_CTRL) & ~(0x01 << 7));    VrefInputPin_SetDriveMode(VrefInputPin_DM_STRONG);    VrefInputPin_Write(0);    CyDelayUs(10);        /* Switch SAR reference to 1.024V to charge external cap */    VrefInputPin_SetDriveMode(VrefInputPin_DM_ALG_HIZ);    CY_SET_REG32(CYREG_SAR_CTRL, (CY_GET_REG32(CYREG_SAR_CTRL) & ~(0x000000F0Lu)) | (0x00000040Lu) | (0x01Lu << 7));    CyDelayUs(100);        /* Switch the reference back to VDDA/2 for measuring the REF voltage */    CY_SET_REG32(CYREG_SAR_CTRL, CY_GET_REG32(CYREG_SAR_CTRL) & ~(0x01 << 7));    CY_SET_REG32(CYREG_SAR_CTRL, (CY_GET_REG32(CYREG_SAR_CTRL) & ~(0x00000070Lu)) | (0x00000060Lu));        /* Enable channel 1 of the ADC, disable channel 0 */    ADC_SetChanMask(0x02);        /* Clear ADC interrupt triggered flag and start a new conversion */    canMeasureBattery = false;    ADC_StartConvert();    while(true != canMeasureBattery);    /* Since our ADC reference is VDDA/2, we get full scale (11-bit) at VDDA/2.     * We can calculate VDDA by the formula:     * VDDA = (VREF * (Full scale ADC out) * 2) / (ADC out for VREF)     */    adcCountsVref = ADC_GetResult16(1);    if(adcCountsVref != 0)    {        vddaVoltageMv = ((uint32)VREF_VOLTAGE_MV * ADC_FULL_SCALE_OUT * 2) / (uint32)adcCountsVref;    }        /* Battery level is implemented as a linear plot from 2.0V to 3.0V      * Battery % level = (0.1 x VDDA in mV) - 200     */    batteryLevel = ((uint32)(vddaVoltageMv / 10)) - 200;    if((batteryLevel > 100) && (batteryLevel < 230))    {        batteryLevel = 100;    }    else if(batteryLevel >= 230)    {        batteryLevel = 0;    }            /* Enable channel 0 again, disable channel 1 */    ADC_SetChanMask(0x01);        /* Enable bypass cap for the VDDA/2 reference */    CY_SET_REG32(CYREG_SAR_CTRL, CY_GET_REG32(CYREG_SAR_CTRL) | (0x01 << 7));}

/******************************************************************************** Function Name: USBUART_Suspend********************************************************************************** Summary:*  This function disables the USBFS block and prepares for power down mode.** Parameters:*  None.** Return:*   None.** Global variables:*  USBUART_backup.enable:  modified.** Reentrant:*  No.********************************************************************************/void USBUART_Suspend(void) {    uint8 enableInterrupts;    enableInterrupts = CyEnterCriticalSection();    if((CY_GET_REG8(USBUART_CR0_PTR) & USBUART_CR0_ENABLE) != 0u)    {   /* USB block is enabled */        USBUART_backup.enableState = 1u;        #if(USBUART_EP_MM != USBUART__EP_MANUAL)            USBUART_Stop_DMA(USBUART_MAX_EP);     /* Stop all DMAs */        #endif   /*  USBUART_EP_MM != USBUART__EP_MANUAL */        /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */        USBUART_USBIO_CR0_REG &= (uint8)~USBUART_USBIO_CR0_TEN;        CyDelayUs(0u);  /*~50ns delay */        /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */        USBUART_PM_USB_CR0_REG &=                                (uint8)~(USBUART_PM_USB_CR0_PD_N | USBUART_PM_USB_CR0_PD_PULLUP_N);        /* Disable the SIE */        USBUART_CR0_REG &= (uint8)~USBUART_CR0_ENABLE;        CyDelayUs(0u);  /* ~50ns delay */        /* Store mode and Disable VRegulator*/        USBUART_backup.mode = USBUART_CR1_REG & USBUART_CR1_REG_ENABLE;        USBUART_CR1_REG &= (uint8)~USBUART_CR1_REG_ENABLE;        CyDelayUs(1u);  /* 0.5 us min delay */        /* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/        USBUART_PM_USB_CR0_REG &= (uint8)~USBUART_PM_USB_CR0_REF_EN;        /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/        USBUART_USBIO_CR1_REG |= USBUART_USBIO_CR1_IOMODE;        /* Disable USB in ACT PM */        USBUART_PM_ACT_CFG_REG &= (uint8)~USBUART_PM_ACT_EN_FSUSB;        /* Disable USB block for Standby Power Mode */        USBUART_PM_STBY_CFG_REG &= (uint8)~USBUART_PM_STBY_EN_FSUSB;        CyDelayUs(1u); /* min  0.5us delay required */    }    else    {        USBUART_backup.enableState = 0u;    }    CyExitCriticalSection(enableInterrupts);    /* Set the DP Interrupt for wake-up from sleep mode. */    #if(USBUART_DP_ISR_REMOVE == 0u)        (void) CyIntSetVector(USBUART_DP_INTC_VECT_NUM, &USBUART_DP_ISR);        CyIntSetPriority(USBUART_DP_INTC_VECT_NUM, USBUART_DP_INTC_PRIOR);        CyIntClearPending(USBUART_DP_INTC_VECT_NUM);        CyIntEnable(USBUART_DP_INTC_VECT_NUM);    #endif /* (USBUART_DP_ISR_REMOVE == 0u) */}

void LCD_Write(uint8 data_or_command, uint8 data_value){    CE_Write(LOW);    CyDelayUs(DELAY_1_US);    DC_Write(data_or_command);    Send_Data(data_value);    CE_Write(HIGH);    CyDelayUs(DELAY_1_US);}

void NRF24L01writeReg(uint8 address, uint8 data){    while(!(SPIM_Funk_ReadTxStatus() & (SPIM_Funk_STS_SPI_DONE | SPIM_Funk_STS_SPI_IDLE)));    /* Senden eines Wortes */    SPIM_Funk_WriteTxData((1 << 5) & address);    CyDelayUs(10);    SPIM_Funk_WriteTxData(data);    CyDelayUs(10);}

CY_CFG_SECTIONstatic void ClockSetup(void){	/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));	/* Trim IMO BG based on desired frequency. */	SetIMOBGTrims(12u);	/* Going less than or equal to 24MHz, so update the clock speed then adjust trim value. */	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (12u));	CyDelayCycles(5u);	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM09)));	CyDelayUs(5u);	/* Start the WCO */	CySysClkWcoStart();	CyDelay(500u); /* WCO may take up to 500ms to start */	(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM);    /* Switch to the low power mode */	/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);	CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00002D6Au);	/* Disable Crystal Stable Interrupt before enabling ECO */	CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));	/* Start the ECO and do not check status since it is not needed for HFCLK */	(void)CySysClkEcoStart(2000u);	CyDelayUs(1500u); /* Wait to stabalize */	/* Setup phase aligned clocks */	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL02, 0x00000B00u);	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF42u);	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL00, 0x0000FE00u);	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL01, 0x0000FE00u);	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);	/* CYDEV_PERI_PCLK_CTL11 Starting address: CYDEV_PERI_PCLK_CTL11 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL11), 0x00000042u);	/* CYDEV_PERI_PCLK_CTL05 Starting address: CYDEV_PERI_PCLK_CTL05 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL05), 0x00000040u);	/* CYDEV_PERI_PCLK_CTL04 Starting address: CYDEV_PERI_PCLK_CTL04 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL04), 0x00000041u);	/* Set Flash Cycles based on newly configured 12.00MHz HFCLK. */	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0000u));}

/******************************************************************************** Function Name: FTCommandWrite********************************************************************************** Summary:*  Send a command to FT chip.*  Every command is 1 byte long and have to be followed by 2 bytes with 0 value.** Parameters:*  command: command to be sent.** Return:*  none********************************************************************************/void FTCommandWrite(uint8 command){    unsigned char tobesent[3] = {command, 0x00, 0x00};        mmSPI_SS(0);    CyDelayUs(SS_DELAY);    mmSPI_SpiUartClearTxBuffer();    mmSPI_SpiUartPutArray(tobesent, 3);        mSPI_WAIT_TXDONE();    CyDelayUs(SS_DELAY);    mmSPI_SS(1);}

/******************************************************************************** Function Name: CyFlashGetSpcAlgorithm********************************************************************************** Summary:*  Sends a command to the SPC to download code into RAM.** Parameters:*  None** Return:*  status:*   CYRET_SUCCESS - if successful*   CYRET_LOCKED  - if Flash writing already in use*   CYRET_UNKNOWN - if there was an SPC error********************************************************************************/static cystatus CyFlashGetSpcAlgorithm(void) {    cystatus status;    /* Make sure SPC is powered */    CySpcStart();    if(CySpcLock() == CYRET_SUCCESS)    {        status = CySpcGetAlgorithm();        if(CYRET_STARTED == status)        {            while(CY_SPC_BUSY)            {                /* Spin until idle. */                CyDelayUs(1u);            }            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)            {                status = CYRET_SUCCESS;            }        }        CySpcUnlock();    }    else    {        status = CYRET_LOCKED;    }    return (status);}

CY_CFG_SECTIONstatic void ClockSetup(void){	/* Enable HALF_EN before trimming for the flash accelerator. */	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));	/* Trim IMO BG based on desired frequency. */	SetIMOBGTrims(48u);	/* Going faster than 24MHz, so update trim value then adjust to new clock speed. */	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM45)));	CyDelayUs(5u);	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (53u));	/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT02), 0x00000010u);	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT03), 0x00000010u);	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000000u);	/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);	/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000000u);}

void NRF24L01initTX(){    SPIM_Funk_Start();        CE_Funk_Write(0);    /* CONFIG Register      * 0(default)0(RX interrupt)1(TX interrupt)1(MAX_RT interrupt)1(CRC_Enable)0(CRC 1 byte)0(PWR_DOWN)1(RX)     */    NRF24L01writeReg(0x00,0b01011000);    /* EN_RXADDR Register     * 00(default)000011(Enable RX pipes)     */    NRF24L01writeReg(0x01,0b00000011);    /* EN_AA Register     * 00(default)000011(Enable auto ACK)     */    NRF24L01writeReg(0x02,0b00000011);    /* RX_PW_Px Register     * 00(default)XXXXXX(pipe length)     */    NRF24L01writeReg(0x11,0b00100000);    NRF24L01writeReg(0x12,0b00100000);        CE_Funk_Write(1);    CyDelayUs(15);    }

uint16 NRF24L01readReg(uint8 addressfivebit){    SPIM_Funk_ClearRxBuffer();    /* Warten auf abschliessen der TX Uebertragung */    while(!(SPIM_Funk_ReadTxStatus() & (SPIM_Funk_STS_SPI_DONE | SPIM_Funk_STS_SPI_IDLE)));    /* Senden eines Wortes */    SPIM_Funk_WriteTxData(0x00 + addressfivebit);    CyDelayUs(10);    SPIM_Funk_WriteTxData(0xFF);    CyDelayUs(10);    while(SPIM_Funk_GetRxBufferSize()==0){CyDelayUs(50);}    uint16 received=SPIM_Funk_ReadRxData();    received=SPIM_Funk_ReadRxData();    CyDelayUs(10);    return received;}

void NRF24L01writeTXpayload(uint8 numberOfbytes, uint8* data){    /* Warten auf abschliessen der TX Uebertragung */    while(!(SPIM_Funk_ReadTxStatus() & (SPIM_Funk_STS_SPI_DONE | SPIM_Funk_STS_SPI_IDLE)))    {        CyDelayUs(5);    }    SPIM_Funk_WriteTxData(0b10100000);    uint16 transmitted=0;    while(transmitted<numberOfbytes)    {        /* Weniger als 255 Werte zu übertragen */        if((numberOfbytes-transmitted)<255)         {            SPIM_Funk_PutArray(&data[transmitted],numberOfbytes-transmitted);            transmitted = numberOfbytes;        }        /* Noch mehr als 255 Restwerte */        else         {            SPIM_Funk_PutArray(&data[transmitted],255);            transmitted += 255;        }    }}

CY_CFG_SECTIONstatic void ClockSetup(void){	/* Enable HALF_EN before trimming for the flash accelerator. */	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));	/* Trim IMO BG based on desired frequency. */	SetIMOBGTrims(24u);	/* Going less than or equal to 24MHz, so update the clock speed then adjust trim value. */	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (25u));	CyDelayCycles(5u);	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM21)));	CyDelayUs(5u);	/* Disable HALF_EN since it is not required at this IMO frequency. */	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);	/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT12), 0x00000010u);	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);	/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000033u);}

/********************************************************************************  Function Name: LCD_WrDatNib********************************************************************************** Summary:*  Writes a data nibble to the LCD module.** Parameters:*  nibble:  byte containing nibble in least significant nibble to be written*           to LCD module.** Return:*  None.********************************************************************************/static void LCD_WrDatNib(uint8 nibble) {    LCD_IsReady();    /* RS shoul be low to select data register */    LCD_PORT_DR_REG |= LCD_RS;    /* Reset RW for write operation */    LCD_PORT_DR_REG &= ((uint8)(~LCD_RW));    /* Two following lines of code will provide us with 40ns delay */    /* Clear data pins */    LCD_PORT_DR_REG &= ((uint8)(~LCD_DATA_MASK));    /* Write in data, bring E high*/    #if(0u != LCD_PORT_SHIFT) /* MISRA forbids shift by 0 so need to handle that */        LCD_PORT_DR_REG |=             (LCD_E | ((uint8)(((uint8) nibble) << LCD_PORT_SHIFT)));    #else        LCD_PORT_DR_REG |= (LCD_E | nibble);    #endif /* (0u != LCD_PORT_SHIFT) */    /* Minimum of 230 ns delay */    CyDelayUs(1u);    LCD_PORT_DR_REG &= ((uint8)(~LCD_E));}

void NRF24L01p::WriteRegister(uint8_t registerAddress, uint8_t data){	uint8_t buffer[2] = {(uint8_t)(NRF24L01p_INSTRUCTION_W_REGISTER|registerAddress), data};	NRF24L01p_CS_Write(0);	NRF24L01p_SPI_CONTROLLER_PutArray(buffer, 2);    CyDelayUs(5);	NRF24L01p_CS_Write(1);}

CY_CFG_SECTIONstatic void ClockSetup(void){	/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));	/* Start the WCO */	CySysClkWcoStart();	CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */	(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM);    /* Switch to the low power mode */	/* Setup and trim IMO based on desired frequency. */	CySysClkWriteImoFreq(48u);	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);	/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);	/* Enable fast start mode for XO */	CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);	CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);	/*Set XTAL(ECO) divider*/	CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG), 0x00000000u);	/* Disable Crystal Stable Interrupt before enabling ECO */	CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));	/* Start the ECO and do not check status since it is not needed for HFCLK */	(void)CySysClkEcoStart(2000u);	CyDelayUs(1500u); /* Wait to stabalize */	/* Setup phase aligned clocks */	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00BB7F00u);	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x0001A000u);	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);	/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);	/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000041u);	/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);	(void)CyIntSetVector(8u, &CySysWdtIsr);	CyIntEnable(8u);	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_MATCH), 0x00000020u);	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000005u);	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000008u);	while ((CY_GET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL)) & 0x00000008u) != 0u) { }	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000001u);}

CY_CFG_SECTIONstatic void ClockSetup(void){	/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));	/* Start the WCO */	CySysClkWcoStart();	(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM);    /* Switch to the low power mode */	/* Setup and trim IMO based on desired frequency. */	CySysClkWriteImoFreq(24u);	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);	/* Enable fast start mode for XO */	CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);	CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);	/* Disable Crystal Stable Interrupt before enabling ECO */	CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));	/* Start the ECO and do not check status since it is not needed for HFCLK */	(void)CySysClkEcoStart(2000u);	CyDelayUs(1500u); /* Wait to stabalize */	/* Setup phase aligned clocks */	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL2, 0x0001DF00u);	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF42u);	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00000E00u);	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00001000u);	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);	/* CYDEV_PERI_PCLK_CTL11 Starting address: CYDEV_PERI_PCLK_CTL11 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL11), 0x00000042u);	/* CYDEV_PERI_PCLK_CTL8 Starting address: CYDEV_PERI_PCLK_CTL8 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL8), 0x00000042u);	/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000042u);	/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);	/* CYDEV_PERI_PCLK_CTL1 Starting address: CYDEV_PERI_PCLK_CTL1 */	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL1), 0x00000041u);	(void)CyIntSetVector(8u, &CySysWdtIsr);	CyIntEnable(8u);	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);	/* Set Flash Cycles based on newly configured 24.00MHz HFCLK. */	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0011u));}

void scsiPhyReset(){	trace(trace_scsiPhyReset);	if (dmaInProgress)	{		dmaInProgress = 0;		dmaBuffer = NULL;		dmaSentCount = 0;		dmaTotalCount = 0;		CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN);		CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN);		// CyDmaChGetRequest returns 0 for the relevant bit once the		// request is completed.		trace(trace_spinDMAReset);		while (			(CyDmaChGetRequest(scsiDmaTxChan) & CY_DMA_CPU_TERM_CHAIN) &&			!scsiTxDMAComplete			)		{}		while ((			CyDmaChGetRequest(scsiDmaRxChan) & CY_DMA_CPU_TERM_CHAIN) &&			!scsiRxDMAComplete			)		{}		CyDelayUs(1);		CyDmaChDisable(scsiDmaTxChan);		CyDmaChDisable(scsiDmaRxChan);	}	// Set the Clear bits for both SCSI device FIFOs	scsiTarget_AUX_CTL = scsiTarget_AUX_CTL | 0x03;	// Trigger RST outselves.  It is connected to the datapath and will	// ensure it returns to the idle state.  The datapath runs at the BUS clk	// speed (ie. same as the CPU), so we can be sure it is active for a sufficient	// duration.	SCSI_RST_ISR_Disable();	SCSI_SetPin(SCSI_Out_RST);	SCSI_CTL_PHASE_Write(0);	SCSI_ClearPin(SCSI_Out_ATN);	SCSI_ClearPin(SCSI_Out_BSY);	SCSI_ClearPin(SCSI_Out_ACK);	SCSI_ClearPin(SCSI_Out_RST);	SCSI_ClearPin(SCSI_Out_SEL);	SCSI_ClearPin(SCSI_Out_REQ);	// Allow the FIFOs to fill up again.	SCSI_ClearPin(SCSI_Out_RST);	SCSI_RST_ISR_Enable();	scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03);	SCSI_Parity_Error_Read(); // clear sticky bits}

/******************************************************************************** Function Name: CyFlash_Start********************************************************************************** Summary:*  Enable the Flash.** Parameters:*  None** Return:*  None********************************************************************************/void CyFlash_Start(void) {    /* Active Power Mode */    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;    /* Standby Power Mode */    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;    CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);}

void NRF24L01p::WriteExtendedRegister(uint8_t registerAddress, uint8_t* data, uint8_t size){	uint8_t buffer[size+1];    memset(buffer, 0, size+1);	buffer[0] = NRF24L01p_INSTRUCTION_W_REGISTER|registerAddress;	memcpy(&buffer[1], data, size);	NRF24L01p_CS_Write(0);	NRF24L01p_SPI_CONTROLLER_PutArray(buffer, size+1);    CyDelayUs(10);	NRF24L01p_CS_Write(1);}

void Send_Data(int8 value){    uint8 index3;    for (index3 = 0; index3 < FONT_HEIGHT; index3++)    {        /* Take one bit (MSb) at a time and send it to Data Input pin of LCD */        if(MSb_POSITION == (value & MSb_POSITION))            Din_Write(HIGH);        else            Din_Write(LOW);                /* After setting the Data value on Din pin, toggle the Clock so that LCD can read Din */        Clk_Write(HIGH);        CyDelayUs(DELAY_1_US);        Clk_Write(LOW);        CyDelayUs(DELAY_1_US);                /* Left shift the value before processing next bit */        value <<= SHIFT_LEFT_BY_1;    }}

void main(){    CyGlobalIntEnable;#if USE_WATCHDOG    // Enable watchdog timer for every 2 seconds    CySysWdtWriteMode(0, CY_SYS_WDT_MODE_RESET);    CySysWdtWriteMatch(0, 0xFFFF);    CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK);#endif    if(settings->settings_version < default_settings.settings_version)        factory_reset();    Backlight_Write(1);		disp_reset_Write(0);	CyDelayUs(10);	disp_reset_Write(1);	CyDelayUs(10);	Display_Start();    Display_SetContrast(settings->lcd_contrast);		#ifdef USE_SPLASHSCREEN	load_splashscreen();	#endif		IDAC_High_Start();	IDAC_Low_Start();    state.calibrating = 0;    set_current(0);	set_output_mode(OUTPUT_MODE_FEEDBACK);			start_adc();	setup();	//Create the two tasks	xTaskCreate(vTaskUI, (signed portCHAR *) "UI", 178, NULL, tskIDLE_PRIORITY + 2, &ui_task);	xTaskCreate(vTaskComms, (signed portCHAR *) "UART", 180, NULL, tskIDLE_PRIORITY + 2, &comms_task);		prvHardwareSetup();	vTaskStartScheduler();}

/******************************************************************************** Function Name: ResistiveTouch_TouchDetect********************************************************************************** Summary:*  Determines if the screen is touched.** Parameters:*  None** Return:*  uint8: The touch state.*  0 - untouched*  1 - touched********************************************************************************/uint8 ResistiveTouch_TouchDetect(void) {    /* Configure x+ pin to detect touch. */    CyPins_SetPinDriveMode(ResistiveTouch_xp_0, PIN_DM_STRONG);    /* Add delay for signal to stabilize. */    CyDelayUs(5u);    CyPins_SetPinDriveMode(ResistiveTouch_xp_0, PIN_DM_RES_UP);        /* Switch AMux if channel 0 is not selected. */    if(ResistiveTouch_AMux_GetChannel() != ResistiveTouch_AMUX_XP_CHAN)    {        ResistiveTouch_AMux_Next();    }    /* Configure x-, y+ and y- to detect touch. */    CyPins_SetPinDriveMode(ResistiveTouch_xm_0, PIN_DM_ALG_HIZ);    CyPins_SetPinDriveMode(ResistiveTouch_yp_0, PIN_DM_ALG_HIZ);    CyPins_SetPinDriveMode(ResistiveTouch_ym_0, PIN_DM_STRONG);    /* Add delay for signal to stabilize. The delay is dependant on whether    * the measurement has been done before touch detect or not.    */    if (ResistiveTouch_measurementFlag == 0u)    {        CyDelayUs(20u);    }    else    {        ResistiveTouch_measurementFlag = 0u;        CyDelayUs(8u);            }    /* The screen is touched if the measured value is lower than the specified    * threshold.    */    return ((ResistiveTouch_Measure() < ResistiveTouch_TOUCH_THRESHOLD) ? 1u : 0u);}

/******************************************************************************** Function Name: DEBUG_UartCyBtldrCommRead********************************************************************************** Summary:*  Allows the caller to read data from the bootloader host (the host writes the*  data). The function handles polling to allow a block of data to be completely*  received from the host device.** Parameters:*  pData:    Pointer to storage for the block of data to be read from the*            bootloader host*  size:     Number of bytes to be read.*  count:    Pointer to the variable to write the number of bytes actually*            read.*  timeOut:  Number of units in 10 ms to wait before returning because of a*            timeout.** Return:*  Returns CYRET_SUCCESS if no problem was encountered or returns the value*  that best describes the problem. For more information refer to the*  "Return Codes" section of the System Reference Guide.********************************************************************************/cystatus DEBUG_UartCyBtldrCommRead(uint8 pData[], uint16 size, uint16 * count, uint8 timeOut){    cystatus status;    uint32 byteCount;    uint32 timeoutMs;    uint32 i;    status = CYRET_BAD_PARAM;    if ((NULL != pData) && (size > 0u))    {        status = CYRET_TIMEOUT;        timeoutMs = ((uint32) 10u * timeOut); /* Convert from 10mS check to 1mS checks */        /* Wait with timeout 1mS for packet end */        byteCount = 0u;        do        {            /* Check packet start */            if (0u != DEBUG_SpiUartGetRxBufferSize())            {                /* Wait for end of packet */                do                {                    byteCount = DEBUG_SpiUartGetRxBufferSize();                    CyDelayUs(DEBUG_UART_BYTE_TO_BYTE);                }                while (byteCount != DEBUG_SpiUartGetRxBufferSize());                byteCount = DEBUG_BYTES_TO_COPY(byteCount, size);                *count = (uint16) byteCount;                status = CYRET_SUCCESS;                break;            }            CyDelay(DEBUG_WAIT_1_MS);            --timeoutMs;        }        while (0u != timeoutMs);        /* Get data from RX buffer into bootloader buffer */        for (i = 0u; i < byteCount; ++i)        {            pData[i] = (uint8) DEBUG_SpiUartReadRxData();        }    }    return (status);}