自学教程：C++ DDPMSG函数代码示例

int ddp_path_top_clock_on(void){    DDPMSG("ddp path top clock on/n");    enable_clock(MT_CG_DISP0_SMI_COMMON   , "DDP");    enable_clock(MT_CG_DISP0_SMI_LARB0   , "DDP");    enable_clock(MT_CG_DISP0_MUTEX_32K   , "DDP");    DDPMSG("ddp CG:%x/n", DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));    return 0;}

static int setup_rdma_sec(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void *handle)	{	static int rdma_is_sec[2];	CMDQ_ENG_ENUM cmdq_engine;	int rdma_idx = rdma_index(module);	DISP_BUFFER_TYPE security = pConfig->rdma_config.security;	enum RDMA_MODE mode = rdma_config_mode(pConfig->rdma_config.address);	cmdq_engine = rdma_idx==0 ? CMDQ_ENG_DISP_RDMA0 : CMDQ_ENG_DISP_RDMA1;		if(!handle) {		DDPMSG("[SVP] bypass rdma sec setting sec=%d,handle=NULL/n", security);		return 0;		}	/* sec setting make sence only in memory mode ! */	if(mode == RDMA_MODE_MEMORY) {	if(security == DISP_SECURE_BUFFER) {		cmdqRecSetSecure(handle, 1);		/* set engine as sec */		cmdqRecSecureEnablePortSecurity(handle, (1LL << cmdq_engine));		//cmdqRecSecureEnableDAPC(handle, (1LL << cmdq_engine));		if(rdma_is_sec[rdma_idx] == 0)			DDPMSG("[SVP] switch rdma%d to sec/n", rdma_idx);		rdma_is_sec[rdma_idx] = 1;	} else {		if(rdma_is_sec[rdma_idx]) {			/* rdma is in sec stat, we need to switch it to nonsec */			cmdqRecHandle nonsec_switch_handle;			int ret;			ret = cmdqRecCreate(CMDQ_SCENARIO_DISP_PRIMARY_DISABLE_SECURE_PATH, &(nonsec_switch_handle));			if(ret)				DDPAEE("[SVP]fail to create disable handle %s ret=%d/n", __FUNCTION__, ret);			cmdqRecReset(nonsec_switch_handle);			_cmdq_insert_wait_frame_done_token_mira(nonsec_switch_handle);			cmdqRecSetSecure(nonsec_switch_handle, 1);			/*ugly work around by kzhang !!. will remove when cmdq delete disable scenario.			 * To avoid translation fault like ovl (see notes in ovl.c)*/			do_rdma_config_l(module, pConfig, nonsec_switch_handle);				/*in fact, dapc/port_sec will be disabled by cmdq*/			cmdqRecSecureEnablePortSecurity(nonsec_switch_handle, (1LL << cmdq_engine));			//cmdqRecSecureEnableDAPC(nonsec_switch_handle, (1LL << cmdq_engine));				cmdqRecFlush(nonsec_switch_handle);			cmdqRecDestroy(nonsec_switch_handle);				DDPMSG("[SVP] switch rdma%d to nonsec done/n", rdma_idx);		}		rdma_is_sec[rdma_idx] = 0;	}	}	return 0;	}

void ovl_dump_analysis(DISP_MODULE_ENUM module){	int i = 0;	unsigned int layer_offset = 0;	unsigned int rdma_offset = 0;	int index = (module==DISP_MODULE_OVL0)?0:1;	unsigned int offset = index*DISP_INDEX_OFFSET;	unsigned int src_on = DISP_REG_GET(DISP_REG_OVL_SRC_CON+offset);	DDPMSG("==DISP OVL%d ANALYSIS==/n", index);	DDPMSG("ovl_en=%d,layer_enable(%d,%d,%d,%d),bg(w=%d, h=%d),"		"cur_pos(x=%d,y=%d),layer_hit(%d,%d,%d,%d)/n",		DISP_REG_GET(DISP_REG_OVL_EN+offset),		DISP_REG_GET(DISP_REG_OVL_SRC_CON+offset)&0x1,		(DISP_REG_GET(DISP_REG_OVL_SRC_CON+offset)>>1)&0x1,		(DISP_REG_GET(DISP_REG_OVL_SRC_CON+offset)>>2)&0x1,		(DISP_REG_GET(DISP_REG_OVL_SRC_CON+offset)>>3)&0x1,		DISP_REG_GET(DISP_REG_OVL_ROI_SIZE+offset)&0xfff,		(DISP_REG_GET(DISP_REG_OVL_ROI_SIZE+offset)>>16)&0xfff,		DISP_REG_GET_FIELD(ADDCON_DBG_FLD_ROI_X, DISP_REG_OVL_ADDCON_DBG+offset),		DISP_REG_GET_FIELD(ADDCON_DBG_FLD_ROI_Y, DISP_REG_OVL_ADDCON_DBG+offset),		DISP_REG_GET_FIELD(ADDCON_DBG_FLD_L0_WIN_HIT, DISP_REG_OVL_ADDCON_DBG+offset),		DISP_REG_GET_FIELD(ADDCON_DBG_FLD_L1_WIN_HIT, DISP_REG_OVL_ADDCON_DBG+offset),		DISP_REG_GET_FIELD(ADDCON_DBG_FLD_L2_WIN_HIT, DISP_REG_OVL_ADDCON_DBG+offset),		DISP_REG_GET_FIELD(ADDCON_DBG_FLD_L3_WIN_HIT, DISP_REG_OVL_ADDCON_DBG+offset)	       );	for (i = 0; i < 4; i++) {		layer_offset = i * 0x20 + offset;		rdma_offset  = i * 0x4 + offset;		if (src_on & (0x1<<i)) {			DDPMSG("layer%d: w=%d,h=%d,off(x=%d,y=%d),pitch=%d,addr=0x%x,fmt=%s, source=%s/n",				i,				DISP_REG_GET(layer_offset+DISP_REG_OVL_L0_SRC_SIZE)&0xfff,				(DISP_REG_GET(layer_offset+DISP_REG_OVL_L0_SRC_SIZE)>>16)&0xfff,				DISP_REG_GET(layer_offset+DISP_REG_OVL_L0_OFFSET)&0xfff,				(DISP_REG_GET(layer_offset+DISP_REG_OVL_L0_OFFSET)>>16)&0xfff,				DISP_REG_GET(layer_offset+DISP_REG_OVL_L0_PITCH)&0xffff,				DISP_REG_GET(layer_offset+DISP_REG_OVL_L0_ADDR),				ovl_intput_format_name(					DISP_REG_GET_FIELD(L_CON_FLD_CFMT, DISP_REG_OVL_L0_CON+layer_offset),					DISP_REG_GET_FIELD(L_CON_FLD_BTSW, DISP_REG_OVL_L0_CON+layer_offset)),					(DISP_REG_GET_FIELD(L_CON_FLD_LARC, DISP_REG_OVL_L0_CON+layer_offset)==0)?"memory":"constant_color"					);			DDPMSG("ovl rdma%d status:(en %d)/n", i, DISP_REG_GET(layer_offset+DISP_REG_OVL_RDMA0_CTRL));				}	}

int ddp_path_top_clock_off(void){    DDPMSG("ddp path top clock off/n");    if(clk_is_force_on(MT_CG_DISP0_SMI_LARB0) || clk_is_force_on(MT_CG_DISP0_SMI_COMMON))    {    	DDPMSG("clear SMI_LARB0 & SMI_COMMON forced on/n");    	clk_clr_force_on(MT_CG_DISP0_SMI_LARB0);    	clk_clr_force_on(MT_CG_DISP0_SMI_COMMON);    }    disable_clock(MT_CG_DISP0_MUTEX_32K   , "DDP");    disable_clock(MT_CG_DISP0_SMI_LARB0   , "DDP");    disable_clock(MT_CG_DISP0_SMI_COMMON  , "DDP");    return 0;}

// extern smi_dumpDebugMsg(void);static int disp_irq_log_kthread_func(void *data){    unsigned int i=0;    while(1)    {        wait_event_interruptible(disp_irq_log_wq, disp_irq_log_module);        DDPMSG("disp_irq_log_kthread_func dump intr register: disp_irq_log_module=%d /n", disp_irq_log_module);        if((disp_irq_log_module&(1<<DISP_MODULE_RDMA0))!=0 )        {            // ddp_dump_analysis(DISP_MODULE_CONFIG);            ddp_dump_analysis(DISP_MODULE_RDMA0);            ddp_dump_analysis(DISP_MODULE_OVL0);            ddp_dump_analysis(DISP_MODULE_OVL1);                        // dump ultra/preultra related regs            DDPMSG("wdma_con1(2c)=0x%x, wdma_con2(0x38)=0x%x, rdma_gmc0(30)=0x%x, rdma_gmc1(38)=0x%x, fifo_con(40)=0x%x /n",               DISP_REG_GET(DISP_REG_WDMA_BUF_CON1),               DISP_REG_GET(DISP_REG_WDMA_BUF_CON2),               DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0),               DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1),               DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));            DDPMSG("ovl0_gmc: 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc: 0x%x, 0x%x, 0x%x, 0x%x, /n",               DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING),               DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING),               DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING),               DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING),               DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+DISP_OVL_INDEX_OFFSET),               DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING+DISP_OVL_INDEX_OFFSET),               DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING+DISP_OVL_INDEX_OFFSET),               DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING+DISP_OVL_INDEX_OFFSET));                        // dump smi regs            // smi_dumpDebugMsg();        }        else        {            for(i=0;i<DISP_MODULE_NUM;i++)            {                if( (disp_irq_log_module&(1<<i))!=0 )                {                    ddp_dump_reg(i);                }            }        }        disp_irq_log_module = 0;    }    return 0;}

int ddp_is_scenario_on_primary(DDP_SCENARIO_ENUM scenario){   int on_primary = 0;   switch(scenario)   {        case DDP_SCENARIO_PRIMARY_DISP:        case DDP_SCENARIO_PRIMARY_RDMA0_COLOR0_DISP:        case DDP_SCENARIO_PRIMARY_RDMA0_DISP:        case DDP_SCENARIO_PRIMARY_BYPASS_RDMA:        case DDP_SCENARIO_PRIMARY_OVL_MEMOUT:        case DDP_SCENARIO_PRIMARY_DITHER_MEMOUT:        case DDP_SCENARIO_PRIMARY_UFOE_MEMOUT:        case DDP_SCENARIO_PRIMARY_ALL:             case DDP_SCENARIO_MULTIPLE_OVL:            on_primary = 1;            break;        case DDP_SCENARIO_SUB_DISP:         case DDP_SCENARIO_SUB_RDMA1_DISP:        case DDP_SCENARIO_SUB_OVL_MEMOUT:        case DDP_SCENARIO_SUB_ALL:            on_primary = 0;            break;			        default:            DDPMSG("invalid scenario id=%d/n", scenario);	      }   return on_primary;}

static int RDMADeInit(DISP_MODULE_ENUM module,void * handle){    unsigned int idx = rdma_index(module);    DDPMSG("RDMA%dDeinit/n",idx);    ddp_disable_module_clock(module);    return 0;}

static int RDMAInit(DISP_MODULE_ENUM module,void * handle){    unsigned int idx = rdma_index(module);    ddp_enable_module_clock(module);    DDPMSG("RDMA%dInit CG 0x%x /n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));     return 0;}

static int RDMAPollingInterrupt(DISP_MODULE_ENUM module, int bit, int timeout){    unsigned int idx = rdma_index(module);    unsigned int cnt  = 0;	unsigned int regval = 0;    if( timeout <= 0)    {        while((DISP_REG_GET(idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS) & bit)==0);        cnt = 1;    }    else    {        // time need to update        cnt = timeout*1000/100;        while(cnt > 0)        {            cnt--;		regval = DISP_REG_GET(idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS);            if(regval  & bit )            {            	DISP_CPU_REG_SET(idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS, ~regval);               break;            }            udelay(100);        }    }    //should clear?    DDPMSG(" RDMA%d polling interrupt ret =%d /n", idx, cnt);    return cnt;}

static unsigned int is_reg_addr_valid(unsigned int isVa, unsigned long addr){	unsigned int i = 0;	for (i = 0; i < DISP_REG_NUM; i++) {		if ((isVa == 1) && (addr >= dispsys_reg[i])		    && (addr <= dispsys_reg[i] + 0x1000))			break;		if ((isVa == 0) && (addr >= ddp_reg_pa_base[i])		    && (addr <= ddp_reg_pa_base[i] + 0x1000))			break;	}	if (i < DISP_REG_NUM) {		DDPMSG("addr valid, isVa=0x%x, addr=0x%lx, module=%s!/n", isVa,		       addr, ddp_get_reg_module_name(i));		return 1;	} else {		DDPERR		    ("is_reg_addr_valid return fail, isVa=0x%x, addr=0x%lx!/n",		     isVa, addr);		return 0;	}}

int  ddp_remove_module(DDP_SCENARIO_ENUM ddp_scenario, DISP_MODULE_ENUM module){    int i = 0;    int idx = ddp_find_module_index(ddp_scenario,module);    if( idx < 0)    {       DDPERR("ddp_remove_module, can not find module %s in scenario %s/n", ddp_get_module_name(module), ddp_get_scenario_name(ddp_scenario));       return -1;    }        for(i=idx; i<DDP_ENING_NUM-1; i++)    {        module_list_scenario[ddp_scenario][i] = module_list_scenario[ddp_scenario][i+1];    }    module_list_scenario[ddp_scenario][DDP_ENING_NUM-1] = -1;    {                int * modules = ddp_get_scenario_list(ddp_scenario);         int module_num = ddp_get_module_num(ddp_scenario);          DDPMSG("after remove module, module list is: /n");         for(i=0;i<module_num;i++)        {               printk("%s-", ddp_get_module_name(modules[i]));        }    }        return 0;}

static void ovl_store_regs(DISP_MODULE_ENUM module){	int i = 0;	int idx = ovl_index(module);    unsigned int idx_offset = idx*DISP_OVL_INDEX_OFFSET;#if 0	static const unsigned long regs[] = {		DISP_REG_OVL_ROI_SIZE, DISP_REG_OVL_ROI_BGCLR,	};#else		static unsigned long regs[3];	regs[0] = DISP_REG_OVL_ROI_SIZE + idx_offset;	regs[1] = DISP_REG_OVL_ROI_BGCLR + idx_offset;    regs[2] = DISP_REG_OVL_DATAPATH_CON + idx_offset;#endif	reg_back_cnt[idx] = sizeof(regs)/sizeof(unsigned long);	ASSERT(reg_back_cnt[idx]  <= OVL_REG_BACK_MAX);	for (i = 0; i < reg_back_cnt[idx]; i++) {		reg_back[idx][i].address = regs[i];		reg_back[idx][i].value   = DISP_REG_GET(regs[i]);	}	DDPMSG("store %d cnt registers on ovl %d/n", reg_back_cnt[idx], idx);}

int ddp_get_module_max_irq_bit(DISP_MODULE_ENUM module){    switch(module)    {        case DISP_MODULE_AAL    :    return 1;        case DISP_MODULE_COLOR0 :    return 2;        case DISP_MODULE_COLOR1 :    return 2;        case DISP_MODULE_RDMA0  :    return 5;        case DISP_MODULE_RDMA1  :    return 5;        case DISP_MODULE_RDMA2  :    return 5;        case DISP_MODULE_WDMA0  :    return 1;        case DISP_MODULE_OVL0   :    return 3;        case DISP_MODULE_GAMMA  :    return 0;        case DISP_MODULE_PWM0   :    return 0;        case DISP_MODULE_PWM1   :    return 0;        case DISP_MODULE_OD     :    return 0;        case DISP_MODULE_MERGE  :    return 0;        case DISP_MODULE_SPLIT0 :    return 0;        case DISP_MODULE_SPLIT1 :    return 0;        case DISP_MODULE_DSI0   :    return 6;        case DISP_MODULE_DSI1   :    return 6;        case DISP_MODULE_DSIDUAL:    return 6;        case DISP_MODULE_DPI    :    return 2;        case DISP_MODULE_SMI    :    return 0;        case DISP_MODULE_CONFIG :    return 0;        case DISP_MODULE_CMDQ   :    return 0;        case DISP_MODULE_MUTEX  :    return 14;        case DISP_MODULE_CCORR  :    return 0;        case DISP_MODULE_DITHER :    return 0;        default:             DDPMSG("invalid module id=%d", module);    }    return 0;}

static int ufoe_reset(DISP_MODULE_ENUM module, void *handle){	DISP_REG_SET_FIELD(handle, START_FLD_DISP_UFO_SW_RST_ENGINE, DISP_REG_UFO_START, 1);	DISP_REG_SET_FIELD(handle, START_FLD_DISP_UFO_SW_RST_ENGINE, DISP_REG_UFO_START, 0);	 DDPMSG("ufoe reset done/n");	return 0;}

void  OVLDeInit(DISP_MODULE_ENUM module,void * handle){    int idx = ovl_index(module);    DDPMSG("OVL%dDeInit close CG /n",idx);    ddp_disable_module_clock(module);	return;}

/* set ovl1 status */void ovl_set_status(DISP_OVL1_STATUS status){	DDPMSG("cascade, set_ovl1 from %s to %s!/n", ovl_get_status_name(ovl1_status),	       ovl_get_status_name(status));	MMProfileLogEx(ddp_mmp_get_events()->ovl1_status, MMProfileFlagPulse, ovl1_status, status);	ovl1_status = status;	/* atomic operation */}

char* ddp_get_reg_module_name(DISP_MODULE_ENUM module){    switch(module)    {        case DISP_REG_OVL0      : return "ovl0";        case DISP_REG_RDMA0     : return "rdma0";        case DISP_REG_RDMA1     : return "rdma1";        case DISP_REG_WDMA0     : return "wdma0";        case DISP_REG_COLOR     : return "color";        case DISP_REG_CCORR     : return "ccorr";        case DISP_REG_AAL       : return "aal";        case DISP_REG_GAMMA     : return "gamma";        case DISP_REG_DITHER    : return "dither";        case DISP_REG_PWM       : return "pwm";        case DISP_REG_MUTEX     : return "mutex";        case DISP_REG_DSI0      : return "dsi0";        case DISP_REG_DPI0      : return "dpi0";        case DISP_REG_CONFIG    : return "config";        case DISP_REG_SMI_LARB0 : return "smi_larb0";        case DISP_REG_SMI_COMMON: return "smi_common";		case DISP_REG_MIPI      : return "mipi";        default:             DDPMSG("invalid module id=%d", module);             return "unknown";    	    }}

void  OVLClockOn(DISP_MODULE_ENUM module,void * handle){    int idx = ovl_index(module);     ddp_enable_module_clock(module);    DDPMSG("OVL%dClockOn CG 0x%x /n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0)); 	return;}

char* ddp_get_scenario_name(DDP_SCENARIO_ENUM scenario){    switch(scenario)    {        case DDP_SCENARIO_PRIMARY_DISP                 : return "primary_disp";        case DDP_SCENARIO_PRIMARY_RDMA0_COLOR0_DISP    : return "primary_rdma0_color_disp";        case DDP_SCENARIO_PRIMARY_RDMA0_DISP           : return "primary_rdma0_disp";        case DDP_SCENARIO_PRIMARY_BYPASS_RDMA          : return "primary_bypass_rdma";                case DDP_SCENARIO_PRIMARY_OVL_MEMOUT           : return "primary_ovl_memout";        case DDP_SCENARIO_PRIMARY_OD_MEMOUT            : return "primary_od_memout";         case DDP_SCENARIO_PRIMARY_UFOE_MEMOUT          : return "primary_ufoe_memout";        case DDP_SCENARIO_SUB_DISP                     : return "sub_disp";        case DDP_SCENARIO_SUB_RDMA1_DISP               : return "sub_rdma1_disp";        case DDP_SCENARIO_SUB_RDMA2_DISP               : return "sub_rdma2_disp";              case DDP_SCENARIO_SUB_OVL_MEMOUT               : return "sub_ovl_memout";        case DDP_SCENARIO_SUB_GAMMA_MEMOUT             : return "sub_gamma_memout";        case DDP_SCENARIO_DISP                         : return "disp";          case DDP_SCENARIO_RDMA0_DUAL_DISP              : return "rmda0_dual_disp";        case DDP_SCENARIO_PRIMARY_ALL                  : return "primary_all";        case DDP_SCENARIO_SUB_ALL                      : return "sub_all";                   default:             DDPMSG("invalid scenario id=%d", scenario);             return "unknown";    	    }}

void  OVLInit(DISP_MODULE_ENUM module,void * handle){    //power on, no need to care clock     int idx = ovl_index(module);     ddp_enable_module_clock(module);    DDPMSG("OVL%dInit open CG 0x%x /n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0)); 	return;}

void disp_rdma_enable_preultra(unsigned int enable){    if(enable==1)        rdma_ultra = rdma_ultra_high;    else        rdma_ultra = rdma_ultra_low;            DDPMSG("rdma_ultra set to 0x%x. /n", rdma_ultra);}

void ddp_mmp_init(void){#ifdef DEFAULT_MMP_ENABLE    DDPMSG("ddp_mmp_init/n");    MMProfileEnable(1);    init_ddp_mmp_events();    MMProfileStart(1);#endif}

int ufoe_start(DISP_MODULE_ENUM module, void* cmdq){	if(ufoe_enable)	{		DISP_REG_SET_FIELD(cmdq, START_FLD_DISP_UFO_START, DISP_REG_UFO_START, 1);	}	DDPMSG("ufoe_start, ufoe_start:0x%x/n", DISP_REG_GET(DISP_REG_UFO_START));	return 0;}

static int rdma_deinit(DISP_MODULE_ENUM module,void * handle){    unsigned int idx = rdma_index(module);#ifdef ENABLE_CLK_MGR    disable_clock(MT_CG_DISP0_DISP_RDMA0+idx , "DDP");#endif    DDPMSG("rdma%d_deinit CG 0x%x /n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));        return 0;}

static void ddp_print_scenario(DDP_SCENARIO_ENUM scenario){    int i =0;    char path[512]={'/0'};    int num = ddp_get_module_num(scenario);    for(i=0; i< num; i++)    {        strcat(path,ddp_get_module_name(module_list_scenario[scenario][i]));    }    DDPMSG("scenario %s have modules: %s/n",ddp_get_scenario_name(scenario),path);}

char* ddp_get_mode_name(DDP_MODE ddp_mode){    switch(ddp_mode)    {        case DDP_VIDEO_MODE  :    return "vido_mode";        case DDP_CMD_MODE    :    return "cmd_mode";        default:             DDPMSG("invalid ddp mode =%d/n", ddp_mode);             return "unknown";    	    }}

static void ovl_restore_regs(DISP_MODULE_ENUM module, void *handle){	int idx = ovl_index(module);	int i = reg_back_cnt[idx];	while (i > 0) {		i--;		DISP_REG_SET(handle, reg_back[idx][i].address,			reg_back[idx][i].value);	}	DDPMSG("restore %d cnt registers on ovl %d/n", reg_back_cnt[idx], idx);	reg_back_cnt[idx] = 0;}

int  ovl_resume(DISP_MODULE_ENUM module, void *handle){	int idx = ovl_index(module);	DDPMSG("ovl%d_resume/n", idx);#ifdef ENABLE_CLK_MGR    if(idx == 0){        enable_clock(MT_CG_DISP0_DISP_OVL0, "OVL0");    }#endif	ovl_restore_regs(module, handle);	return 0;}

static void ufoe_dump(void){	DDPMSG("==DISP UFOE REGS==/n");	DDPMSG("(0x000)UFOE_START =0x%x/n", DISP_REG_GET(DISP_REG_UFO_START));	DDPMSG("(0x000)UFOE_CFG0 =0x%x/n", DISP_REG_GET(DISP_REG_UFO_CFG_0B));	DDPMSG("(0x000)UFOE_CFG1 =0x%x/n", DISP_REG_GET(DISP_REG_UFO_CFG_1B));	DDPMSG("(0x000)UFOE_WIDTH =0x%x/n", DISP_REG_GET(DISP_REG_UFO_FRAME_WIDTH));	DDPMSG("(0x000)UFOE_HEIGHT =0x%x/n", DISP_REG_GET(DISP_REG_UFO_FRAME_HEIGHT));	DDPMSG("(0x000)UFOE_PAD  =0x%x/n", DISP_REG_GET(DISP_REG_UFO_CR0P6_PAD));}

void  OVLClockOff(DISP_MODULE_ENUM module,void * handle){    int idx = ovl_index(module);    DDPMSG("OVL%dClockOff/n",idx);	//store registers   // OVLRegRestore(module,handle);    DISP_REG_SET(handle, idx * DISP_INDEX_OFFSET + DISP_REG_OVL_EN, 0x00);    OVLReset(module,handle);    DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+DISP_REG_OVL_INTEN, 0x00);    DISP_REG_SET(handle, idx * DISP_INDEX_OFFSET + DISP_REG_OVL_INTSTA, 0x00);    ddp_disable_module_clock(module);	return;}