自学教程：C++ EFX_SET_OWORD_FIELD函数代码示例

static int sfn4111t_reset(struct efx_nic *efx){	struct falcon_board *board = falcon_board(efx);	efx_oword_t reg;	/* GPIO 3 and the GPIO register are shared with I2C, so block that */	i2c_lock_adapter(&board->i2c_adap);	/* Pull RST_N (GPIO 2) low then let it up again, setting the	 * FLASH_CFG_1 strap (GPIO 3) appropriately.  Only change the	 * output enables; the output levels should always be 0 (low)	 * and we rely on external pull-ups. */	efx_reado(efx, &reg, FR_AB_GPIO_CTL);	EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, true);	efx_writeo(efx, &reg, FR_AB_GPIO_CTL);	msleep(1000);	EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, false);	EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN,			    !!(efx->phy_mode & PHY_MODE_SPECIAL));	efx_writeo(efx, &reg, FR_AB_GPIO_CTL);	msleep(1);	i2c_unlock_adapter(&board->i2c_adap);	ssleep(1);	return 0;}

	__checkReturn	intefx_intr_init(	__in		efx_nic_t *enp,	__in		efx_intr_type_t type,	__in		efsys_mem_t *esmp){	efx_intr_t *eip = &(enp->en_intr);	efx_oword_t oword;	int rc;	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);	if (enp->en_mod_flags & EFX_MOD_INTR) {		rc = EINVAL;		goto fail1;	}	enp->en_mod_flags |= EFX_MOD_INTR;	eip->ei_type = type;	eip->ei_esmp = esmp;	/*	 * bug17213 workaround.	 *	 * Under legacy interrupts, don't share a level between fatal	 * interrupts and event queue interrupts. Under MSI-X, they	 * must share, or we won't get an interrupt.	 */	if (enp->en_family == EFX_FAMILY_SIENA &&	    eip->ei_type == EFX_INTR_LINE)		eip->ei_level = 0x1f;	else		eip->ei_level = 0;	/* Enable all the genuinely fatal interrupts */	EFX_SET_OWORD(oword);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0);	if (enp->en_family >= EFX_FAMILY_SIENA)		EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0);	EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword);	/* Set up the interrupt address register */	EFX_POPULATE_OWORD_3(oword,	    FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0,	    FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff,	    FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32);	EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);	return (0);fail1:	EFSYS_PROBE1(fail1, int, rc);	return (rc);}

static void falcon_reset_macs(struct efx_nic *efx){	struct falcon_nic_data *nic_data = efx->nic_data;	efx_oword_t reg, mac_ctrl;	int count;	if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {		EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);		efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);		for (count = 0; count < 10000; count++) {			efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);			if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==			    0)				return;			udelay(10);		}		netif_err(efx, hw, efx->net_dev,			  "timed out waiting for XMAC core reset/n");	}		WARN_ON(nic_data->stats_disable_count == 0);	efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);	EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);	efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);	efx_reado(efx, &reg, FR_AB_GLB_CTL);	EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);	EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);	EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);	efx_writeo(efx, &reg, FR_AB_GLB_CTL);	count = 0;	while (1) {		efx_reado(efx, &reg, FR_AB_GLB_CTL);		if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&		    !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&		    !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {			netif_dbg(efx, hw, efx->net_dev,				  "Completed MAC reset after %d loops/n",				  count);			break;		}		if (count > 20) {			netif_err(efx, hw, efx->net_dev, "MAC reset failed/n");			break;		}		count++;		udelay(10);	}	efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);	falcon_setup_xaui(efx);}

static	__checkReturn	efx_rc_tsiena_intr_trigger(	__in		efx_nic_t *enp,	__in		unsigned int level){	efx_intr_t *eip = &(enp->en_intr);	efx_oword_t oword;	unsigned int count;	uint32_t sel;	efx_rc_t rc;	/* bug16757: No event queues can be initialized */	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));	if (level >= EFX_NINTR_SIENA) {		rc = EINVAL;		goto fail1;	}	if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL))		return (ENOTSUP); /* avoid EFSYS_PROBE() */	sel = level;	/* Trigger a test interrupt */	EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, sel);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER, 1);	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);	/*	 * Wait up to 100ms for the interrupt to be raised before restoring	 * KER_INT_LEVE_SEL. Ignore a failure to raise (the caller will	 * observe this soon enough anyway), but always reset KER_INT_LEVE_SEL	 */	count = 0;	do {		EFSYS_SPIN(100);	/* 100us */		EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);	} while (EFX_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER) && ++count < 1000);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);	return (0);fail1:	EFSYS_PROBE1(fail1, efx_rc_t, rc);	return (rc);}

static			voidsiena_intr_enable(	__in		efx_nic_t *enp){	efx_intr_t *eip = &(enp->en_intr);	efx_oword_t oword;	EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1);	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);}

/* Configure the XAUI driver that is an output from Falcon */void falcon_setup_xaui(struct efx_nic *efx){	efx_oword_t sdctl, txdrv;	/* Move the XAUI into low power, unless there is no PHY, in	 * which case the XAUI will have to drive a cable. */	if (efx->phy_type == PHY_TYPE_NONE)		return;	efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);	efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);	EFX_POPULATE_OWORD_8(txdrv,			     FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,			     FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,			     FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,			     FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,			     FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,			     FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,			     FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,			     FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);	efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);}

/* Configure the XAUI driver that is an output from Falcon */static void falcon_setup_xaui(struct efx_nic *efx){	efx_oword_t sdctl, txdrv;	/* Move the XAUI into low power, unless there is no PHY, in	 * which case the XAUI will have to drive a cable. */	if (efx->phy_type == PHY_TYPE_NONE)		return;	falcon_read(efx, &sdctl, XX_SD_CTL_REG);	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);	falcon_write(efx, &sdctl, XX_SD_CTL_REG);	EFX_POPULATE_OWORD_8(txdrv,			     XX_DEQD, XX_TXDRV_DEQ_DEFAULT,			     XX_DEQC, XX_TXDRV_DEQ_DEFAULT,			     XX_DEQB, XX_TXDRV_DEQ_DEFAULT,			     XX_DEQA, XX_TXDRV_DEQ_DEFAULT,			     XX_DTXD, XX_TXDRV_DTX_DEFAULT,			     XX_DTXC, XX_TXDRV_DTX_DEFAULT,			     XX_DTXB, XX_TXDRV_DTX_DEFAULT,			     XX_DTXA, XX_TXDRV_DTX_DEFAULT);	falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG);}

			voidefx_intr_enable(	__in		efx_nic_t *enp){	efx_intr_t *eip = &(enp->en_intr);	efx_oword_t oword;	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);	EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1);	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);}

void falcon_reconfigure_mac_wrapper(struct efx_nic *efx){	struct efx_link_state *link_state = &efx->link_state;	efx_oword_t reg;	int link_speed, isolate;	isolate = !!ACCESS_ONCE(efx->reset_pending);	switch (link_state->speed) {	case 10000: link_speed = 3; break;	case 1000:  link_speed = 2; break;	case 100:   link_speed = 1; break;	default:    link_speed = 0; break;	}	/* MAC_LINK_STATUS controls MAC backpressure but doesn't work	 * as advertised.  Disable to ensure packets are not	 * indefinitely held and TX queue can be flushed at any point	 * while the link is down. */	EFX_POPULATE_OWORD_5(reg,			     FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,			     FRF_AB_MAC_BCAD_ACPT, 1,			     FRF_AB_MAC_UC_PROM, efx->promiscuous,			     FRF_AB_MAC_LINK_STATUS, 1, /* always set */			     FRF_AB_MAC_SPEED, link_speed);	/* On B0, MAC backpressure can be disabled and packets get	 * discarded. */	if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {		EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,				    !link_state->up || isolate);	}	efx_writeo(efx, &reg, FR_AB_MAC_CTRL);	/* Restore the multicast hash registers. */	falcon_push_multicast_hash(efx);	efx_reado(efx, &reg, FR_AZ_RX_CFG);	/* Enable XOFF signal from RX FIFO (we enabled it during NIC	 * initialisation but it may read back as 0) */	EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);	/* Unisolate the MAC -> RX */	if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);	efx_writeo(efx, &reg, FR_AZ_RX_CFG);}

static void falcon_setscl(void *data, int state){	struct efx_nic *efx = (struct efx_nic *)data;	efx_oword_t reg;	efx_reado(efx, &reg, FR_AB_GPIO_CTL);	EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);	efx_writeo(efx, &reg, FR_AB_GPIO_CTL);}

/* This call performs hardware-specific global initialisation, such as * defining the descriptor cache sizes and number of RSS channels. * It does not set up any buffers, descriptor rings or event queues. */static int siena_init_nic(struct efx_nic *efx){	efx_oword_t temp;	int rc;	/* Recover from a failed assertion post-reset */	rc = efx_mcdi_handle_assertion(efx);	if (rc)		return rc;	/* Squash TX of packets of 16 bytes or less */	efx_reado(efx, &temp, FR_AZ_TX_RESERVED);	EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);	efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);	/* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16	 * descriptors (which is bad).	 */	efx_reado(efx, &temp, FR_AZ_TX_CFG);	EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);	EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);	efx_writeo(efx, &temp, FR_AZ_TX_CFG);	efx_reado(efx, &temp, FR_AZ_RX_CFG);	EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);	EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);	/* Enable hash insertion. This is broken for the 'Falcon' hash	 * if IPv6 hashing is also enabled, so also select Toeplitz	 * TCP/IPv4 and IPv4 hashes. */	EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);	EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);	EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);	EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,			    EFX_RX_USR_BUF_SIZE >> 5);	efx_writeo(efx, &temp, FR_AZ_RX_CFG);	siena_rx_push_rss_config(efx, false, efx->rss_context.rx_indir_table, NULL);	efx->rss_context.context_id = 0; /* indicates RSS is active */	/* Enable event logging */	rc = efx_mcdi_log_ctrl(efx, true, false, 0);	if (rc)		return rc;	/* Set destination of both TX and RX Flush events */	EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);	efx_writeo(efx, &temp, FR_BZ_DP_CTRL);	EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);	efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);	efx_farch_init_common(efx);	return 0;}

static void falcon_init_rx_cfg(struct efx_nic *efx){	const unsigned huge_buf_size = (3 * 4096) >> 5;		const unsigned ctrl_xon_thr = 20;	const unsigned ctrl_xoff_thr = 25;	efx_oword_t reg;	efx_reado(efx, &reg, FR_AZ_RX_CFG);	if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {				EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,				    huge_buf_size);		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);	} else {

static void falcon_clock_mac(struct efx_nic *efx){	unsigned strap_val;	efx_oword_t nic_stat;	/* Configure the NIC generated MAC clock correctly */	efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);	strap_val = EFX_IS10G(efx) ? 5 : 3;	if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {		EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);		EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);		efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);	} else {		/* Falcon A1 does not support 1G/10G speed switching		 * and must not be used with a PHY that does. */		BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=		       strap_val);	}}

static			voidsiena_nic_rx_cfg(	__in		efx_nic_t *enp){	efx_oword_t oword;	/*	 * RX_INGR_EN is always enabled on Siena, because we rely on	 * the RX parser to be resiliant to missing SOP/EOP.	 */	EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);	EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);	EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);	/* Disable parsing of additional 802.1Q in Q packets */	EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);	EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);	EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);}

static			voidsiena_intr_disable(	__in		efx_nic_t *enp){	efx_oword_t oword;	EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);	EFSYS_SPIN(10);}

static			voidsiena_intr_disable_unlocked(	__in		efx_nic_t *enp){	efx_oword_t oword;	EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,			&oword, B_FALSE);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);	EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,	    &oword, B_FALSE);}

static	__checkReturn	efx_rc_tsiena_intr_init(	__in		efx_nic_t *enp,	__in		efx_intr_type_t type,	__in		efsys_mem_t *esmp){	efx_intr_t *eip = &(enp->en_intr);	efx_oword_t oword;	/*	 * bug17213 workaround.	 *	 * Under legacy interrupts, don't share a level between fatal	 * interrupts and event queue interrupts. Under MSI-X, they	 * must share, or we won't get an interrupt.	 */	if (enp->en_family == EFX_FAMILY_SIENA &&	    eip->ei_type == EFX_INTR_LINE)		eip->ei_level = 0x1f;	else		eip->ei_level = 0;	/* Enable all the genuinely fatal interrupts */	EFX_SET_OWORD(oword);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0);	if (enp->en_family >= EFX_FAMILY_SIENA)		EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0);	EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword);	/* Set up the interrupt address register */	EFX_POPULATE_OWORD_3(oword,	    FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0,	    FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff,	    FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32);	EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);	return (0);}

static void falcon_init_rx_cfg(struct efx_nic *efx){	/* Prior to Siena the RX DMA engine will split each frame at	 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to	 * be so large that that never happens. */	const unsigned huge_buf_size = (3 * 4096) >> 5;	/* RX control FIFO thresholds (32 entries) */	const unsigned ctrl_xon_thr = 20;	const unsigned ctrl_xoff_thr = 25;	/* RX data FIFO thresholds (256-byte units; size varies) */	int data_xon_thr = efx_nic_rx_xon_thresh >> 8;	int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;	efx_oword_t reg;	efx_reado(efx, &reg, FR_AZ_RX_CFG);	if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {		/* Data FIFO size is 5.5K */		if (data_xon_thr < 0)			data_xon_thr = 512 >> 8;		if (data_xoff_thr < 0)			data_xoff_thr = 2048 >> 8;		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,				    huge_buf_size);		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);		EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);	} else {		/* Data FIFO size is 80K; register fields moved */		if (data_xon_thr < 0)

static bool falcon_xgxs_link_ok(struct efx_nic *efx){	efx_oword_t reg;	bool align_done, link_ok = false;	int sync_status;	/* Read link status */	efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);	align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);	sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);	if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))		link_ok = true;	/* Clear link status ready for next read */	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);	efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);	return link_ok;}

/* Zeroes out the SRAM contents.  This routine must be called in * process context and is allowed to sleep. */static int falcon_reset_sram(struct efx_nic *efx){	efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;	int count;	/* Set the SRAM wake/sleep GPIO appropriately. */	efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);	EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);	EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);	efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);	/* Initiate SRAM reset */	EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,			     FRF_AZ_SRM_INIT_EN, 1,			     FRF_AZ_SRM_NB_SZ, 0);	efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);	/* Wait for SRAM reset to complete */	count = 0;	do {		netif_dbg(efx, hw, efx->net_dev,			  "waiting for SRAM reset (attempt %d).../n", count);		/* SRAM reset is slow; expect around 16ms */		schedule_timeout_uninterruptible(HZ / 50);		/* Check for reset complete */		efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);		if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {			netif_dbg(efx, hw, efx->net_dev,				  "SRAM reset complete/n");			return 0;		}	} while (++count < 20);	/* wait up to 0.4 sec */	netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset/n");	return -ETIMEDOUT;}

static int falcon_reset_sram(struct efx_nic *efx){	efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;	int count;		efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);	EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);	EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);	efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);		EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,			     FRF_AZ_SRM_INIT_EN, 1,			     FRF_AZ_SRM_NB_SZ, 0);	efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);		count = 0;	do {		netif_dbg(efx, hw, efx->net_dev,			  "waiting for SRAM reset (attempt %d).../n", count);				schedule_timeout_uninterruptible(HZ / 50);				efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);		if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {			netif_dbg(efx, hw, efx->net_dev,				  "SRAM reset complete/n");			return 0;		}	} while (++count < 20);		netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset/n");	return -ETIMEDOUT;}

bool falcon_xaui_link_ok(struct efx_nic *efx){	efx_oword_t reg;	bool align_done, link_ok = false;	int sync_status;	if (LOOPBACK_INTERNAL(efx))		return true;	/* Read link status */	falcon_read(efx, &reg, XX_CORE_STAT_REG);	align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE);	sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT);	if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))		link_ok = true;	/* Clear link status ready for next read */	EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);	EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);	EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);	falcon_write(efx, &reg, XX_CORE_STAT_REG);	/* If the link is up, then check the phy side of the xaui link	 * (error conditions from the wire side propoagate back through	 * the phy to the xaui side). */	if (efx->link_up && link_ok) {		if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))			link_ok = mdio_clause45_phyxgxs_lane_sync(efx);	}	/* If the PHY and XAUI links are up, then check the mac's xgmii	 * fault state */	if (efx->link_up && link_ok)		link_ok = falcon_xgmii_status(efx);	return link_ok;}

void falcon_reconfigure_mac_wrapper(struct efx_nic *efx){	struct efx_link_state *link_state = &efx->link_state;	efx_oword_t reg;	int link_speed, isolate;	isolate = !!ACCESS_ONCE(efx->reset_pending);	switch (link_state->speed) {	case 10000: link_speed = 3; break;	case 1000:  link_speed = 2; break;	case 100:   link_speed = 1; break;	default:    link_speed = 0; break;	}	EFX_POPULATE_OWORD_5(reg,			     FRF_AB_MAC_XOFF_VAL, 0xffff ,			     FRF_AB_MAC_BCAD_ACPT, 1,			     FRF_AB_MAC_UC_PROM, efx->promiscuous,			     FRF_AB_MAC_LINK_STATUS, 1, 			     FRF_AB_MAC_SPEED, link_speed);	if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {		EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,				    !link_state->up || isolate);	}	efx_writeo(efx, &reg, FR_AB_MAC_CTRL);		falcon_push_multicast_hash(efx);	efx_reado(efx, &reg, FR_AZ_RX_CFG);	EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);		if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)		EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);	efx_writeo(efx, &reg, FR_AZ_RX_CFG);}

			voidefx_intr_disable(	__in		efx_nic_t *enp){	efx_oword_t oword;	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);	EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);	EFSYS_SPIN(10);}

			voidefx_intr_disable_unlocked(	__in		efx_nic_t *enp){	efx_oword_t oword;	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);	EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,			&oword, B_FALSE);	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);	EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,	    &oword, B_FALSE);}

static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx){	efx_oword_t reg;	if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)		return;		efx_reado(efx, &reg, FR_AZ_RX_CFG);	EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);	efx_writeo(efx, &reg, FR_AZ_RX_CFG);		falcon_drain_tx_fifo(efx);}