自学教程：C++ GET_CODE函数代码示例

static booltransform_ifelse (ext_cand *cand, rtx def_insn){  rtx set_insn = PATTERN (def_insn);  rtx srcreg, dstreg, srcreg2;  rtx map_srcreg, map_dstreg, map_srcreg2;  rtx ifexpr;  rtx cond;  rtx new_set;  gcc_assert (GET_CODE (set_insn) == SET);  cond = XEXP (SET_SRC (set_insn), 0);  dstreg = SET_DEST (set_insn);  srcreg = XEXP (SET_SRC (set_insn), 1);  srcreg2 = XEXP (SET_SRC (set_insn), 2);  /* If the conditional move already has the right or wider mode,     there is nothing to do.  */  if (GET_MODE_SIZE (GET_MODE (dstreg)) >= GET_MODE_SIZE (cand->mode))    return true;  map_srcreg = gen_rtx_REG (cand->mode, REGNO (srcreg));  map_srcreg2 = gen_rtx_REG (cand->mode, REGNO (srcreg2));  map_dstreg = gen_rtx_REG (cand->mode, REGNO (dstreg));  ifexpr = gen_rtx_IF_THEN_ELSE (cand->mode, cond, map_srcreg, map_srcreg2);  new_set = gen_rtx_SET (VOIDmode, map_dstreg, ifexpr);  if (validate_change (def_insn, &PATTERN (def_insn), new_set, true))    {      if (dump_file)        {          fprintf (dump_file,		   "Mode of conditional move instruction extended:/n");          print_rtl_single (dump_file, def_insn);        }      return true;    }  return false;}

boolrtvec_all_equal_p (const_rtvec vec){  const_rtx first = RTVEC_ELT (vec, 0);  /* Optimize the important special case of a vector of constants.     The main use of this function is to detect whether every element     of CONST_VECTOR is the same.  */  switch (GET_CODE (first))    {    CASE_CONST_UNIQUE:      for (int i = 1, n = GET_NUM_ELEM (vec); i < n; ++i)	if (first != RTVEC_ELT (vec, i))	  return false;      return true;    default:      for (int i = 1, n = GET_NUM_ELEM (vec); i < n; ++i)	if (!rtx_equal_p (first, RTVEC_ELT (vec, i)))	  return false;      return true;    }}

static intrecord_stack_memrefs (rtx *xp, void *data){  rtx x = *xp;  struct record_stack_memrefs_data *d =    (struct record_stack_memrefs_data *) data;  if (!x)    return 0;  switch (GET_CODE (x))    {    case MEM:      if (!reg_mentioned_p (stack_pointer_rtx, x))	return -1;      /* We are not able to handle correctly all possible memrefs containing         stack pointer, so this check is necessary.  */      if (stack_memref_p (x))	{	  d->memlist = record_one_stack_memref (d->insn, xp, d->memlist);	  return -1;	}      return 1;    case REG:      /* ??? We want be able to handle non-memory stack pointer	 references later.  For now just discard all insns referring to	 stack pointer outside mem expressions.  We would probably	 want to teach validate_replace to simplify expressions first.	 We can't just compare with STACK_POINTER_RTX because the	 reference to the stack pointer might be in some other mode.	 In particular, an explicit clobber in an asm statement will	 result in a QImode clobber.  */      if (REGNO (x) == STACK_POINTER_REGNUM)	return 1;      break;    default:      break;    }  return 0;}

/* Callback function for arm_find_sub_rtx_with_code.   DATA is safe to treat as a SEARCH_TERM, ST.  This will   hold a SEARCH_CODE.  PATTERN is checked to see if it is an   RTX with that code.  If it is, write SEARCH_RESULT in ST   and return 1.  Otherwise, or if we have been passed a NULL_RTX   return 0.  If ST.FIND_ANY_SHIFT then we are interested in   anything which can reasonably be described as a SHIFT RTX.  */static intarm_find_sub_rtx_with_search_term (rtx *pattern, void *data){  search_term *st = (search_term *) data;  rtx_code pattern_code;  int found = 0;  gcc_assert (pattern);  gcc_assert (st);  /* Poorly formed patterns can really ruin our day.  */  if (*pattern == NULL_RTX)    return 0;  pattern_code = GET_CODE (*pattern);  if (st->find_any_shift)    {      unsigned i = 0;      /* Left shifts might have been canonicalized to a MULT of some	 power of two.  Make sure we catch them.  */      if (arm_rtx_shift_left_p (*pattern))	found = 1;      else	for (i = 0; i < ARRAY_SIZE (shift_rtx_codes); i++)	  if (pattern_code == shift_rtx_codes[i])	    found = 1;    }  if (pattern_code == st->search_code)    found = 1;  if (found)    st->search_result = *pattern;  return found;}

/* legitimate_address_p returns 1 if it recognizes an RTL expression "x"   that is a valid memory address for an instruction.   The MODE argument is the machine mode for the MEM expression   that wants to use this address.  */intlegitimate_address_p (enum machine_mode mode, rtx x, int strict){  rtx xfoo0, xfoo1;  if (nonindexed_address_p (x, strict))    return 1;  if (GET_CODE (x) != PLUS)    return 0;  /* Handle <address>[index] represented with index-sum outermost */  xfoo0 = XEXP (x, 0);  xfoo1 = XEXP (x, 1);  if (index_term_p (xfoo0, mode, strict)      && nonindexed_address_p (xfoo1, strict))    return 1;  if (index_term_p (xfoo1, mode, strict)      && nonindexed_address_p (xfoo0, strict))    return 1;  /* Handle offset(reg)[index] with offset added outermost */  if (indirectable_constant_address_p (xfoo0)      && (BASE_REGISTER_P (xfoo1, strict)          || reg_plus_index_p (xfoo1, mode, strict)))    return 1;  if (indirectable_constant_address_p (xfoo1)      && (BASE_REGISTER_P (xfoo0, strict)          || reg_plus_index_p (xfoo0, mode, strict)))    return 1;  return 0;}

static inline intix86_comparison_operator_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)#line 1006 "../.././gcc/config/i386/predicates.md"{  enum machine_mode inmode = GET_MODE (XEXP (op, 0));  enum rtx_code code = GET_CODE (op);  if (inmode == CCFPmode || inmode == CCFPUmode)    {      enum rtx_code second_code, bypass_code;      ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);      return (bypass_code == UNKNOWN && second_code == UNKNOWN);    }  switch (code)    {    case EQ: case NE:      return 1;    case LT: case GE:      if (inmode == CCmode || inmode == CCGCmode	  || inmode == CCGOCmode || inmode == CCNOmode)	return 1;      return 0;    case LTU: case GTU: case LEU: case GEU:      if (inmode == CCmode || inmode == CCCmode)	return 1;      return 0;    case ORDERED: case UNORDERED:      if (inmode == CCmode)	return 1;      return 0;    case GT: case LE:      if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)	return 1;      return 0;    default:      return 0;    }}

static rtxconforming_compare (rtx_insn *insn){  rtx set, src, dest;  set = single_set (insn);  if (set == NULL)    return NULL;  src = SET_SRC (set);  if (GET_CODE (src) != COMPARE)    return NULL;  dest = SET_DEST (set);  if (!REG_P (dest) || REGNO (dest) != targetm.flags_regnum)    return NULL;  if (REG_P (XEXP (src, 0))      && (REG_P (XEXP (src, 1)) || CONSTANT_P (XEXP (src, 1))))    return src;  return NULL;}

voidsymtab_make_decl_local (tree decl){  rtx rtl, symbol;  if (TREE_CODE (decl) == VAR_DECL)    DECL_COMMON (decl) = 0;  else gcc_assert (TREE_CODE (decl) == FUNCTION_DECL);  if (DECL_ONE_ONLY (decl) || DECL_COMDAT (decl))    {      DECL_SECTION_NAME (decl) = 0;      DECL_COMDAT (decl) = 0;    }  DECL_COMDAT_GROUP (decl) = 0;  DECL_WEAK (decl) = 0;  DECL_EXTERNAL (decl) = 0;  DECL_VISIBILITY_SPECIFIED (decl) = 0;  DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;  TREE_PUBLIC (decl) = 0;  if (!DECL_RTL_SET_P (decl))    return;  /* Update rtl flags.  */  make_decl_rtl (decl);  rtl = DECL_RTL (decl);  if (!MEM_P (rtl))    return;  symbol = XEXP (rtl, 0);  if (GET_CODE (symbol) != SYMBOL_REF)    return;  SYMBOL_REF_WEAK (symbol) = DECL_WEAK (decl);}

static intuses_addressof (rtx x){  RTX_CODE code;  int i, j;  const char *fmt;  if (x == NULL_RTX)    return 0;  code = GET_CODE (x);  if (code == ADDRESSOF || x == current_function_internal_arg_pointer)    return 1;  if (code == MEM)    return 0;  /* Scan all subexpressions.  */  fmt = GET_RTX_FORMAT (code);  for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)    {      if (*fmt == 'e')	{	  if (uses_addressof (XEXP (x, i)))	    return 1;	}      else if (*fmt == 'E')	{	  for (j = 0; j < XVECLEN (x, i); j++)	    if (uses_addressof (XVECEXP (x, i, j)))	      return 1;	}    }  return 0;}

static struct df_link *get_defs (rtx insn, rtx reg, vec<rtx> *dest){  df_ref reg_info, *uses;  struct df_link *ref_chain, *ref_link;  reg_info = NULL;  for (uses = DF_INSN_USES (insn); *uses; uses++)    {      reg_info = *uses;      if (GET_CODE (DF_REF_REG (reg_info)) == SUBREG)        return NULL;      if (REGNO (DF_REF_REG (reg_info)) == REGNO (reg))        break;    }  gcc_assert (reg_info != NULL && uses != NULL);  ref_chain = DF_REF_CHAIN (reg_info);  for (ref_link = ref_chain; ref_link; ref_link = ref_link->next)    {      /* Problem getting some definition for this instruction.  */      if (ref_link->ref == NULL)        return NULL;      if (DF_REF_INSN_INFO (ref_link->ref) == NULL)        return NULL;    }  if (dest)    for (ref_link = ref_chain; ref_link; ref_link = ref_link->next)      dest->safe_push (DF_REF_INSN (ref_link->ref));  return ref_chain;}

voidprint_rtl (FILE *outf, const_rtx rtx_first){  const_rtx tmp_rtx;  outfile = outf;  sawclose = 0;  if (rtx_first == 0)    {      fputs (print_rtx_head, outf);      fputs ("(nil)/n", outf);    }  else    switch (GET_CODE (rtx_first))      {      case INSN:      case JUMP_INSN:      case CALL_INSN:      case NOTE:      case CODE_LABEL:      case JUMP_TABLE_DATA:      case BARRIER:	for (tmp_rtx = rtx_first; tmp_rtx != 0; tmp_rtx = NEXT_INSN (tmp_rtx))	  {	    fputs (print_rtx_head, outfile);	    print_rtx (tmp_rtx);	    fprintf (outfile, "/n");	  }	break;      default:	fputs (print_rtx_head, outfile);	print_rtx (rtx_first);      }}

//.........这里部分代码省略.........		}	    }	  int smaller_sign = 1;	  int larger_sign = 1;	  if (op0_small_p)	    {	      smaller_sign = op0_sign;	      larger_sign = op1_sign;	    }	  else if (op1_small_p)	    {	      smaller_sign = op1_sign;	      larger_sign = op0_sign;	    }	  else if (op0_sign == op1_sign)	    {	      smaller_sign = op0_sign;	      larger_sign = op0_sign;	    }	  if (!op0_small_p)	    emit_cmp_and_jump_insns (signbit0, hipart0, NE, NULL_RTX, hmode,				     false, large_op0, PROB_UNLIKELY);	  if (!op1_small_p)	    emit_cmp_and_jump_insns (signbit1, hipart1, NE, NULL_RTX, hmode,				     false, small_op0_large_op1,				     PROB_UNLIKELY);	  /* If both op0 and op1 are sign extended from hmode to mode,	     the multiplication will never overflow.  We can do just one	     hmode x hmode => mode widening multiplication.  */	  if (GET_CODE (lopart0) == SUBREG)	    {	      SUBREG_PROMOTED_VAR_P (lopart0) = 1;	      SUBREG_PROMOTED_SET (lopart0, 0);	    }	  if (GET_CODE (lopart1) == SUBREG)	    {	      SUBREG_PROMOTED_VAR_P (lopart1) = 1;	      SUBREG_PROMOTED_SET (lopart1, 0);	    }	  tree halfstype = build_nonstandard_integer_type (hprec, 0);	  ops.op0 = make_tree (halfstype, lopart0);	  ops.op1 = make_tree (halfstype, lopart1);	  ops.code = WIDEN_MULT_EXPR;	  ops.type = TREE_TYPE (arg0);	  rtx thisres	    = expand_expr_real_2 (&ops, NULL_RTX, mode, EXPAND_NORMAL);	  emit_move_insn (res, thisres);	  emit_jump (done_label);	  emit_label (small_op0_large_op1);	  /* If op0 is sign extended from hmode to mode, but op1 is not,	     just swap the arguments and handle it as op1 sign extended,	     op0 not.  */	  rtx larger = gen_reg_rtx (mode);	  rtx hipart = gen_reg_rtx (hmode);	  rtx lopart = gen_reg_rtx (hmode);	  emit_move_insn (larger, op1);	  emit_move_insn (hipart, hipart1);	  emit_move_insn (lopart, lopart0);	  emit_jump (one_small_one_large);

intnds32_address_cost_impl (rtx address,			 enum machine_mode mode ATTRIBUTE_UNUSED,			 addr_space_t as ATTRIBUTE_UNUSED,			 bool speed){  rtx plus0, plus1;  enum rtx_code code;  code = GET_CODE (address);  /* According to 'speed', goto suitable cost model section.  */  if (speed)    goto performance_cost;  else    goto size_cost;performance_cost:  /* This is section for performance cost model.  */  /* FALLTHRU, currently we use same cost model as size_cost.  */size_cost:  /* This is section for size cost model.  */  switch (code)    {    case POST_MODIFY:    case POST_INC:    case POST_DEC:      /* We encourage that rtx contains         POST_MODIFY/POST_INC/POST_DEC behavior.  */      return 0;    case SYMBOL_REF:      /* We can have gp-relative load/store for symbol_ref.         Have it 4-byte cost.  */      return COSTS_N_INSNS (1);    case CONST:      /* It is supposed to be the pattern (const (plus symbol_ref const_int)).         Have it 4-byte cost.  */      return COSTS_N_INSNS (1);    case REG:      /* Simply return 4-byte costs.  */      return COSTS_N_INSNS (1);    case PLUS:      /* We do not need to check if the address is a legitimate address,         because this hook is never called with an invalid address.         But we better check the range of         const_int value for cost, if it exists.  */      plus0 = XEXP (address, 0);      plus1 = XEXP (address, 1);      if (REG_P (plus0) && CONST_INT_P (plus1))        {	  /* If it is possible to be lwi333/swi333 form,	     make it 2-byte cost.  */	  if (satisfies_constraint_Iu05 (plus1))	    return (COSTS_N_INSNS (1) - 2);	  else	    return COSTS_N_INSNS (1);	}      /* For other 'plus' situation, make it cost 4-byte.  */      return COSTS_N_INSNS (1);    default:      break;    }  return COSTS_N_INSNS (4);}

static boolcopyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd){  bool anything_changed = false;  rtx insn;  for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn))    {      int n_ops, i, alt, predicated;      bool is_asm, any_replacements;      rtx set;      bool replaced[MAX_RECOG_OPERANDS];      bool changed = false;      struct kill_set_value_data ksvd;      if (!NONDEBUG_INSN_P (insn))	{	  if (DEBUG_INSN_P (insn))	    {	      rtx loc = INSN_VAR_LOCATION_LOC (insn);	      if (!VAR_LOC_UNKNOWN_P (loc))		replace_oldest_value_addr (&INSN_VAR_LOCATION_LOC (insn),					   ALL_REGS, GET_MODE (loc),					   ADDR_SPACE_GENERIC, insn, vd);	    }	  if (insn == BB_END (bb))	    break;	  else	    continue;	}      set = single_set (insn);      extract_insn (insn);      if (! constrain_operands (1))	fatal_insn_not_found (insn);      preprocess_constraints ();      alt = which_alternative;      n_ops = recog_data.n_operands;      is_asm = asm_noperands (PATTERN (insn)) >= 0;      /* Simplify the code below by rewriting things to reflect	 matching constraints.  Also promote OP_OUT to OP_INOUT	 in predicated instructions.  */      predicated = GET_CODE (PATTERN (insn)) == COND_EXEC;      for (i = 0; i < n_ops; ++i)	{	  int matches = recog_op_alt[i][alt].matches;	  if (matches >= 0)	    recog_op_alt[i][alt].cl = recog_op_alt[matches][alt].cl;	  if (matches >= 0 || recog_op_alt[i][alt].matched >= 0	      || (predicated && recog_data.operand_type[i] == OP_OUT))	    recog_data.operand_type[i] = OP_INOUT;	}      /* Apply changes to earlier DEBUG_INSNs if possible.  */      if (vd->n_debug_insn_changes)	note_uses (&PATTERN (insn), cprop_find_used_regs, vd);      /* For each earlyclobber operand, zap the value data.  */      for (i = 0; i < n_ops; i++)	if (recog_op_alt[i][alt].earlyclobber)	  kill_value (recog_data.operand[i], vd);      /* Within asms, a clobber cannot overlap inputs or outputs.	 I wouldn't think this were true for regular insns, but	 scan_rtx treats them like that...  */      note_stores (PATTERN (insn), kill_clobbered_value, vd);      /* Kill all auto-incremented values.  */      /* ??? REG_INC is useless, since stack pushes aren't done that way.  */      for_each_rtx (&PATTERN (insn), kill_autoinc_value, vd);      /* Kill all early-clobbered operands.  */      for (i = 0; i < n_ops; i++)	if (recog_op_alt[i][alt].earlyclobber)	  kill_value (recog_data.operand[i], vd);      /* Special-case plain move instructions, since we may well	 be able to do the move from a different register class.  */      if (set && REG_P (SET_SRC (set)))	{	  rtx src = SET_SRC (set);	  unsigned int regno = REGNO (src);	  enum machine_mode mode = GET_MODE (src);	  unsigned int i;	  rtx new_rtx;	  /* If we are accessing SRC in some mode other that what we	     set it in, make sure that the replacement is valid.  */	  if (mode != vd->e[regno].mode)	    {	      if (hard_regno_nregs[regno][mode]		  > hard_regno_nregs[regno][vd->e[regno].mode])		goto no_move_special_case;	      /* And likewise, if we are narrowing on big endian the transformation		 is also invalid.  */	      if (hard_regno_nregs[regno][mode]//.........这里部分代码省略.........

static boolreplace_oldest_value_addr (rtx *loc, enum reg_class cl,			   enum machine_mode mode, addr_space_t as,			   rtx insn, struct value_data *vd){  rtx x = *loc;  RTX_CODE code = GET_CODE (x);  const char *fmt;  int i, j;  bool changed = false;  switch (code)    {    case PLUS:      if (DEBUG_INSN_P (insn))	break;      {	rtx orig_op0 = XEXP (x, 0);	rtx orig_op1 = XEXP (x, 1);	RTX_CODE code0 = GET_CODE (orig_op0);	RTX_CODE code1 = GET_CODE (orig_op1);	rtx op0 = orig_op0;	rtx op1 = orig_op1;	rtx *locI = NULL;	rtx *locB = NULL;	enum rtx_code index_code = SCRATCH;	if (GET_CODE (op0) == SUBREG)	  {	    op0 = SUBREG_REG (op0);	    code0 = GET_CODE (op0);	  }	if (GET_CODE (op1) == SUBREG)	  {	    op1 = SUBREG_REG (op1);	    code1 = GET_CODE (op1);	  }	if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE	    || code0 == ZERO_EXTEND || code1 == MEM)	  {	    locI = &XEXP (x, 0);	    locB = &XEXP (x, 1);	    index_code = GET_CODE (*locI);	  }	else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE		 || code1 == ZERO_EXTEND || code0 == MEM)	  {	    locI = &XEXP (x, 1);	    locB = &XEXP (x, 0);	    index_code = GET_CODE (*locI);	  }	else if (code0 == CONST_INT || code0 == CONST		 || code0 == SYMBOL_REF || code0 == LABEL_REF)	  {	    locB = &XEXP (x, 1);	    index_code = GET_CODE (XEXP (x, 0));	  }	else if (code1 == CONST_INT || code1 == CONST		 || code1 == SYMBOL_REF || code1 == LABEL_REF)	  {	    locB = &XEXP (x, 0);	    index_code = GET_CODE (XEXP (x, 1));	  }	else if (code0 == REG && code1 == REG)	  {	    int index_op;	    unsigned regno0 = REGNO (op0), regno1 = REGNO (op1);	    if (REGNO_OK_FOR_INDEX_P (regno1)		&& regno_ok_for_base_p (regno0, mode, as, PLUS, REG))	      index_op = 1;	    else if (REGNO_OK_FOR_INDEX_P (regno0)		     && regno_ok_for_base_p (regno1, mode, as, PLUS, REG))	      index_op = 0;	    else if (regno_ok_for_base_p (regno0, mode, as, PLUS, REG)		     || REGNO_OK_FOR_INDEX_P (regno1))	      index_op = 1;	    else if (regno_ok_for_base_p (regno1, mode, as, PLUS, REG))	      index_op = 0;	    else	      index_op = 1;	    locI = &XEXP (x, index_op);	    locB = &XEXP (x, !index_op);	    index_code = GET_CODE (*locI);	  }	else if (code0 == REG)	  {	    locI = &XEXP (x, 0);	    locB = &XEXP (x, 1);	    index_code = GET_CODE (*locI);	  }	else if (code1 == REG)	  {	    locI = &XEXP (x, 1);	    locB = &XEXP (x, 0);	    index_code = GET_CODE (*locI);//.........这里部分代码省略.........

static unsigned intrest_of_handle_simplify_got (void){  df_ref ref;  rtx use = NULL_RTX;  int i, n_symbol, n_access = 0;  struct got_access_info* got_accesses;  htab_t var_table = htab_create (VAR_TABLE_SIZE,				  htab_hash_pointer,				  htab_eq_pointer,				  NULL);  rtx pic_reg = targetm.got_access.get_pic_reg ();  gcc_assert (pic_reg);  ref = DF_REG_USE_CHAIN (REGNO (pic_reg));  got_accesses = XNEWVEC(struct got_access_info,			 DF_REG_USE_COUNT (REGNO (pic_reg)));  /* Check if all uses of pic_reg are loading global address through the     default method.  */  while (ref)    {      rtx_insn* insn = DF_REF_INSN (ref);      /* Check for the special USE insn, it is not a real usage of pic_reg.  */      if (GET_CODE (PATTERN (insn)) == USE)	use = insn;      else	{	  /* If an insn both set and use pic_reg, it is in the process of	     constructing the value of pic_reg. We should also ignore it.  */	  rtx set = single_set (insn);	  if (!(set && SET_DEST (set) == pic_reg))	    {	      rtx offset_reg;	      rtx offset_insn;	      rtx symbol = targetm.got_access.loaded_global_var (insn,								 &offset_reg,								 &offset_insn);	      if (symbol)		{		  rtx* slot = (rtx*) htab_find_slot (var_table, symbol, INSERT);		  if (*slot == HTAB_EMPTY_ENTRY)		    *slot = symbol;		  gcc_assert (set);		  got_accesses[n_access].symbol = symbol;		  got_accesses[n_access].offset_reg = offset_reg;		  got_accesses[n_access].address_reg = SET_DEST (set);		  got_accesses[n_access].load_insn = insn;		  got_accesses[n_access].offset_insn = offset_insn;		  n_access++;		}	      else		{		  /* This insn doesn't load a global address, but it has		     other unexpected usage of pic_reg, give up.  */		  free (got_accesses);		  htab_delete (var_table);		  return 0;		}	    }	}      ref = DF_REF_NEXT_REG(ref);    }  /* Check if we can simplify it.  */  n_symbol = htab_elements (var_table);  gcc_assert (n_symbol <= n_access);  if (!targetm.got_access.can_simplify_got_access (n_symbol, n_access))    {      free (got_accesses);      htab_delete (var_table);      return 0;    }  /* Rewrite the global address loading insns.  */  for (i=0; i<n_access; i++)    targetm.got_access.load_global_address (got_accesses[i].symbol,					    got_accesses[i].offset_reg,					    got_accesses[i].address_reg,					    got_accesses[i].load_insn,					    got_accesses[i].offset_insn);  /* Since there is no usage of pic_reg now, we can remove it.  */  if (use)    remove_insn (use);  targetm.got_access.clear_pic_reg ();  free (got_accesses);  htab_delete (var_table);  return 0;}

/* Recursive hash function for RTL X.  */static hashval_trtx_hash (rtx x){  int i, j;  enum rtx_code code;  const char *fmt;  hashval_t val = 0;  if (x == 0)    return val;  code = GET_CODE (x);  val += (int) code + 4095;  /* Some RTL can be compared nonrecursively.  */  switch (code)    {    case REG:      return val + REGNO (x);    case LABEL_REF:      return iterative_hash_object (XEXP (x, 0), val);    case SYMBOL_REF:      return iterative_hash_object (XSTR (x, 0), val);    case SCRATCH:    case CONST_DOUBLE:    case CONST_INT:    case CONST_VECTOR:      return val;    default:      break;    }  /* Hash the elements.  */  fmt = GET_RTX_FORMAT (code);  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)    {      switch (fmt[i])	{	case 'w':	  val += XWINT (x, i);	  break;	case 'n':	case 'i':	  val += XINT (x, i);	  break;	case 'V':	case 'E':	  val += XVECLEN (x, i);	  for (j = 0; j < XVECLEN (x, i); j++)	    val += rtx_hash (XVECEXP (x, i, j));	  break;	case 'e':	  val += rtx_hash (XEXP (x, i));	  break;	case 'S':	case 's':	  val += htab_hash_string (XSTR (x, i));	  break;	case 'u':	case '0':	case 't':	  break;	  /* It is believed that rtx's at this level will never	     contain anything but integers and other rtx's, except for	     within LABEL_REFs and SYMBOL_REFs.  */	default:	  abort ();	}    }  return val;}

static voidgen_int_relational (enum rtx_code code,			    rtx result,			    rtx cmp0,			    rtx cmp1,			    rtx destination)	{  machine_mode mode;  int branch_p;  mode = GET_MODE (cmp0);  if (mode == VOIDmode)    mode = GET_MODE (cmp1);  /* Is this a branch or compare.  */  branch_p = (destination != 0);  /* Instruction set doesn't support LE or LT, so swap operands and use      GE, GT.  */  switch (code)    {    case LE:    case LT:    case LEU:    case LTU:      {	rtx temp;	code = swap_condition (code);	temp = cmp0;	cmp0 = cmp1;	cmp1 = temp;	break;      }    default:      break;    }  if (branch_p)    {      rtx insn, cond, label;      /* Operands must be in registers.  */      if (!register_operand (cmp0, mode))	cmp0 = force_reg (mode, cmp0);      if (!register_operand (cmp1, mode))	cmp1 = force_reg (mode, cmp1);      /* Generate conditional branch instruction.  */      cond = gen_rtx_fmt_ee (code, mode, cmp0, cmp1);      label = gen_rtx_LABEL_REF (VOIDmode, destination);      insn = gen_rtx_SET (pc_rtx, gen_rtx_IF_THEN_ELSE (VOIDmode,							cond, label, pc_rtx));      emit_jump_insn (insn);    }  else    {      /* We can't have const_ints in cmp0, other than 0.  */      if ((GET_CODE (cmp0) == CONST_INT) && (INTVAL (cmp0) != 0))	cmp0 = force_reg (mode, cmp0);      /* If the comparison is against an int not in legal range         move it into a register.  */      if (GET_CODE (cmp1) == CONST_INT)	{	  switch (code)	    {	    case EQ:	    case NE:	    case LE:	    case LT:	    case GE:	    case GT:	      if (!satisfies_constraint_K (cmp1))		cmp1 = force_reg (mode, cmp1);	      break;	    case LEU:	    case LTU:	    case GEU:	    case GTU:	      if (!satisfies_constraint_L (cmp1))		cmp1 = force_reg (mode, cmp1);	      break;	    default:	      gcc_unreachable ();	    }	}      /* Generate compare instruction.  */      emit_move_insn (result, gen_rtx_fmt_ee (code, mode, cmp0, cmp1));    }}

static basic_blockcreate_pre_exit (int n_entities, int *entity_map, const int *num_modes){  edge eg;  edge_iterator ei;  basic_block pre_exit;  /* The only non-call predecessor at this stage is a block with a     fallthrough edge; there can be at most one, but there could be     none at all, e.g. when exit is called.  */  pre_exit = 0;  FOR_EACH_EDGE (eg, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds)    if (eg->flags & EDGE_FALLTHRU)      {	basic_block src_bb = eg->src;	rtx_insn *last_insn;	rtx ret_reg;	gcc_assert (!pre_exit);	/* If this function returns a value at the end, we have to	   insert the final mode switch before the return value copy	   to its hard register.  */	if (EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == 1	    && NONJUMP_INSN_P ((last_insn = BB_END (src_bb)))	    && GET_CODE (PATTERN (last_insn)) == USE	    && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG)	  {	    int ret_start = REGNO (ret_reg);	    int nregs = hard_regno_nregs[ret_start][GET_MODE (ret_reg)];	    int ret_end = ret_start + nregs;	    bool short_block = false;	    bool multi_reg_return = false;	    bool forced_late_switch = false;	    rtx_insn *before_return_copy;	    do	      {		rtx_insn *return_copy = PREV_INSN (last_insn);		rtx return_copy_pat, copy_reg;		int copy_start, copy_num;		int j;		if (NONDEBUG_INSN_P (return_copy))		  {		    /* When using SJLJ exceptions, the call to the		       unregister function is inserted between the		       clobber of the return value and the copy.		       We do not want to split the block before this		       or any other call; if we have not found the		       copy yet, the copy must have been deleted.  */		    if (CALL_P (return_copy))		      {			short_block = true;			break;		      }		    return_copy_pat = PATTERN (return_copy);		    switch (GET_CODE (return_copy_pat))		      {		      case USE:			/* Skip USEs of multiple return registers.			   __builtin_apply pattern is also handled here.  */			if (GET_CODE (XEXP (return_copy_pat, 0)) == REG			    && (targetm.calls.function_value_regno_p				(REGNO (XEXP (return_copy_pat, 0)))))			  {			    multi_reg_return = true;			    last_insn = return_copy;			    continue;			  }			break;		      case ASM_OPERANDS:			/* Skip barrier insns.  */			if (!MEM_VOLATILE_P (return_copy_pat))			  break;			/* Fall through.  */		      case ASM_INPUT:		      case UNSPEC_VOLATILE:			last_insn = return_copy;			continue;		      default:			break;		      }		    /* If the return register is not (in its entirety)		       likely spilled, the return copy might be		       partially or completely optimized away.  */		    return_copy_pat = single_set (return_copy);		    if (!return_copy_pat)		      {			return_copy_pat = PATTERN (return_copy);			if (GET_CODE (return_copy_pat) != CLOBBER)			  break;			else if (!optimize)			  {			    /* This might be (clobber (reg [<result>]))			       when not optimizing.  Then check if//.........这里部分代码省略.........

static voidgen_insn (rtx insn, int lineno){  struct pattern_stats stats;  int i;  /* See if the pattern for this insn ends with a group of CLOBBERs of (hard)     registers or MATCH_SCRATCHes.  If so, store away the information for     later.  */  if (XVEC (insn, 1))    {      int has_hard_reg = 0;      for (i = XVECLEN (insn, 1) - 1; i > 0; i--)	{	  if (GET_CODE (XVECEXP (insn, 1, i)) != CLOBBER)	    break;	  if (REG_P (XEXP (XVECEXP (insn, 1, i), 0)))	    has_hard_reg = 1;	  else if (GET_CODE (XEXP (XVECEXP (insn, 1, i), 0)) != MATCH_SCRATCH)	    break;	}      if (i != XVECLEN (insn, 1) - 1)	{	  struct clobber_pat *p;	  struct clobber_ent *link = XNEW (struct clobber_ent);	  int j;	  link->code_number = insn_code_number;	  /* See if any previous CLOBBER_LIST entry is the same as this	     one.  */	  for (p = clobber_list; p; p = p->next)	    {	      if (p->first_clobber != i + 1		  || XVECLEN (p->pattern, 1) != XVECLEN (insn, 1))		continue;	      for (j = i + 1; j < XVECLEN (insn, 1); j++)		{		  rtx old_rtx = XEXP (XVECEXP (p->pattern, 1, j), 0);		  rtx new_rtx = XEXP (XVECEXP (insn, 1, j), 0);		  /* OLD and NEW_INSN are the same if both are to be a SCRATCH		     of the same mode,		     or if both are registers of the same mode and number.  */		  if (! (GET_MODE (old_rtx) == GET_MODE (new_rtx)			 && ((GET_CODE (old_rtx) == MATCH_SCRATCH			      && GET_CODE (new_rtx) == MATCH_SCRATCH)			     || (REG_P (old_rtx) && REG_P (new_rtx)				 && REGNO (old_rtx) == REGNO (new_rtx)))))		    break;		}	      if (j == XVECLEN (insn, 1))		break;	    }	  if (p == 0)	    {	      p = XNEW (struct clobber_pat);	      p->insns = 0;	      p->pattern = insn;	      p->first_clobber = i + 1;	      p->next = clobber_list;	      p->has_hard_reg = has_hard_reg;	      clobber_list = p;	    }	  link->next = p->insns;	  p->insns = link;	}

static voidgen_addr_rtx (enum machine_mode address_mode,	      rtx symbol, rtx base, rtx index, rtx step, rtx offset,	      rtx *addr, rtx **step_p, rtx **offset_p){  rtx act_elem;  *addr = NULL_RTX;  if (step_p)    *step_p = NULL;  if (offset_p)    *offset_p = NULL;  if (index)    {      act_elem = index;      if (step)	{	  act_elem = gen_rtx_MULT (address_mode, act_elem, step);	  if (step_p)	    *step_p = &XEXP (act_elem, 1);	}      *addr = act_elem;    }  if (base && base != const0_rtx)    {      if (*addr)	*addr = simplify_gen_binary (PLUS, address_mode, base, *addr);      else	*addr = base;    }  if (symbol)    {      act_elem = symbol;      if (offset)	{	  act_elem = gen_rtx_PLUS (address_mode, act_elem, offset);	  if (offset_p)	    *offset_p = &XEXP (act_elem, 1);	  if (GET_CODE (symbol) == SYMBOL_REF	      || GET_CODE (symbol) == LABEL_REF	      || GET_CODE (symbol) == CONST)	    act_elem = gen_rtx_CONST (address_mode, act_elem);	}      if (*addr)	*addr = gen_rtx_PLUS (address_mode, *addr, act_elem);      else	*addr = act_elem;    }  else if (offset)    {      if (*addr)	{	  *addr = gen_rtx_PLUS (address_mode, *addr, offset);	  if (offset_p)	    *offset_p = &XEXP (*addr, 1);	}      else	{	  *addr = offset;	  if (offset_p)	    *offset_p = addr;	}    }  if (!*addr)    *addr = const0_rtx;}

static voidgen_exp (rtx x, enum rtx_code subroutine_type, char *used){  RTX_CODE code;  int i;  int len;  const char *fmt;  if (x == 0)    {      printf ("NULL_RTX");      return;    }  code = GET_CODE (x);  switch (code)    {    case MATCH_OPERAND:    case MATCH_DUP:      if (used)	{	  if (used[XINT (x, 0)])	    {	      printf ("copy_rtx (operand%d)", XINT (x, 0));	      return;	    }	  used[XINT (x, 0)] = 1;	}      printf ("operand%d", XINT (x, 0));      return;    case MATCH_OP_DUP:      printf ("gen_rtx_fmt_");      for (i = 0; i < XVECLEN (x, 1); i++)	printf ("e");      printf (" (GET_CODE (operand%d), ", XINT (x, 0));      if (GET_MODE (x) == VOIDmode)	printf ("GET_MODE (operand%d)", XINT (x, 0));      else	printf ("%smode", GET_MODE_NAME (GET_MODE (x)));      for (i = 0; i < XVECLEN (x, 1); i++)	{	  printf (",/n/t/t");	  gen_exp (XVECEXP (x, 1, i), subroutine_type, used);	}      printf (")");      return;    case MATCH_OPERATOR:      printf ("gen_rtx_fmt_");      for (i = 0; i < XVECLEN (x, 2); i++)	printf ("e");      printf (" (GET_CODE (operand%d)", XINT (x, 0));      printf (", %smode", GET_MODE_NAME (GET_MODE (x)));      for (i = 0; i < XVECLEN (x, 2); i++)	{	  printf (",/n/t/t");	  gen_exp (XVECEXP (x, 2, i), subroutine_type, used);	}      printf (")");      return;    case MATCH_PARALLEL:    case MATCH_PAR_DUP:      printf ("operand%d", XINT (x, 0));      return;    case MATCH_SCRATCH:      gen_rtx_scratch (x, subroutine_type);      return;    case PC:      printf ("pc_rtx");      return;    case RETURN:      printf ("ret_rtx");      return;    case SIMPLE_RETURN:      printf ("simple_return_rtx");      return;    case CLOBBER:      if (REG_P (XEXP (x, 0)))	{	  printf ("gen_hard_reg_clobber (%smode, %i)", GET_MODE_NAME (GET_MODE (XEXP (x, 0))),			  			     REGNO (XEXP (x, 0)));	  return;	}      break;    case CC0:      printf ("cc0_rtx");      return;    case CONST_INT:      if (INTVAL (x) == 0)	printf ("const0_rtx");      else if (INTVAL (x) == 1)	printf ("const1_rtx");      else if (INTVAL (x) == -1)//.........这里部分代码省略.........

rtxcopy_rtx (rtx orig){  rtx copy;  int i, j;  RTX_CODE code;  const char *format_ptr;  code = GET_CODE (orig);  switch (code)    {    case REG:    case DEBUG_EXPR:    case VALUE:    case CONST_INT:    case CONST_DOUBLE:    case CONST_FIXED:    case CONST_VECTOR:    case SYMBOL_REF:    case CODE_LABEL:    case PC:    case CC0:    case RETURN:    case SIMPLE_RETURN:    case SCRATCH:      /* SCRATCH must be shared because they represent distinct values.  */      return orig;    case CLOBBER:      if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER)	return orig;      break;    case CONST:      if (shared_const_p (orig))	return orig;      break;      /* A MEM with a constant address is not sharable.  The problem is that	 the constant address may need to be reloaded.  If the mem is shared,	 then reloading one copy of this mem will cause all copies to appear	 to have been reloaded.  */    default:      break;    }  /* Copy the various flags, fields, and other information.  We assume     that all fields need copying, and then clear the fields that should     not be copied.  That is the sensible default behavior, and forces     us to explicitly document why we are *not* copying a flag.  */  copy = shallow_copy_rtx (orig);  /* We do not copy the USED flag, which is used as a mark bit during     walks over the RTL.  */  RTX_FLAG (copy, used) = 0;  format_ptr = GET_RTX_FORMAT (GET_CODE (copy));  for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)    switch (*format_ptr++)      {      case 'e':	if (XEXP (orig, i) != NULL)	  XEXP (copy, i) = copy_rtx (XEXP (orig, i));	break;      case 'E':      case 'V':	if (XVEC (orig, i) != NULL)	  {	    XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));	    for (j = 0; j < XVECLEN (copy, i); j++)	      XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j));	  }	break;      case 't':      case 'w':      case 'i':      case 's':      case 'S':      case 'T':      case 'u':      case 'B':      case '0':	/* These are left unchanged.  */	break;      default:	gcc_unreachable ();      }  return copy;}

intrtx_equal_p (const_rtx x, const_rtx y){  int i;  int j;  enum rtx_code code;  const char *fmt;  if (x == y)    return 1;  if (x == 0 || y == 0)    return 0;  code = GET_CODE (x);  /* Rtx's of different codes cannot be equal.  */  if (code != GET_CODE (y))    return 0;  /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.     (REG:SI x) and (REG:HI x) are NOT equivalent.  */  if (GET_MODE (x) != GET_MODE (y))    return 0;  /* MEMs referring to different address space are not equivalent.  */  if (code == MEM && MEM_ADDR_SPACE (x) != MEM_ADDR_SPACE (y))    return 0;  /* Some RTL can be compared nonrecursively.  */  switch (code)    {    case REG:      return (REGNO (x) == REGNO (y));    case LABEL_REF:      return XEXP (x, 0) == XEXP (y, 0);    case SYMBOL_REF:      return XSTR (x, 0) == XSTR (y, 0);    case DEBUG_EXPR:    case VALUE:    case SCRATCH:    case CONST_DOUBLE:    case CONST_INT:    case CONST_FIXED:      return 0;    case DEBUG_IMPLICIT_PTR:      return DEBUG_IMPLICIT_PTR_DECL (x)	     == DEBUG_IMPLICIT_PTR_DECL (y);    case DEBUG_PARAMETER_REF:      return DEBUG_PARAMETER_REF_DECL (x)	     == DEBUG_PARAMETER_REF_DECL (y);    case ENTRY_VALUE:      return rtx_equal_p (ENTRY_VALUE_EXP (x), ENTRY_VALUE_EXP (y));    default:      break;    }  /* Compare the elements.  If any pair of corresponding elements     fail to match, return 0 for the whole thing.  */  fmt = GET_RTX_FORMAT (code);  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)    {      switch (fmt[i])	{	case 'w':	  if (XWINT (x, i) != XWINT (y, i))	    return 0;	  break;	case 'n':	case 'i':	  if (XINT (x, i) != XINT (y, i))	    {#ifndef GENERATOR_FILE	      if (((code == ASM_OPERANDS && i == 6)		   || (code == ASM_INPUT && i == 1))		  && locator_eq (XINT (x, i), XINT (y, i)))		break;#endif	      return 0;	    }	  break;	case 'V':	case 'E':	  /* Two vectors must have the same length.  */	  if (XVECLEN (x, i) != XVECLEN (y, i))	    return 0;	  /* And the corresponding elements must match.  */	  for (j = 0; j < XVECLEN (x, i); j++)	    if (rtx_equal_p (XVECEXP (x, i, j),  XVECEXP (y, i, j)) == 0)	      return 0;//.........这里部分代码省略.........

static boollm32_rtx_costs (rtx x, machine_mode mode, int outer_code,		int opno ATTRIBUTE_UNUSED, int *total, bool speed){  int code = GET_CODE (x);  bool small_mode;  const int arithmetic_latency = 1;  const int shift_latency = 1;  const int compare_latency = 2;  const int multiply_latency = 3;  const int load_latency = 3;  const int libcall_size_cost = 5;  /* Determine if we can handle the given mode size in a single instruction.  */  small_mode = (mode == QImode) || (mode == HImode) || (mode == SImode);  switch (code)    {    case PLUS:    case MINUS:    case AND:    case IOR:    case XOR:    case NOT:    case NEG:      if (!speed)	*total = COSTS_N_INSNS (LM32_NUM_REGS (mode));      else	*total =	  COSTS_N_INSNS (arithmetic_latency + (LM32_NUM_REGS (mode) - 1));      break;    case COMPARE:      if (small_mode)	{	  if (!speed)	    *total = COSTS_N_INSNS (1);	  else	    *total = COSTS_N_INSNS (compare_latency);	}      else	{	  /* FIXME. Guessing here.  */	  *total = COSTS_N_INSNS (LM32_NUM_REGS (mode) * (2 + 3) / 2);	}      break;    case ASHIFT:    case ASHIFTRT:    case LSHIFTRT:      if (TARGET_BARREL_SHIFT_ENABLED && small_mode)	{	  if (!speed)	    *total = COSTS_N_INSNS (1);	  else	    *total = COSTS_N_INSNS (shift_latency);	}      else if (TARGET_BARREL_SHIFT_ENABLED)	{	  /* FIXME: Guessing here.  */	  *total = COSTS_N_INSNS (LM32_NUM_REGS (mode) * 4);	}      else if (small_mode && GET_CODE (XEXP (x, 1)) == CONST_INT)	{	  *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1)));	}      else	{	  /* Libcall.  */	  if (!speed)	    *total = COSTS_N_INSNS (libcall_size_cost);	  else	    *total = COSTS_N_INSNS (100);	}      break;    case MULT:      if (TARGET_MULTIPLY_ENABLED && small_mode)	{	  if (!speed)	    *total = COSTS_N_INSNS (1);	  else	    *total = COSTS_N_INSNS (multiply_latency);	}      else	{	  /* Libcall.  */	  if (!speed)	    *total = COSTS_N_INSNS (libcall_size_cost);	  else	    *total = COSTS_N_INSNS (100);	}      break;    case DIV:    case MOD:    case UDIV:    case UMOD://.........这里部分代码省略.........

hashval_titerative_hash_rtx (const_rtx x, hashval_t hash){  enum rtx_code code;  enum machine_mode mode;  int i, j;  const char *fmt;  if (x == NULL_RTX)    return hash;  code = GET_CODE (x);  hash = iterative_hash_object (code, hash);  mode = GET_MODE (x);  hash = iterative_hash_object (mode, hash);  switch (code)    {    case REG:      i = REGNO (x);      return iterative_hash_object (i, hash);    case CONST_INT:      return iterative_hash_object (INTVAL (x), hash);    case SYMBOL_REF:      if (XSTR (x, 0))	return iterative_hash (XSTR (x, 0), strlen (XSTR (x, 0)) + 1,			       hash);      return hash;    case LABEL_REF:    case DEBUG_EXPR:    case VALUE:    case SCRATCH:    case CONST_DOUBLE:    case CONST_FIXED:    case DEBUG_IMPLICIT_PTR:    case DEBUG_PARAMETER_REF:      return hash;    default:      break;    }  fmt = GET_RTX_FORMAT (code);  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)    switch (fmt[i])      {      case 'w':	hash = iterative_hash_object (XWINT (x, i), hash);	break;      case 'n':      case 'i':	hash = iterative_hash_object (XINT (x, i), hash);	break;      case 'V':      case 'E':	j = XVECLEN (x, i);	hash = iterative_hash_object (j, hash);	for (j = 0; j < XVECLEN (x, i); j++)	  hash = iterative_hash_rtx (XVECEXP (x, i, j), hash);	break;      case 'e':	hash = iterative_hash_rtx (XEXP (x, i), hash);	break;      case 'S':      case 's':	if (XSTR (x, i))	  hash = iterative_hash (XSTR (x, 0), strlen (XSTR (x, 0)) + 1,				 hash);	break;      default:	break;      }  return hash;}