自学教程：C++ GT_READ函数代码示例

static void gt64240_p0int_irq(int irq, void *dev_id, struct pt_regs *regs){	uint32_t irq_src, irq_src_mask;	int handled;	/* get the low interrupt cause register */	GT_READ(LOW_INTERRUPT_CAUSE_REGISTER, &irq_src);	/* get the mask register for this pin */	GT_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, &irq_src_mask);	/* mask off only the interrupts we're interested in */	irq_src = irq_src & irq_src_mask;	handled = 0;	/* Check for timer interrupt */	if (irq_src & 0x00000100) {		handled = 1;		irq_src &= ~0x00000100;		/* Clear any pending cause bits */		GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);		/* handle the timer call */		do_timer(regs);	}	if (irq_src) {		printk(KERN_INFO		       "UNKNOWN P0_INT# interrupt received, irq_src=0x%x/n",		       irq_src);	}}

static irqreturn_t gt64120_irq(int irq, void *dev_id){	unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;	int handled = 0;	irq_src = GT_READ(GT_INTRCAUSE_OFS);	irq_src_mask = GT_READ(GT_INTRMASK_OFS);	int_high_src = GT_READ(GT_HINTRCAUSE_OFS);	int_high_src_mask = GT_READ(GT_HINTRMASK_OFS);	irq_src = irq_src & irq_src_mask;	int_high_src = int_high_src & int_high_src_mask;	if (irq_src & 0x00000800) {	/* Check for timer interrupt */		handled = 1;		irq_src &= ~0x00000800;		do_timer(1);#ifndef CONFIG_SMP		update_process_times(user_mode(get_irq_regs()));#endif	}	GT_WRITE(GT_INTRCAUSE_OFS, 0);	GT_WRITE(GT_HINTRCAUSE_OFS, 0);	return IRQ_HANDLED;}

void corehi_irqdispatch(struct pt_regs *regs){	unsigned int intrcause,datalo,datahi;        unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;        printk("CoreHI interrupt, shouldn't happen, so we die here!!!/n");        printk("epc   : %08lx/nStatus: %08lx/nCause : %08lx/nbadVaddr : %08lx/n", regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);	/* Read all the registers and then print them as there is a	   problem with interspersed printk's upsetting the Bonito controller.	   Do it for the others too.	*/        switch(mips_revision_corid) {        case MIPS_REVISION_CORID_CORE_MSC:        case MIPS_REVISION_CORID_CORE_FPGA2:        case MIPS_REVISION_CORID_CORE_FPGA3:        case MIPS_REVISION_CORID_CORE_24K:        case MIPS_REVISION_CORID_CORE_EMUL_MSC:                ll_msc_irq(regs);                break;        case MIPS_REVISION_CORID_QED_RM5261:        case MIPS_REVISION_CORID_CORE_LV:        case MIPS_REVISION_CORID_CORE_FPGA:        case MIPS_REVISION_CORID_CORE_FPGAR2:                intrcause = GT_READ(GT_INTRCAUSE_OFS);                datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);                datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);                printk("GT_INTRCAUSE = %08x/n", intrcause);                printk("GT_CPUERR_ADDR = %02x%08x/n", datahi, datalo);                break;        case MIPS_REVISION_CORID_BONITO64:        case MIPS_REVISION_CORID_CORE_20K:        case MIPS_REVISION_CORID_CORE_EMUL_BON:                pcibadaddr = BONITO_PCIBADADDR;                pcimstat = BONITO_PCIMSTAT;                intisr = BONITO_INTISR;                inten = BONITO_INTEN;                intpol = BONITO_INTPOL;                intedge = BONITO_INTEDGE;                intsteer = BONITO_INTSTEER;                pcicmd = BONITO_PCICMD;                printk("BONITO_INTISR = %08x/n", intisr);                printk("BONITO_INTEN = %08x/n", inten);                printk("BONITO_INTPOL = %08x/n", intpol);                printk("BONITO_INTEDGE = %08x/n", intedge);                printk("BONITO_INTSTEER = %08x/n", intsteer);                printk("BONITO_PCICMD = %08x/n", pcicmd);                printk("BONITO_PCIBADADDR = %08x/n", pcibadaddr);                printk("BONITO_PCIMSTAT = %08x/n", pcimstat);                break;        }        /* We die here*/        die("CoreHi interrupt", regs);}

static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,		struct pci_bus *bus, unsigned int devfn, int where, u32 * data){	unsigned char busnum = bus->number;	u32 intr;	if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))		return -1;	/*                                                */	/*                           */	GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |	                             GT_INTRCAUSE_TARABORT0_BIT));	/*               */	GT_WRITE(GT_PCI0_CFGADDR_OFS,		 (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) |		 (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |		 ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |		 GT_PCI0_CFGADDR_CONFIGEN_BIT);	if (access_type == PCI_ACCESS_WRITE) {		if (busnum == 0 && PCI_SLOT(devfn) == 0) {			/*                                                                                      */			GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);		} else			__GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);	} else {		if (busnum == 0 && PCI_SLOT(devfn) == 0) {			/*                                                                                      */			*data = GT_READ(GT_PCI0_CFGDATA_OFS);		} else			*data = __GT_READ(GT_PCI0_CFGDATA_OFS);	}	/*                                  */	intr = GT_READ(GT_INTRCAUSE_OFS);	if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {		/*                */		/*            */		GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |		                             GT_INTRCAUSE_TARABORT0_BIT));		return -1;	}	return 0;}

static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,		struct pci_bus *bus, unsigned int devfn, int where, u32 * data){	unsigned char busnum = bus->number;	u32 intr;	if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))		return -1;	/* Because of a bug in the galileo (for slot 31). */	/* Clear cause register bits */	GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |	                             GT_INTRCAUSE_TARABORT0_BIT));	/* Setup address */	GT_WRITE(GT_PCI0_CFGADDR_OFS,		 (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) |		 (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |		 ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |		 GT_PCI0_CFGADDR_CONFIGEN_BIT);	if (access_type == PCI_ACCESS_WRITE) {		if (busnum == 0 && PCI_SLOT(devfn) == 0) {			/*			 * The Galileo system controller is acting			 * differently than other devices.			 */			GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);		} else			__GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);	} else {		if (busnum == 0 && PCI_SLOT(devfn) == 0) {			/*			 * The Galileo system controller is acting			 * differently than other devices.			 */			*data = GT_READ(GT_PCI0_CFGDATA_OFS);		} else			*data = __GT_READ(GT_PCI0_CFGDATA_OFS);	}	/* Check for master or target abort */	intr = GT_READ(GT_INTRCAUSE_OFS);	if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {		/* Error occurred */		/* Clear bits */		GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |		                             GT_INTRCAUSE_TARABORT0_BIT));		return -1;	}	return 0;}

static void corehi_irqdispatch(void){	unsigned int intedge, intsteer, pcicmd, pcibadaddr;	unsigned int pcimstat, intisr, inten, intpol;	unsigned int intrcause, datalo, datahi;	struct pt_regs *regs = get_irq_regs();	printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!/n");	printk(KERN_EMERG "epc   : %08lx/nStatus: %08lx/n"			"Cause : %08lx/nbadVaddr : %08lx/n",			regs->cp0_epc, regs->cp0_status,			regs->cp0_cause, regs->cp0_badvaddr);	/* Read all the registers and then print them as there is a	   problem with interspersed printk's upsetting the Bonito controller.	   Do it for the others too.	*/	switch (mips_revision_sconid) {	case MIPS_REVISION_SCON_SOCIT:	case MIPS_REVISION_SCON_ROCIT:	case MIPS_REVISION_SCON_SOCITSC:	case MIPS_REVISION_SCON_SOCITSCP:		ll_msc_irq();		break;	case MIPS_REVISION_SCON_GT64120:		intrcause = GT_READ(GT_INTRCAUSE_OFS);		datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);		datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);		printk(KERN_EMERG "GT_INTRCAUSE = %08x/n", intrcause);		printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x/n",				datahi, datalo);		break;	case MIPS_REVISION_SCON_BONITO:		pcibadaddr = BONITO_PCIBADADDR;		pcimstat = BONITO_PCIMSTAT;		intisr = BONITO_INTISR;		inten = BONITO_INTEN;		intpol = BONITO_INTPOL;		intedge = BONITO_INTEDGE;		intsteer = BONITO_INTSTEER;		pcicmd = BONITO_PCICMD;		printk(KERN_EMERG "BONITO_INTISR = %08x/n", intisr);		printk(KERN_EMERG "BONITO_INTEN = %08x/n", inten);		printk(KERN_EMERG "BONITO_INTPOL = %08x/n", intpol);		printk(KERN_EMERG "BONITO_INTEDGE = %08x/n", intedge);		printk(KERN_EMERG "BONITO_INTSTEER = %08x/n", intsteer);		printk(KERN_EMERG "BONITO_PCICMD = %08x/n", pcicmd);		printk(KERN_EMERG "BONITO_PCIBADADDR = %08x/n", pcibadaddr);		printk(KERN_EMERG "BONITO_PCIMSTAT = %08x/n", pcimstat);		break;	}	die("CoreHi interrupt", regs);}

static int __init gt64120_pci_init(void){    u32 tmp;    tmp = GT_READ(GT_PCI0_CMD_OFS);        /* Huh??? -- Ralf  */    tmp = GT_READ(GT_PCI0_BARE_OFS);    /* reset the whole PCI I/O space range */    ioport_resource.start = GT_PCI_IO_BASE;    ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;    register_pci_controller(&hose_0);    return 0;}

static void mask_ack_gt641xx_irq(struct irq_data *d){	unsigned long flags;	u32 cause, mask;	raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);	mask = GT_READ(GT_INTRMASK_OFS);	mask &= ~GT641XX_IRQ_TO_BIT(d->irq);	GT_WRITE(GT_INTRMASK_OFS, mask);	cause = GT_READ(GT_INTRCAUSE_OFS);	cause &= ~GT641XX_IRQ_TO_BIT(d->irq);	GT_WRITE(GT_INTRCAUSE_OFS, cause);	raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);}

static void gt641xx_timer0_set_mode(enum clock_event_mode mode,				    struct clock_event_device *evt){	u32 ctrl;	raw_spin_lock(&gt641xx_timer_lock);	ctrl = GT_READ(GT_TC_CONTROL_OFS);	ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);	switch (mode) {	case CLOCK_EVT_MODE_PERIODIC:		ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;		break;	case CLOCK_EVT_MODE_ONESHOT:		ctrl |= GT_TC_CONTROL_ENTC0_MSK;		break;	default:		break;	}	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);	raw_spin_unlock(&gt641xx_timer_lock);}

static inline int mips_pcibios_iack(void){	int irq;	switch (mips_revision_sconid) {	case MIPS_REVISION_SCON_SOCIT:	case MIPS_REVISION_SCON_ROCIT:	case MIPS_REVISION_SCON_SOCITSC:	case MIPS_REVISION_SCON_SOCITSCP:		MSC_READ(MSC01_PCI_IACK, irq);		irq &= 0xff;		break;	case MIPS_REVISION_SCON_GT64120:		irq = GT_READ(GT_PCI0_IACK_OFS);		irq &= 0xff;		break;	case MIPS_REVISION_SCON_BONITO:		BONITO_PCIMAP_CFG = 0x20000;				(void) BONITO_PCIMAP_CFG;		iob();    		irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);		iob();    		irq &= 0xff;		BONITO_PCIMAP_CFG = 0;		break;	default:		printk(KERN_WARNING "Unknown system controller./n");		return -1;	}	return irq;}

static inline void galileo_irq(void){	unsigned int mask, pending, devfn;	mask = GT_READ(GT_INTRMASK_OFS);	pending = GT_READ(GT_INTRCAUSE_OFS) & mask;	if (pending & GT_INTR_T0EXP_MSK) {		GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);		do_IRQ(COBALT_GALILEO_IRQ);	} else if (pending & GT_INTR_RETRYCTR0_MSK) {		devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;		GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);		printk(KERN_WARNING		       "Galileo: PCI retry count exceeded (%02x.%u)/n",		       PCI_SLOT(devfn), PCI_FUNC(devfn));	} else {

int gt641xx_timer0_state(void){	if (GT_READ(GT_TC0_OFS))		return 0;	GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);	GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);	return 1;}

void corehi_irqdispatch(struct pt_regs *regs){        unsigned int data,datahi;	/* Mask out corehi interrupt. */	clear_c0_status(IE_IRQ3);        printk("CoreHI interrupt, shouldn't happen, so we die here!!!/n");        printk("epc   : %08lx/nStatus: %08lx/nCause : %08lx/nbadVaddr : %08lx/n", regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);        switch(mips_revision_corid) {        case MIPS_REVISION_CORID_CORE_MSC:                break;        case MIPS_REVISION_CORID_QED_RM5261:        case MIPS_REVISION_CORID_CORE_LV:        case MIPS_REVISION_CORID_CORE_FPGA:                data = GT_READ(GT_INTRCAUSE_OFS);                printk("GT_INTRCAUSE = %08x/n", data);                data = GT_READ(0x70);                datahi = GT_READ(0x78);                printk("GT_CPU_ERR_ADDR = %0x2%08x/n", datahi,data);                break;        case MIPS_REVISION_CORID_BONITO64:        case MIPS_REVISION_CORID_CORE_20K:                data = BONITO_INTISR;                printk("BONITO_INTISR = %08x/n", data);                data = BONITO_INTEN;                printk("BONITO_INTEN = %08x/n", data);                data = BONITO_INTPOL;                printk("BONITO_INTPOL = %08x/n", data);                data = BONITO_INTEDGE;                printk("BONITO_INTEDGE = %08x/n", data);                data = BONITO_INTSTEER;                printk("BONITO_INTSTEER = %08x/n", data);                data = BONITO_PCICMD;                printk("BONITO_PCICMD = %08x/n", data);                break;        }        /* We die here*/        die("CoreHi interrupt", regs);}

static void unmask_gt641xx_irq(struct irq_data *d){	unsigned long flags;	u32 mask;	raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);	mask = GT_READ(GT_INTRMASK_OFS);	mask |= GT641XX_IRQ_TO_BIT(d->irq);	GT_WRITE(GT_INTRMASK_OFS, mask);	raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);}

static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs){	unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;	int handled = 0;	irq_src = GT_READ(GT_INTRCAUSE_OFS);	irq_src_mask = GT_READ(GT_INTRMASK_OFS);	int_high_src = GT_READ(GT_HINTRCAUSE_OFS);	int_high_src_mask = GT_READ(GT_HINTRMASK_OFS);	irq_src = irq_src & irq_src_mask;	int_high_src = int_high_src & int_high_src_mask;	if (irq_src & 0x00000800) {	/* Check for timer interrupt */		handled = 1;		irq_src &= ~0x00000800;		do_timer(regs);	}	GT_WRITE(GT_INTRCAUSE_OFS, 0);	GT_WRITE(GT_HINTRCAUSE_OFS, 0);}

void malta_hw0_irqdispatch(struct pt_regs *regs){	int irq;	/*  	 * Determine highest priority pending interrupt by performing a PCI	 * Interrupt Acknowledge cycle.	 */	GT_READ(GT_PCI0_IACK_OFS, irq);	irq &= 0xFF;	do_IRQ(irq, regs);}

static int gt641xx_timer0_set_periodic(struct clock_event_device *evt){	u32 ctrl;	raw_spin_lock(&gt641xx_timer_lock);	ctrl = GT_READ(GT_TC_CONTROL_OFS);	ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);	raw_spin_unlock(&gt641xx_timer_lock);	return 0;}

static inline int mips_pcibios_iack(void){	int irq;        u32 dummy;	/*	 * Determine highest priority pending interrupt by performing	 * a PCI Interrupt Acknowledge cycle.	 */	switch(mips_revision_corid) {	case MIPS_REVISION_CORID_CORE_MSC:	case MIPS_REVISION_CORID_CORE_FPGA2:	case MIPS_REVISION_CORID_CORE_FPGA3:	case MIPS_REVISION_CORID_CORE_24K:	case MIPS_REVISION_CORID_CORE_EMUL_MSC:	        MSC_READ(MSC01_PCI_IACK, irq);		irq &= 0xff;		break;	case MIPS_REVISION_CORID_QED_RM5261:	case MIPS_REVISION_CORID_CORE_LV:	case MIPS_REVISION_CORID_CORE_FPGA:	case MIPS_REVISION_CORID_CORE_FPGAR2:		irq = GT_READ(GT_PCI0_IACK_OFS);		irq &= 0xff;		break;	case MIPS_REVISION_CORID_BONITO64:	case MIPS_REVISION_CORID_CORE_20K:	case MIPS_REVISION_CORID_CORE_EMUL_BON:		/* The following will generate a PCI IACK cycle on the		 * Bonito controller. It's a little bit kludgy, but it		 * was the easiest way to implement it in hardware at		 * the given time.		 */		BONITO_PCIMAP_CFG = 0x20000;		/* Flush Bonito register block */		dummy = BONITO_PCIMAP_CFG;		iob();    /* sync */		irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);		iob();    /* sync */		irq &= 0xff;		BONITO_PCIMAP_CFG = 0;		break;	default:	        printk("Unknown Core card, don't know the system controller./n");		return -1;	}	return irq;}

void __init plat_timer_setup(struct irqaction *irq){	/* Load timer value for HZ (TCLK is 50MHz) */	GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);	/* Enable timer */	GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);	/* Register interrupt */	setup_irq(COBALT_GALILEO_IRQ, irq);	/* Enable interrupt */	GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));}

void gt641xx_irq_dispatch(void){	u32 cause, mask;	int i;	cause = GT_READ(GT_INTRCAUSE_OFS);	mask = GT_READ(GT_INTRMASK_OFS);	cause &= mask;	/*	 * bit0 : logical or of all the interrupt bits.	 * bit30: logical or of bits[29:26,20:1].	 * bit31: logical or of bits[25:1].	 */	for (i = 1; i < 30; i++) {		if (cause & (1U << i)) {			do_IRQ(GT641XX_IRQ_BASE + i);			return;		}	}	atomic_inc_unchecked(&irq_err_count);}

static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs){	unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;	int handled = 0;	irq_src = GT_READ(GT_INTRCAUSE_OFS);	irq_src_mask = GT_READ(GT_INTRMASK_OFS);	int_high_src = GT_READ(GT_HINTRCAUSE_OFS);	int_high_src_mask = GT_READ(GT_HINTRMASK_OFS);	irq_src = irq_src & irq_src_mask;	int_high_src = int_high_src & int_high_src_mask;	if (irq_src & 0x00000800) {	/* Check for timer interrupt */		handled = 1;		irq_src &= ~0x00000800;		do_timer(regs);#ifndef CONFIG_SMP		update_process_times(user_mode(regs));#endif	}	GT_WRITE(GT_INTRCAUSE_OFS, 0);	GT_WRITE(GT_HINTRCAUSE_OFS, 0);}

void __init plat_mem_setup(void){	static struct uart_port uart;	unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);	int i;	_machine_restart = cobalt_machine_restart;	_machine_halt = cobalt_machine_halt;	pm_power_off = cobalt_machine_power_off;	set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));	/* I/O port resource must include LCD/buttons */	ioport_resource.end = 0x0fffffff;	/* These resources have been reserved by VIA SuperI/O chip. */	for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)		request_resource(&ioport_resource, cobalt_reserved_resources + i);        /* Read the cobalt id register out of the PCI config space */        PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));        cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);        cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);        cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);	printk("Cobalt board ID: %d/n", cobalt_board_id);#ifdef CONFIG_PCI	register_pci_controller(&cobalt_pci_controller);#endif	if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {#ifdef CONFIG_SERIAL_8250		uart.line	= 0;		uart.type	= PORT_UNKNOWN;		uart.uartclk	= 18432000;		uart.irq	= COBALT_SERIAL_IRQ;		uart.flags	= UPF_IOREMAP | UPF_BOOT_AUTOCONF |				  UPF_SKIP_TEST;		uart.iotype	= UPIO_MEM;		uart.mapbase	= 0x1c800000;		early_serial_setup(&uart);#endif	}}

static int gt641xx_timer0_set_next_event(unsigned long delta,					 struct clock_event_device *evt){	u32 ctrl;	raw_spin_lock(&gt641xx_timer_lock);	ctrl = GT_READ(GT_TC_CONTROL_OFS);	ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);	ctrl |= GT_TC_CONTROL_ENTC0_MSK;	GT_WRITE(GT_TC0_OFS, delta);	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);	raw_spin_unlock(&gt641xx_timer_lock);	return 0;}

static inline int mips_pcibios_iack(void){	int irq;	u32 dummy;	/*	 * Determine highest priority pending interrupt by performing	 * a PCI Interrupt Acknowledge cycle.	 */	switch (mips_revision_sconid) {	case MIPS_REVISION_SCON_SOCIT:	case MIPS_REVISION_SCON_ROCIT:	case MIPS_REVISION_SCON_SOCITSC:	case MIPS_REVISION_SCON_SOCITSCP:		MSC_READ(MSC01_PCI_IACK, irq);		irq &= 0xff;		break;	case MIPS_REVISION_SCON_GT64120:		irq = GT_READ(GT_PCI0_IACK_OFS);		irq &= 0xff;		break;	case MIPS_REVISION_SCON_BONITO:		/* The following will generate a PCI IACK cycle on the		 * Bonito controller. It's a little bit kludgy, but it		 * was the easiest way to implement it in hardware at		 * the given time.		 */		BONITO_PCIMAP_CFG = 0x20000;		/* Flush Bonito register block */		dummy = BONITO_PCIMAP_CFG;		iob();    /* sync */		irq = readl((u32 *)_pcictrl_bonito_pcicfg);		iob();    /* sync */		irq &= 0xff;		BONITO_PCIMAP_CFG = 0;		break;	default:		printk(KERN_WARNING "Unknown system controller./n");		return -1;	}	return irq;}

void __init mips_pcibios_init(void){	struct pci_controller *controller;	resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;	switch (mips_revision_sconid) {	case MIPS_REVISION_SCON_GT64120:		/*		 * Due to a bug in the Galileo system controller, we need		 * to setup the PCI BAR for the Galileo internal registers.		 * This should be done in the bios/bootprom and will be		 * fixed in a later revision of YAMON (the MIPS boards		 * boot prom).		 */		GT_WRITE(GT_PCI0_CFGADDR_OFS,			 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */			 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */			 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/			 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/			 GT_PCI0_CFGADDR_CONFIGEN_BIT);		/* Perform the write */		GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));		/* Set up resource ranges from the controller's registers.  */		start = GT_READ(GT_PCI0M0LD_OFS);		end = GT_READ(GT_PCI0M0HD_OFS);		map = GT_READ(GT_PCI0M0REMAP_OFS);		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);		start1 = GT_READ(GT_PCI0M1LD_OFS);		end1 = GT_READ(GT_PCI0M1HD_OFS);		map1 = GT_READ(GT_PCI0M1REMAP_OFS);		end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);		/* Cannot support multiple windows, use the wider.  */		if (end1 - start1 > end - start) {			start = start1;			end = end1;			map = map1;		}		mask = ~(start ^ end);		/* We don't support remapping with a discontiguous mask.  */		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&		       mask != ~((mask & -mask) - 1));		gt64120_mem_resource.start = start;		gt64120_mem_resource.end = end;		gt64120_controller.mem_offset = (start & mask) - (map & mask);		/* Addresses are 36-bit, so do shifts in the destinations.  */		gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;		gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;		gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;		gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;		start = GT_READ(GT_PCI0IOLD_OFS);		end = GT_READ(GT_PCI0IOHD_OFS);		map = GT_READ(GT_PCI0IOREMAP_OFS);		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);		mask = ~(start ^ end);		/* We don't support remapping with a discontiguous mask.  */		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&		       mask != ~((mask & -mask) - 1));		gt64120_io_resource.start = map & mask;		gt64120_io_resource.end = (map & mask) | ~mask;		gt64120_controller.io_offset = 0;		/* Addresses are 36-bit, so do shifts in the destinations.  */		gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;		gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;		gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;		controller = &gt64120_controller;		break;	case MIPS_REVISION_SCON_BONITO:		/* Set up resource ranges from the controller's registers.  */		map = BONITO_PCIMAP;		map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>		       BONITO_PCIMAP_PCIMAP_LO0_SHIFT;		map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>		       BONITO_PCIMAP_PCIMAP_LO1_SHIFT;		map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>		       BONITO_PCIMAP_PCIMAP_LO2_SHIFT;		/* Combine as many adjacent windows as possible.  */		map = map1;		start = BONITO_PCILO0_BASE;		end = 1;		if (map3 == map2 + 1) {			map = map2;			start = BONITO_PCILO1_BASE;			end++;		}		if (map2 == map1 + 1) {			map = map1;			start = BONITO_PCILO0_BASE;			end++;		}		bonito64_mem_resource.start = start;		bonito64_mem_resource.end = start +					    BONITO_PCIMAP_WINBASE(end) - 1;		bonito64_controller.mem_offset = start -						 BONITO_PCIMAP_WINBASE(map);//.........这里部分代码省略.........

void __init prom_init(void){	mips_display_message("LINUX");	/*	 * early setup of _pcictrl_bonito so that we can determine	 * the system controller on a CORE_EMUL board	 */	_pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);	mips_revision_corid = MIPS_REVISION_CORID;	if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {		if (BONITO_PCIDID == 0x0001df53 ||		    BONITO_PCIDID == 0x0003df53)			mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;		else			mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;	}	mips_revision_sconid = MIPS_REVISION_SCONID;	if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {		switch (mips_revision_corid) {		case MIPS_REVISION_CORID_QED_RM5261:		case MIPS_REVISION_CORID_CORE_LV:		case MIPS_REVISION_CORID_CORE_FPGA:		case MIPS_REVISION_CORID_CORE_FPGAR2:			mips_revision_sconid = MIPS_REVISION_SCON_GT64120;			break;		case MIPS_REVISION_CORID_CORE_EMUL_BON:		case MIPS_REVISION_CORID_BONITO64:		case MIPS_REVISION_CORID_CORE_20K:			mips_revision_sconid = MIPS_REVISION_SCON_BONITO;			break;		case MIPS_REVISION_CORID_CORE_MSC:		case MIPS_REVISION_CORID_CORE_FPGA2:		case MIPS_REVISION_CORID_CORE_24K:			/*			 * SOCit/ROCit support is essentially identical			 * but make an attempt to distinguish them			 */			mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;			break;		case MIPS_REVISION_CORID_CORE_FPGA3:		case MIPS_REVISION_CORID_CORE_FPGA4:		case MIPS_REVISION_CORID_CORE_FPGA5:		case MIPS_REVISION_CORID_CORE_EMUL_MSC:		default:			/* See above */			mips_revision_sconid = MIPS_REVISION_SCON_ROCIT;			break;		}	}	switch (mips_revision_sconid) {		u32 start, map, mask, data;	case MIPS_REVISION_SCON_GT64120:		/*		 * Setup the North bridge to do Master byte-lane swapping		 * when running in bigendian.		 */		_pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);#ifdef CONFIG_CPU_LITTLE_ENDIAN		GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |			 GT_PCI0_CMD_SBYTESWAP_BIT);#else		GT_WRITE(GT_PCI0_CMD_OFS, 0);#endif		/* Fix up PCI I/O mapping if necessary (for Atlas).  */		start = GT_READ(GT_PCI0IOLD_OFS);		map = GT_READ(GT_PCI0IOREMAP_OFS);		if ((start & map) != 0) {			map &= ~start;			GT_WRITE(GT_PCI0IOREMAP_OFS, map);		}		set_io_port_base(MALTA_GT_PORT_BASE);		break;	case MIPS_REVISION_SCON_BONITO:		_pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);		/*		 * Disable Bonito IOBC.		 */		BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &			~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |			  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);		/*		 * Setup the North bridge to do Master byte-lane swapping		 * when running in bigendian.		 */#ifdef CONFIG_CPU_LITTLE_ENDIAN		BONITO_BONGENCFG = BONITO_BONGENCFG &			~(BONITO_BONGENCFG_MSTRBYTESWAP |			  BONITO_BONGENCFG_BYTESWAP);#else//.........这里部分代码省略.........

void __init mips_pcibios_init(void){	struct pci_controller *controller;	unsigned long start, end, map, start1, end1, map1, map2, map3, mask;	switch (mips_revision_corid) {	case MIPS_REVISION_CORID_QED_RM5261:	case MIPS_REVISION_CORID_CORE_LV:	case MIPS_REVISION_CORID_CORE_FPGA:	case MIPS_REVISION_CORID_CORE_FPGAR2:		/*		 * Due to a bug in the Galileo system controller, we need		 * to setup the PCI BAR for the Galileo internal registers.		 * This should be done in the bios/bootprom and will be		 * fixed in a later revision of YAMON (the MIPS boards		 * boot prom).		 */		GT_WRITE(GT_PCI0_CFGADDR_OFS,			 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */			 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */			 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/			 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/			 GT_PCI0_CFGADDR_CONFIGEN_BIT);		/* Perform the write */		GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));		/* Set up resource ranges from the controller's registers.  */		start = GT_READ(GT_PCI0M0LD_OFS);		end = GT_READ(GT_PCI0M0HD_OFS);		map = GT_READ(GT_PCI0M0REMAP_OFS);		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);		start1 = GT_READ(GT_PCI0M1LD_OFS);		end1 = GT_READ(GT_PCI0M1HD_OFS);		map1 = GT_READ(GT_PCI0M1REMAP_OFS);		end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);		/* Cannot support multiple windows, use the wider.  */		if (end1 - start1 > end - start) {			start = start1;			end = end1;			map = map1;		}		mask = ~(start ^ end);                /* We don't support remapping with a discontiguous mask.  */		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&		       mask != ~((mask & -mask) - 1));		gt64120_mem_resource.start = start;		gt64120_mem_resource.end = end;		gt64120_controller.mem_offset = (start & mask) - (map & mask);		/* Addresses are 36-bit, so do shifts in the destinations.  */		gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;		gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;		gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;		gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;		start = GT_READ(GT_PCI0IOLD_OFS);		end = GT_READ(GT_PCI0IOHD_OFS);		map = GT_READ(GT_PCI0IOREMAP_OFS);		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);		mask = ~(start ^ end);                /* We don't support remapping with a discontiguous mask.  */		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&		       mask != ~((mask & -mask) - 1));		gt64120_io_resource.start = map & mask;		gt64120_io_resource.end = (map & mask) | ~mask;		gt64120_controller.io_offset = 0;		/* Addresses are 36-bit, so do shifts in the destinations.  */		gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;		gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;		gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;		controller = &gt64120_controller;		break;	case MIPS_REVISION_CORID_BONITO64:	case MIPS_REVISION_CORID_CORE_20K:	case MIPS_REVISION_CORID_CORE_EMUL_BON:		/* Set up resource ranges from the controller's registers.  */		map = BONITO_PCIMAP;		map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>		       BONITO_PCIMAP_PCIMAP_LO0_SHIFT;		map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>		       BONITO_PCIMAP_PCIMAP_LO1_SHIFT;		map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>		       BONITO_PCIMAP_PCIMAP_LO2_SHIFT;		/* Combine as many adjacent windows as possible.  */		map = map1;		start = BONITO_PCILO0_BASE;		end = 1;		if (map3 == map2 + 1) {			map = map2;			start = BONITO_PCILO1_BASE;			end++;		}		if (map2 == map1 + 1) {			map = map1;			start = BONITO_PCILO0_BASE;			end++;		}		bonito64_mem_resource.start = start;//.........这里部分代码省略.........

void __init mips_pcibios_init(void){	struct pci_controller *controller;	resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;	switch (mips_revision_sconid) {	case MIPS_REVISION_SCON_GT64120:		GT_WRITE(GT_PCI0_CFGADDR_OFS,			 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | 			 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | 			 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | 			 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | 			 GT_PCI0_CFGADDR_CONFIGEN_BIT);				GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));				start = GT_READ(GT_PCI0M0LD_OFS);		end = GT_READ(GT_PCI0M0HD_OFS);		map = GT_READ(GT_PCI0M0REMAP_OFS);		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);		start1 = GT_READ(GT_PCI0M1LD_OFS);		end1 = GT_READ(GT_PCI0M1HD_OFS);		map1 = GT_READ(GT_PCI0M1REMAP_OFS);		end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);				if (end1 - start1 > end - start) {			start = start1;			end = end1;			map = map1;		}		mask = ~(start ^ end);                		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&		       mask != ~((mask & -mask) - 1));		gt64120_mem_resource.start = start;		gt64120_mem_resource.end = end;		gt64120_controller.mem_offset = (start & mask) - (map & mask);				gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;		gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;		gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;		gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;		start = GT_READ(GT_PCI0IOLD_OFS);		end = GT_READ(GT_PCI0IOHD_OFS);		map = GT_READ(GT_PCI0IOREMAP_OFS);		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);		mask = ~(start ^ end);                		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&		       mask != ~((mask & -mask) - 1));		gt64120_io_resource.start = map & mask;		gt64120_io_resource.end = (map & mask) | ~mask;		gt64120_controller.io_offset = 0;				gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;		gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;		gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;		controller = &gt64120_controller;		break;	case MIPS_REVISION_SCON_BONITO:				map = BONITO_PCIMAP;		map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>		       BONITO_PCIMAP_PCIMAP_LO0_SHIFT;		map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>		       BONITO_PCIMAP_PCIMAP_LO1_SHIFT;		map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>		       BONITO_PCIMAP_PCIMAP_LO2_SHIFT;				map = map1;		start = BONITO_PCILO0_BASE;		end = 1;		if (map3 == map2 + 1) {			map = map2;			start = BONITO_PCILO1_BASE;			end++;		}		if (map2 == map1 + 1) {			map = map1;			start = BONITO_PCILO0_BASE;			end++;		}		bonito64_mem_resource.start = start;		bonito64_mem_resource.end = start +					    BONITO_PCIMAP_WINBASE(end) - 1;		bonito64_controller.mem_offset = start -						 BONITO_PCIMAP_WINBASE(map);		controller = &bonito64_controller;		break;	case MIPS_REVISION_SCON_SOCIT:	case MIPS_REVISION_SCON_ROCIT:	case MIPS_REVISION_SCON_SOCITSC:	case MIPS_REVISION_SCON_SOCITSCP://.........这里部分代码省略.........

void __init prom_init(void){	prom_argc = fw_arg0;	_prom_argv = (int *) fw_arg1;	_prom_envp = (int *) fw_arg2;	mips_display_message("LINUX");	_pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);	mips_revision_corid = MIPS_REVISION_CORID;	if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {		if (BONITO_PCIDID == 0x0001df53 ||		    BONITO_PCIDID == 0x0003df53)			mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;		else			mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;	}	mips_revision_sconid = MIPS_REVISION_SCONID;	if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {		switch (mips_revision_corid) {		case MIPS_REVISION_CORID_QED_RM5261:		case MIPS_REVISION_CORID_CORE_LV:		case MIPS_REVISION_CORID_CORE_FPGA:		case MIPS_REVISION_CORID_CORE_FPGAR2:			mips_revision_sconid = MIPS_REVISION_SCON_GT64120;			break;		case MIPS_REVISION_CORID_CORE_EMUL_BON:		case MIPS_REVISION_CORID_BONITO64:		case MIPS_REVISION_CORID_CORE_20K:			mips_revision_sconid = MIPS_REVISION_SCON_BONITO;			break;		case MIPS_REVISION_CORID_CORE_MSC:		case MIPS_REVISION_CORID_CORE_FPGA2:		case MIPS_REVISION_CORID_CORE_24K:			mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;			break;		case MIPS_REVISION_CORID_CORE_FPGA3:		case MIPS_REVISION_CORID_CORE_FPGA4:		case MIPS_REVISION_CORID_CORE_FPGA5:		case MIPS_REVISION_CORID_CORE_EMUL_MSC:		default:						mips_revision_sconid = MIPS_REVISION_SCON_ROCIT;			break;		}	}	switch (mips_revision_sconid) {		u32 start, map, mask, data;	case MIPS_REVISION_SCON_GT64120:		_pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);#ifdef CONFIG_CPU_LITTLE_ENDIAN		GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |			 GT_PCI0_CMD_SBYTESWAP_BIT);#else		GT_WRITE(GT_PCI0_CMD_OFS, 0);#endif				start = GT_READ(GT_PCI0IOLD_OFS);		map = GT_READ(GT_PCI0IOREMAP_OFS);		if ((start & map) != 0) {			map &= ~start;			GT_WRITE(GT_PCI0IOREMAP_OFS, map);		}		set_io_port_base(MALTA_GT_PORT_BASE);		break;	case MIPS_REVISION_SCON_BONITO:		_pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);		BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &			~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |			  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);#ifdef CONFIG_CPU_LITTLE_ENDIAN		BONITO_BONGENCFG = BONITO_BONGENCFG &			~(BONITO_BONGENCFG_MSTRBYTESWAP |			  BONITO_BONGENCFG_BYTESWAP);#else		BONITO_BONGENCFG = BONITO_BONGENCFG |			BONITO_BONGENCFG_MSTRBYTESWAP |			BONITO_BONGENCFG_BYTESWAP;#endif		set_io_port_base(MALTA_BONITO_PORT_BASE);		break;	case MIPS_REVISION_SCON_SOCIT:	case MIPS_REVISION_SCON_ROCIT:		_pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);	mips_pci_controller:		mb();		MSC_READ(MSC01_PCI_CFG, data);		MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);//.........这里部分代码省略.........

/* * Interrupt handler for interrupts coming from the Galileo chip. * It could be built in ethernet ports etc... */static void gt64240_irq(int irq, void *dev_id, struct pt_regs *regs){	unsigned int irq_src, int_high_src, irq_src_mask,	    int_high_src_mask;	int handled;#if 0	GT_READ(GT_INTRCAUSE_OFS, &irq_src);	GT_READ(GT_INTRMASK_OFS, &irq_src_mask);	GT_READ(GT_HINTRCAUSE_OFS, &int_high_src);	GT_READ(GT_HINTRMASK_OFS, &int_high_src_mask);#endif	irq_src = irq_src & irq_src_mask;	int_high_src = int_high_src & int_high_src_mask;	handled = 0;	/* Execute all interrupt handlers */	/* Check for timer interrupt */	if (irq_src & 0x00000800) {		handled = 1;		irq_src &= ~0x00000800;		//    RESET_REG_BITS (INTERRUPT_CAUSE_REGISTER,BIT8);		do_timer(regs);	}	if (irq_src) {		printk(KERN_INFO		       "Other Galileo interrupt received irq_src %x/n",		       irq_src);#if CURRENTLY_UNUSED		for (count = 0; count < MAX_CAUSE_REG_WIDTH; count++) {			if (irq_src & (1 << count)) {				if (irq_handlers[INT_CAUSE_MAIN][count].				    routine) {					queue_task(&irq_handlers						   [INT_CAUSE_MAIN][count],						   &tq_immediate);					mark_bh(IMMEDIATE_BH);					handled = 1;				}			}		}#endif				/*  UNUSED  */	}#if 0	GT_WRITE(GT_INTRCAUSE_OFS, 0);	GT_WRITE(GT_HINTRCAUSE_OFS, 0);#endif#undef GALILEO_I2O#ifdef GALILEO_I2O	/*	 * Future I2O support.  We currently attach I2O interrupt handlers to	 * the Galileo interrupt (int 4) and handle them in do_IRQ.	 */	if (isInBoundDoorBellInterruptSet()) {		printk(KERN_INFO "I2O doorbell interrupt received./n");		handled = 1;	}	if (isInBoundPostQueueInterruptSet()) {		printk(KERN_INFO "I2O Queue interrupt received./n");		handled = 1;	}	/*	 * This normally would be outside of the ifdef, but since we're	 * handling I2O outside of this handler, this printk shows up every	 * time we get a valid I2O interrupt.  So turn this off for now.	 */	if (handled == 0) {		if (counter < 50) {			printk("Spurious Galileo interrupt.../n");			counter++;		}	}#endif}