自学教程：C++ GetPciAddress函数代码示例

/** * A Family Specific Workaround method, to sync internal node 1 SbiAddr setting. * * @param[in] Data      The table data value (unused in this routine) * @param[in] StdHeader Config handle for library and services * *--------------------------------------------------------------------------------------- **/VOIDSTATICF10RevDSyncInternalNode1SbiAddr (  IN       UINT32            Data,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT32       Socket;  UINT32       Module;  UINT32       DataOr;  UINT32       DataAnd;  UINT32       ModuleType;  PCI_ADDR     PciAddress;  AGESA_STATUS AgesaStatus;  UINT32       SyncToModule;  AP_MAIL_INFO ApMailboxInfo;  UINT32       LocalPciRegister;  ApMailboxInfo.Info = 0;  GetApMailbox (&ApMailboxInfo.Info, StdHeader);  ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS);  ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES);  Socket = ApMailboxInfo.Fields.Socket;  Module = ApMailboxInfo.Fields.Module;  ModuleType = ApMailboxInfo.Fields.ModuleType;  // sync is just needed on multinode cpu  if (ModuleType != 0) {    // check if it is internal node 0 of every socket    if (Module == 0) {      if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {        PciAddress.Address.Function = FUNC_3;        PciAddress.Address.Register = 0x1E4;        // read internal node 0 F3x1E4[6:4]        LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);        DataOr = LocalPciRegister & ((UINT32) (7 << 4));        DataAnd = ~(UINT32) (7 << 4);        for (SyncToModule = 1; SyncToModule < GetPlatformNumberOfModules (); SyncToModule++) {          if (GetPciAddress (StdHeader, Socket, SyncToModule, &PciAddress, &AgesaStatus)) {            PciAddress.Address.Function = FUNC_3;            PciAddress.Address.Register = 0x1E4;            // sync the other internal node F3x1E4[6:4]            LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);            LocalPciRegister &= DataAnd;            LocalPciRegister |= DataOr;            LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);          }        }      }    }  }}

/** *  Writes to all nodes on the executing core's socket. * *  @param[in]     PciAddress    The Function and Register to update *  @param[in]     Mask          The bitwise AND mask to apply to the current register value *  @param[in]     Data          The bitwise OR mask to apply to the current register value *  @param[in]     StdHeader     Header for library and services. * */VOIDModifyCurrSocketPciMulti (  IN       PCI_ADDR               *PciAddress,  IN       UINT32                 Mask,  IN       UINT32                 Data,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32 Socket;  UINT32 Module;  UINT32 Core;  UINT32 LocalPciRegister;  AGESA_STATUS AgesaStatus;  PCI_ADDR Reg;  IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus);  for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {    if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) {      Reg.Address.Function = PciAddress->Address.Function;      Reg.Address.Register = PciAddress->Address.Register;      LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader);      LocalPciRegister &= Mask;      LocalPciRegister |= Data;      LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader);    }  }}

/** *  Check to see if the input CPU supports L3 dependent features. * * @param[in]    L3FeatureServices   L3 Feature family services. * @param[in]    Socket              Processor socket to check. * @param[in]    StdHeader           Config Handle for library, services. * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data. * * @retval       TRUE                L3 dependent features are supported. * @retval       FALSE               L3 dependent features are not supported. * */BOOLEANSTATICF10IsL3FeatureSupported (  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,  IN       UINT32 Socket,  IN       AMD_CONFIG_PARAMS *StdHeader,  IN       PLATFORM_CONFIGURATION *PlatformConfig  ){  UINT32       Module;  UINT32       LocalPciRegister;  BOOLEAN      IsSupported;  PCI_ADDR     PciAddress;  AGESA_STATUS IgnoredStatus;  IsSupported = FALSE;  if (PlatformConfig->PlatformProfile.UseHtAssist) {  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {      PciAddress.Address.Function = FUNC_3;      PciAddress.Address.Register = NB_CAPS_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);      if (((NB_CAPS_REGISTER *) &LocalPciRegister)->L3Capable == 1) {        IsSupported = TRUE;      }      break;    }  }  }  return IsSupported;}

/** *    Main entry point for initializing the Thermal Control *    safety net feature. * *    This must be run by all Family 10h core 0s in the system. * * @param[in]  FamilySpecificServices  The current Family Specific Services. * @param[in]  CpuEarlyParamsPtr       Service parameters. * @param[in]  StdHeader               Config handle for library and services. */VOIDF10PmThermalInit (  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,  IN       AMD_CONFIG_PARAMS     *StdHeader  ){  UINT32    Core;  UINT32    Module;  UINT32    LocalPciRegister;  UINT32    Socket;  PCI_ADDR  PciAddress;  AGESA_STATUS  IgnoredSts;  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);  ASSERT (Core == 0);  if (GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts)) {    PciAddress.Address.Function = FUNC_3;    PciAddress.Address.Register = NB_CAPS_REG;    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);    if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) {      // Enable HTC      PciAddress.Address.Register = HTC_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);      ((HTC_REGISTER *) &LocalPciRegister)->HtcSlewSel = 0;      ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);    }  }}

/** * Multisocket call to determine if the BIOS is responsible for updating the * northbridge operating frequency and voltage. * * This function loops through all possible socket locations, checking whether * any populated sockets require NB COF VID programming. * * @param[in]  StdHeader         Config handle for library and services * * @retval     TRUE    BIOS needs to set up NB frequency and voltage * @retval     FALSE   BIOS does not need to set up NB frequency and voltage * */BOOLEANGetSystemNbCofVidUpdateMulti (  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT8    Module;  UINT32   Socket;  UINT32   NumberOfSockets;  BOOLEAN  IgnoredBool;  BOOLEAN  AtLeast1RequiresUpdate;  PCI_ADDR PciAddress;  AGESA_STATUS Ignored;  CPU_SPECIFIC_SERVICES *FamilySpecificServices;  NumberOfSockets = GetPlatformNumberOfSockets ();  AtLeast1RequiresUpdate = FALSE;  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {        if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) {          break;        }      }      if (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &IgnoredBool, StdHeader)) {        AtLeast1RequiresUpdate = TRUE;        break;      }    }  }  return AtLeast1RequiresUpdate;}

/** * Clear EnableCf8ExtCfg on all socket * * Clear F3x8C bit 14 EnableCf8ExtCfg * * @param[in]  StdHeader         Config handle for library and services * * */VOIDDisableCf8ExtCfg (  IN       AMD_CONFIG_PARAMS   *StdHeader  ){  AGESA_STATUS  AgesaStatus;  PCI_ADDR PciAddress;  UINT32 Socket;  UINT32 Module;  UINT32 PciData;  UINT32 LegacyPciAccess;  ASSERT (IsBsp (StdHeader, &AgesaStatus));  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {      if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {        PciAddress.Address.Function = FUNC_3;        PciAddress.Address.Register = NB_CFG_HIGH_REG;        LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));        // read from PCI register        LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);        LibAmdIoRead (AccessWidth32, IOCFC, &PciData, StdHeader);        // Disable Cf8ExtCfg        PciData &= 0xFFFFBFFF;        // write to PCI register        LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);        LibAmdIoWrite (AccessWidth32, IOCFC, &PciData, StdHeader);      }    }  }}

/** * Ids Write PCI register to All node * * * @param[in] PciAddress    Pci address * @param[in]   Highbit       High bit position of the field in DWORD * @param[in]   Lowbit        Low bit position of the field in DWORD * @param[in] Value         Pointer to input value * @param[in] StdHeader     Standard configuration header * */VOIDIdsLibPciWriteBitsToAllNode (  IN       PCI_ADDR PciAddress,  IN       UINT8 Highbit,  IN       UINT8 Lowbit,  IN       UINT32 *Value,  IN OUT   AMD_CONFIG_PARAMS *StdHeader  ){  UINT32 Socket;  UINT32 Module;  AGESA_STATUS IgnoreStatus;  PCI_ADDR PciAddr;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {      if (GetPciAddress (StdHeader, Socket, Module, &PciAddr, &IgnoreStatus)) {        PciAddr.Address.Function = PciAddress.Address.Function;        PciAddr.Address.Register = PciAddress.Address.Register;        LibAmdPciWriteBits (PciAddr, Highbit, Lowbit, Value, StdHeader);      }    }  }}

/** *  Check to see if the input CPU supports HT Assist. * * @param[in]    HtAssistServices    HT Assist family services. * @param[in]    Socket              Processor socket to check. * @param[in]    StdHeader           Config Handle for library, services. * * @retval       TRUE               HT Assist is supported. * @retval       FALSE              HT Assist cannot be enabled. * */BOOLEANSTATICF10IsHtAssistSupported (  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,  IN       UINT32 Socket,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT32       Module;  UINT32       PciRegister;  BOOLEAN      IsSupported;  PCI_ADDR     PciAddress;  AGESA_STATUS IgnoredStatus;  IsSupported = FALSE;  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {      PciAddress.Address.Function = FUNC_3;      PciAddress.Address.Register = NB_CAPS_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);      if (((NB_CAPS_REGISTER *) &PciRegister)->L3Capable == 1) {        IsSupported = TRUE;      }      break;    }  }  return IsSupported;}

/** * This routine checks whether any non-coherent links in the system * runs in HT1 mode; used to determine whether certain features * should be disabled when this routine returns TRUE. * * @param[in]      StdHeader  Standard AMD configuration parameters. * * @retval         TRUE       One of the non-coherent links in the *                            system runs in HT1 mode * @retval         FALSE      None of the non-coherent links in the *                            system is running in HT1 mode */BOOLEANIsNonCoherentHt1 (  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINTN                 Link;  UINT32                Socket;  UINT32                Module;  PCI_ADDR              PciAddress;  AGESA_STATUS          AgesaStatus;  HT_HOST_FEATS         HtHostFeats;  CPU_SPECIFIC_SERVICES *CpuServices;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetCpuServicesOfSocket (Socket, &CpuServices, StdHeader);      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {        if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {          HtHostFeats.HtHostValue = 0;          Link = 0;          while (CpuServices->GetNextHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader)) {            // Return TRUE and exit routine once we find a non-coherent link in HT1            if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) {              return TRUE;            }          }        }      }    }  }  return FALSE;}

/** * *  InitializeCacheFlushOnHaltFeature * *    CPU feature leveling. Enable Cpu Cache Flush On Halt Function * *    @param[in]       EntryPoint       Timepoint designator. *    @param[in]       PlatformConfig   Contains the runtime modifiable feature input data. *    @param[in,out]   StdHeader        Pointer to AMD_CONFIG_PARAMS struct. * *    @return          The most severe status of any family specific service. */STATIC AGESA_STATUSInitializeCacheFlushOnHaltFeature (  IN       UINT64                 EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN OUT   AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32 Socket;  UINT32 Module;  UINT32 AndMask;  UINT32 OrMask;  UINT32 PciRegister;  PCI_ADDR PciAddress;  PCI_ADDR CfohPciAddress;  AGESA_STATUS AgesaStatus;  CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices;  ASSERT (IsBsp (StdHeader, &AgesaStatus));  FamilySpecificServices = NULL;  AndMask = 0xFFFFFFFF;  OrMask = 0x00000000;  PciRegister = 0;  AgesaStatus = AGESA_SUCCESS;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      // Get services for the socket      GetFeatureServicesOfSocket (&CacheFlushOnHaltFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);      if (FamilySpecificServices != NULL) {        FamilySpecificServices->GetCacheFlushOnHaltRegister (FamilySpecificServices, &CfohPciAddress, &AndMask, &OrMask, StdHeader);        // Get the Or Mask value from IDS        IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);        // Set Cache Flush On Halt register        for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {          if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {            PciAddress.Address.Function = CfohPciAddress.Address.Function;            PciAddress.Address.Register = CfohPciAddress.Address.Register;            LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);            PciRegister &= AndMask;            PciRegister |= OrMask;            LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);          }        }      }    }  }  return AgesaStatus;}

/** * Multisocket call to loop through all possible socket locations and Nb Pstates, * comparing the NB frequencies to determine the slowest system and P0 frequency * * @param[in]  PlatformConfig      Platform profile/build option config structure. * @param[out] MinSysNbFreq        NB frequency numerator for the system in MHz * @param[out] MinP0NbFreq         NB frequency numerator for P0 in MHz * @param[in]  StdHeader           Config handle for library and services */VOIDGetMinNbCofMulti (  IN       PLATFORM_CONFIGURATION *PlatformConfig,     OUT   UINT32                 *MinSysNbFreq,     OUT   UINT32                 *MinP0NbFreq,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32                Socket;  UINT32                Module;  UINT32                CurrMinFreq;  UINT32                CurrMaxFreq;  PCI_ADDR              PciAddress;  AGESA_STATUS          Ignored;  CPU_SPECIFIC_SERVICES *FamilySpecificServices;  AGESA_STATUS AgesaStatus;  *MinSysNbFreq = 0xFFFFFFFF;  *MinP0NbFreq  = 0xFFFFFFFF;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {        if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored )) {          break;        }      }      AgesaStatus = FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices,                                                      PlatformConfig,                                                      &PciAddress,                                                      &CurrMinFreq,                                                      &CurrMaxFreq,                                                      StdHeader);      ASSERT (AgesaStatus == AGESA_SUCCESS);      ASSERT ((CurrMinFreq != 0) && (CurrMaxFreq != 0));      // Determine the slowest NB Pmin frequency      if (CurrMinFreq < *MinSysNbFreq) {        *MinSysNbFreq = CurrMinFreq;      }      // Determine the slowest NB P0 frequency      if (CurrMaxFreq < *MinP0NbFreq) {        *MinP0NbFreq = CurrMaxFreq;      }    }  }}

/** * Family 10h core 0 entry point for performing the necessary steps after * a warm reset has occurred. * * The steps are as follows: *    1. Modify F3xDC[PstateMaxVal] to reflect the lowest performance P-state *       supported, as indicated in MSRC001_00[68:64][PstateEn] *    2. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis] *    3. If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20 *    4. If F3xDC[PstateMaxVal] = 0 or F3xDC[PstateMaxVal] != 4, go to step 7 *    5. If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17 *    6. Exit the sequence *    7. Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state *       register pointed to by F3xDC[PstateMaxVal]+1 *    8. Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal] *    9. Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] *   10. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state *       register pointed to by (the new) F3xDC[PstateMaxVal] *   11. Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd] *   12. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state *       register pointed to by (the new) F3xDC[PstateMaxVal]-1 *   13. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis] *   14. If required, transition the NB COF and VID to the NbDid and NbVid from the *       P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF *       and VID transition sequence after a warm reset *   15. Write MSRC001_00[68:64][PstateEn]=0 for the P-state pointed to by F3xDC[PstateMaxVal] *   16. Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal] and exit the sequence *   17. Copy F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd] *   18. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state *       register pointed to by F3xDC[PstateMaxVal]-1 *   19. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis] *   20. Copy F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] *   21. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state *       register pointed to by F3xDC[PstateMaxVal] *   22. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis] *   23. Issue an LDTSTOP assertion in the IO hub and exit sequence *   24. If required, transition the NB COF and VID to the NbDid and NbVid from the *       P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID *       transition sequence after a warm reset * * @param[in]  FamilySpecificServices  The current Family Specific Services. * @param[in]  CpuEarlyParamsPtr       Service parameters * @param[in]  StdHeader               Config handle for library and services. * */VOIDF10PmAfterReset (  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,  IN       AMD_CONFIG_PARAMS     *StdHeader  ){  UINT32    Socket;  UINT32    Module;  UINT32    PsMaxVal;  UINT32    CoreNum;  UINT32    MsrAddr;  UINT32    Core;  UINT32    AndMask;  UINT32    OrMask;  UINT64    LocalMsrRegister;  PCI_ADDR  PciAddress;  AP_TASK   TaskPtr;  AGESA_STATUS IgnoredSts;  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);  GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);  ASSERT (Core == 0);  // Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance  //        P-state supported, as indicated in MSRC001_00[68:64][PstateEn]  for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) {    LibAmdMsrRead (MsrAddr, &LocalMsrRegister, StdHeader);    if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {      break;    }  }  PsMaxVal = MsrAddr - PS_REG_BASE;  PciAddress.Address.Function = FUNC_3;  PciAddress.Address.Register = CPTC2_REG;  AndMask = 0xFFFFFFFF;  OrMask = 0x00000000;  ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;  ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PsMaxVal;  ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);  // Launch each local core to perform the remaining steps.  TaskPtr.FuncAddress.PfApTask = F10PmAfterResetCore;  TaskPtr.DataTransfer.DataSizeInDwords = 0;  TaskPtr.ExeFlags = WAIT_FOR_CORE;  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);}

/** *  Check to see if the input CPU is running in the optimal configuration. * * @param[in]    HtAssistServices    HT Assist family services. * @param[in]    Socket              Processor socket to check. * @param[in]    StdHeader           Config Handle for library, services. * * @retval       TRUE               HT Assist is running sub-optimally. * @retval       FALSE              HT Assist is running optimally. * */STATIC BOOLEANF10IsNonOptimalConfig (  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,  IN       UINT32 Socket,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  BOOLEAN      IsNonOptimal;  BOOLEAN      IsMemoryPresent;  UINT32       Module;  UINT32       PciRegister;  PCI_ADDR     PciAddress;  AGESA_STATUS IgnoredStatus;  IsNonOptimal = FALSE;  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {      IsMemoryPresent = FALSE;      PciAddress.Address.Function = FUNC_2;      PciAddress.Address.Register = DRAM_CFG_HI_REG0;      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);      if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreqVal == 1) {        IsMemoryPresent = TRUE;        if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreq < 4) {          IsNonOptimal = TRUE;          break;        }      }      PciAddress.Address.Register = DRAM_CFG_HI_REG1;      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);      if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreqVal == 1) {        IsMemoryPresent = TRUE;        if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreq < 4) {          IsNonOptimal = TRUE;          break;        }      }      if (!IsMemoryPresent) {        IsNonOptimal = TRUE;        break;      }    }  }  return IsNonOptimal;}

UINT8PciRead8 (  UINT8   Segment,  UINT8   Bus,  UINT8   DevFunc,  UINT8   Register  )/*++Routine Description:  Perform an one byte PCI config cycle read    Arguments:  Segment   - PCI Segment ACPI _SEG  Bus       - PCI Bus  DevFunc   - PCI Device(7:3) and Func(2:0)  Register  - PCI config space registerReturns:  Data read from PCI config space--*/{  EFI_STATUS  Status;  UINT32      PciAddress;  UINT32      PciAddress1;  UINT8       Data;  PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);  //  // Set bit 31 for PCI config access  //  PciAddress1 = PciAddress;  PciAddress  = ((PciAddress & 0xFFFFFFFC) | (0x80000000));  Status      = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);  if (EFI_ERROR (Status)) {    return 0;  }  EfiIoRead (EfiCpuIoWidthUint8, (PCI_CONFIG_DATA_PORT + (PciAddress1 & 0x3)), 1, &Data);  return Data;}

/** *  Hook before the probe filter initialization sequence. * * @param[in]    HtAssistServices    HT Assist family services. * @param[in]    Socket              Processor socket to check. * @param[in]    StdHeader           Config Handle for library, services. * */VOIDSTATICF10HookBeforeInit (  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,  IN       UINT32 Socket,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT32          Module;  UINT32          PciRegister;  UINT32          PfCtrlRegister;  PCI_ADDR        PciAddress;  CPU_LOGICAL_ID  LogicalId;  AGESA_STATUS    IgnoredStatus;  UINT32          PackageType;  GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);  PackageType = LibAmdGetPackageType (StdHeader);  PciRegister = 0;  ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFWayNum = 2;  ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFSubCacheEn = 15;  ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFLoIndexHashEn = 1;  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {      PciAddress.Address.Function = FUNC_3;      PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);      ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFPreferredSORepl =        ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl;      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);      // Assumption: all socket use the same CPU package.      if (((LogicalId.Revision & AMD_F10_D0) != 0) && (PackageType == PACKAGE_TYPE_C32)) {        // Apply erratum #384        // Set F2x11C[13:12] = 11b        PciAddress.Address.Function = FUNC_2;        PciAddress.Address.Register = 0x11C;        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);        PciRegister |= 0x3000;        LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);      }    }  }}

VOIDPciWrite32 (  UINT8   Segment,  UINT8   Bus,  UINT8   DevFunc,  UINT8   Register,  UINT32  Data  )/*++Routine Description:  Perform an four byte PCI config cycle write    Arguments:  Segment   - PCI Segment ACPI _SEG  Bus       - PCI Bus  DevFunc   - PCI Device(7:3) and Func(2:0)  Register  - PCI config space register  Data      - Data to writeReturns:  NONE--*/{  EFI_STATUS  Status;  UINT32      PciAddress;  UINT32      PciAddress1;  PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);  //  // Set bit 31 for PCI config access  //  PciAddress1 = PciAddress;  PciAddress  = ((PciAddress & 0xFFFFFFFC) | (0x80000000));  Status      = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);  if (EFI_ERROR (Status)) {    return ;  }  EfiIoWrite (EfiCpuIoWidthUint32, (PCI_CONFIG_DATA_PORT + (PciAddress1 & 0x3)), 1, &Data);}

/** *  Save the current settings of the scrubbers, and disabled them. * * @param[in]    HtAssistServices    HT Assist family services. * @param[in]    Socket              Processor socket to check. * @param[in]    ScrubSettings       Location to store current L3 scrubber settings. * @param[in]    StdHeader           Config Handle for library, services. * */VOIDSTATICF10GetL3ScrubCtrl (  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,  IN       UINT32 Socket,  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT32       Module;  UINT32       ScrubCtrl;  UINT32       ScrubAddr;  PCI_ADDR     PciAddress;  AGESA_STATUS IgnoredStatus;  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {      ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);      PciAddress.Address.Function = FUNC_3;      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);      PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub =        ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub;      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub =        ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub;      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect =        ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn;      ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0;      ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0;      ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0;      LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;      LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);    }  }}

/** *  Enable the Probe filter feature. * * @param[in]    HtAssistServices    HT Assist family services. * @param[in]    Socket              Processor socket to check. * @param[in]    StdHeader           Config Handle for library, services. * */VOIDSTATICF10HtAssistInit (  IN       HT_ASSIST_FAMILY_SERVICES  *HtAssistServices,  IN       UINT32  Socket,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32                     Module;  UINT32                     PciRegister;  PCI_ADDR                   PciAddress;  AGESA_STATUS               IgnoredStatus;  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {      PciAddress.Address.Function = FUNC_3;      PciAddress.Address.Register = L3_CACHE_PARAM_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);      ((L3_CACHE_PARAM_REGISTER *) &PciRegister)->L3TagInit = 1;      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);      do {        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);      } while (((L3_CACHE_PARAM_REGISTER *) &PciRegister)->L3TagInit != 0);      PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);      ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFMode = 0;      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);      F10RevDProbeFilterCritical (PciAddress, PciRegister);      do {        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);      } while (((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFInitDone != 1);      IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader);    }  }}

AGESA_STATUSAmdMemRecovery (  IN OUT   MEM_DATA_STRUCT *MemPtr  ){  UINT8 Socket;  UINT8 Module;  UINT8 i;  AGESA_STATUS AgesaStatus;  PCI_ADDR Address;  MEM_NB_BLOCK NBBlock;  MEM_TECH_BLOCK TechBlock;  LOCATE_HEAP_PTR  SocketWithMem;  ALLOCATE_HEAP_PARAMS AllocHeapParams;  //  // Read SPD data  //  MemRecSPDDataProcess (MemPtr);  //  // Get the socket id from heap.  //  SocketWithMem.BufferHandle = AMD_REC_MEM_SOCKET_HANDLE;  if (HeapLocateBuffer (&SocketWithMem, &MemPtr->StdHeader) == AGESA_SUCCESS) {    Socket = *(UINT8 *) SocketWithMem.BufferPtr;  } else {    ASSERT(FALSE);  // Socket handle not found    return AGESA_FATAL;  }  //  // Allocate buffer for memory init structures  //  AllocHeapParams.RequestedBufferSize = MAX_DIES_PER_SOCKET * sizeof (DIE_STRUCT);  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0);  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {    ASSERT(FALSE); // Heap allocation failed to allocate Die struct    return AGESA_FATAL;  }  MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr;  //  // Discover populated CPUs  //  for (Module = 0; Module < MAX_DIES_PER_SOCKET; Module++) {    if (GetPciAddress ((VOID *)MemPtr, Socket, Module, &Address, &AgesaStatus)) {      MemPtr->DiesPerSystem[Module].SocketId = Socket;      MemPtr->DiesPerSystem[Module].DieId = Module;      MemPtr->DiesPerSystem[Module].PciAddr.AddressValue = Address.AddressValue;    }  }  i = 0;  while (MemRecNBInstalled[i] != NULL) {    if (MemRecNBInstalled[i] (&NBBlock, MemPtr, 0) == TRUE) {      break;    }    i++;  };  if (MemRecNBInstalled[i] == NULL) {    ASSERT(FALSE);    // No NB installed    return AGESA_FATAL;  }  MemRecTechInstalled[0] (&TechBlock, &NBBlock);  NBBlock.TechPtr = &TechBlock;  return NBBlock.InitRecovery (&NBBlock);}

/** * * * MemSocketScan - Scan all nodes, recording the physical Socket number, * Die Number (relative to the socket), and PCI Device address of each * populated socket. * * This information is used by the northbridge block to map a dram * channel on a particular DCT, on a particular CPU Die, in a particular * socket to a the DRAM SPD Data for the DIMMS physically connected to * that channel. * * Also, the customer socket map is populated with pointers to the * appropriate channel structures, so that the customer can locate the * appropriate channel configuration data. * * This socket scan will always result in Die 0 as the BSP. * *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK * */AGESA_STATUSMemSocketScan (  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr  ){  MEM_DATA_STRUCT *MemPtr;  UINT8 DieIndex;  UINT8 DieCount;  UINT32 SocketId;  UINT32 DieId;  UINT8 Die;  PCI_ADDR Address;  AGESA_STATUS AgesaStatus;  ALLOCATE_HEAP_PARAMS AllocHeapParams;  ASSERT (mmPtr != NULL);  ASSERT (mmPtr->MemPtr != NULL);  MemPtr = mmPtr->MemPtr;  //  //  Count the number of dies in the system  //  DieCount = 0;  for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) {    if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) {      DieCount++;    }  }  MemPtr->DieCount = DieCount;  mmPtr->DieCount = DieCount;  if (DieCount > 0) {    //    //  Allocate buffer for DIE_STRUCTs    //    AllocHeapParams.RequestedBufferSize = ((UINT16)DieCount * sizeof (DIE_STRUCT));    AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0);    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;    if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {      MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr;      //      //  Find SocketId, DieId, and PCI address of each node      //      DieIndex = 0;      for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) {        if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) {          if (GetPciAddress ((VOID *)MemPtr, (UINT8)SocketId, (UINT8)DieId, &Address, &AgesaStatus)) {            MemPtr->DiesPerSystem[DieIndex].SocketId = (UINT8)SocketId;            MemPtr->DiesPerSystem[DieIndex].DieId = (UINT8)DieId;            MemPtr->DiesPerSystem[DieIndex].PciAddr.AddressValue = Address.AddressValue;            DieIndex++;          }        }      }      AgesaStatus = AGESA_SUCCESS;    } else {      ASSERT(FALSE); // Heap allocation failed for DIE_STRUCTs      AgesaStatus = AGESA_FATAL;    }  } else {    ASSERT(FALSE); // No die in the system    AgesaStatus = AGESA_FATAL;  }  return AgesaStatus;}

/** * Family 10h core 0 entry point for performing power plane initialization. * * The steps are as follows: *    1. If single plane, program lower VID code of CpuVid & NbVid for all *       enabled P-States. *    2. Configure F3xA0[SlamMode] & F3xD8[VsRampTime & VsSlamTime] based on *       platform requirements. *    3. Configure F3xD4[PowerStepUp & PowerStepDown] *    4. Optionally configure F3xA0[PsiVidEn & PsiVid] * * @param[in]  FamilySpecificServices  The current Family Specific Services. * @param[in]  CpuEarlyParams          Service parameters * @param[in]  StdHeader               Config handle for library and services. * */VOIDF10CpuAmdPmPwrPlaneInit (  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,  IN       AMD_CONFIG_PARAMS     *StdHeader  ){  BOOLEAN   PviModeFlag;  PCI_ADDR  PciAddress;  UINT16    PowerStepTime;  UINT32    PowerStepEncoded;  UINT32    PciRegister;  UINT32    VsSlamTime;  UINT32    Socket;  UINT32    Module;  UINT32    Core;  UINT32    NumOfCores;  UINT32    LowCore;  UINT32    AndMask;  UINT32    OrMask;  UINT64    MsrRegister;  AP_TASK   TaskPtr;  AGESA_STATUS  IgnoredSts;  PLATFORM_FEATS Features;  CPU_LOGICAL_ID LogicalId;  // Initialize the union  Features.PlatformValue = 0;  GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader);  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);  ASSERT (Core == 0);  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);  // Set SlamVidMode  PciAddress.Address.Function = FUNC_3;  PciAddress.Address.Register = PW_CTL_MISC_REG;  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);  AndMask = 0xFFFFFFFF;  OrMask = 0x00000000;  if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {    PviModeFlag = TRUE;    ((POWER_CTRL_MISC_REGISTER *) &AndMask)->SlamVidMode = 0;    // Have all single plane cores adjust their NB and CPU VID fields    TaskPtr.FuncAddress.PfApTask = F10PmPwrPlaneInitPviCore;    TaskPtr.DataTransfer.DataSizeInDwords = 0;    TaskPtr.ExeFlags = WAIT_FOR_CORE;    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);  } else {    PviModeFlag = FALSE;    ((POWER_CTRL_MISC_REGISTER *) &OrMask)->SlamVidMode = 1;  }  ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);  F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);  // Configure PowerStepUp/PowerStepDown  PciAddress.Address.Register = CPTC0_REG;  if ((Features.PlatformFeatures.PlatformSingleLink == 1) ||      (Features.PlatformFeatures.PlatformUma == 1) ||      (Features.PlatformFeatures.PlatformUmaIfcm == 1) ||      (Features.PlatformFeatures.PlatformIfcm == 1) ||      (Features.PlatformFeatures.PlatformIommu == 1)) {    PowerStepEncoded = 0x8;  } else {    GetGivenModuleCoreRange ((UINT32) Socket,                             (UINT32) Module,                             &LowCore,                             &NumOfCores,                             StdHeader);    NumOfCores = ((NumOfCores - LowCore) + 1);    PowerStepTime = (UINT16) (400 / NumOfCores);    for (PowerStepEncoded = 0xF; PowerStepEncoded > 0; PowerStepEncoded--) {      if (PowerStepTime <= PowerStepEncodings[PowerStepEncoded]) {        break;      }    }  }  AndMask = 0xFFFFFFFF;//.........这里部分代码省略.........

/** * Set down core register on Mullins * * This function set F3x190 Downcore Control Register[5:0] * * @param[in]   FamilySpecificServices   The current Family Specific Services. * @param[in]   Socket                   Socket ID. * @param[in]   Module                   Module ID in socket. * @param[in]   LeveledCores             Number of core. * @param[in]   CoreLevelMode            Core level mode. * @param[in]   StdHeader                Header for library and services. * * @retval      TRUE                     Down Core register is updated. * @retval      FALSE                    Down Core register is not updated. */BOOLEANF16MlSetDownCoreRegister (    IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,    IN       UINT32 *Socket,    IN       UINT32 *Module,    IN       UINT32 *LeveledCores,    IN       CORE_LEVELING_TYPE CoreLevelMode,    IN       AMD_CONFIG_PARAMS *StdHeader){    UINT8     NumOfComputeUnit;    UINT8     CoresPerComputeUnit;    UINT32    LocalPciRegister;    UINT32    CoreDisableBits;    UINT32    TempVar32_a;    PCI_ADDR  PciAddress;    BOOLEAN   IsUpdated;    AGESA_STATUS AgesaStatus;    IsUpdated = FALSE;    CoreDisableBits = 0;    TempVar32_a = 1;    CoresPerComputeUnit = 1;    switch (CoreLevelMode) {    // There's no 'break' except 'case CORE_LEVEL_COMPUTE_UNIT'.    // It's for generating CoreDisableBits and CoresPerComputeUnit    case CORE_LEVEL_COMPUTE_UNIT_THREE:        TempVar32_a = TempVar32_a << 1;        CoresPerComputeUnit++;    case CORE_LEVEL_COMPUTE_UNIT_TWO:        TempVar32_a = TempVar32_a << 1;        CoresPerComputeUnit++;    case CORE_LEVEL_COMPUTE_UNIT:        TempVar32_a = (TempVar32_a << 1) - 1;        TempVar32_a = FOUR_CORE_COMPUTE_UNIT_BITMAP & (~TempVar32_a);        NumOfComputeUnit = (UINT8) ((*LeveledCores) / CoresPerComputeUnit);        for (CoreDisableBits = 0; NumOfComputeUnit > 0; NumOfComputeUnit--) {            CoreDisableBits <<= FOUR_CORE_COMPUTE_UNIT_BITWIDTH;            CoreDisableBits |= TempVar32_a;        }        break;    default:        TempVar32_a = *LeveledCores;        if (TempVar32_a == 1) {            CoreDisableBits = DOWNCORE_MASK_SINGLE;        } else {            CoreDisableBits = ALL_CORES_DISABLE_BITMAP;            TempVar32_a = ((1 << TempVar32_a) - 1);            CoreDisableBits &= ~TempVar32_a;        }    }    if (CoreDisableBits != 0) {        if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {            PciAddress.Address.Function = FUNC_5;            PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_2_REG;            LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);            LocalPciRegister = (LocalPciRegister & 0xFF) + 1;            LocalPciRegister = (1 << LocalPciRegister) - 1;            CoreDisableBits &= LocalPciRegister;            PciAddress.Address.Function = FUNC_3;            PciAddress.Address.Register = DOWNCORE_CTRL;            LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);            if ((LocalPciRegister | CoreDisableBits) != LocalPciRegister) {                LocalPciRegister |= CoreDisableBits;                LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);                IsUpdated = TRUE;            }        }    }    return IsUpdated;}

//.........这里部分代码省略.........      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddValue = TempVar_a;      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddDiv = TempVar_b;    }    // 2_a)    if (!AllCoreHaveMaxOnePStateFlag) {      //--------------------------------------------------------------------------      // STEP - 3      //--------------------------------------------------------------------------      // Match the CPU COF and power for P-states used by HTC. Skip to step 4      // is any processor reports F3xE8[HTC_Capable] = 0;      // 3_a) Set F3x64[HtcPstateLimit] = 001b and F3x68[StcPstateLimit] = 001b for      //      processors with F3x64[HtcPstateLimit] = 000b.      // 3_b) Identify the lowest CPU COF for all processors in the P-state      //      pointed to by [The Hardware Thermal Control (HTC) Register]      //      F3x64[HtcPstateLimit]      // 3_c) Modify the CPU COF pointed to by [The Hardware Thermal Control      //      (HTC) Register] F3x64[HtcPstateLimit] for all processors to the      //      previously identified lowest CPU COF value.      // 3_d) Identify the highest power for all processors in the P-state      //      pointed to by [The Hardware Thermal Control (HTC) Register]      //      F3x64[HtcPstateLimit].      // 3_e) Modify the power pointed to by [The Hardware Thermal Control (HTC)      //      Register] F3x64[HtcPstateLimit] to the previously identified      //      highest power value.      if (!AllCoresHaveHtcCapEquToZeroFlag) {        // 3_a)        for (i = 0; i < LogicalSocketCount; i++) {          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);          if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 0) {            // To Be Done (Set Htc and Stc PstateLimit values)            // for this CPU (using PCI address space)            for (k = 0; k < (UINT8)GetPlatformNumberOfModules (); k++) {              if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, k, &PciAddress, &Status)) {                // Set F3x64[HtcPstateLimit] = 001b                PciAddress.Address.Function = FUNC_3;                PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG;                LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);                // Bits 30:28                TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000;                LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);                // Set F3x68[StcPstateLimit] = 001b                PciAddress.Address.Register = SOFTWARE_THERMAL_CTRL_REG;                LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);                // Bits 28:30                TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000;                LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);              }            }            // Set LocalBuffer            PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit = 1;            if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1) < 2) {              PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE;            }            if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 1) {              PstateMaxValEquToPstateHtcLimitFlag = TRUE;            }          }          if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) {            AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE;          }        }

/** * Multisocket call to determine the frequency that the northbridges must run. * * This function loops through all possible socket locations, comparing the * maximum NB frequencies to determine the slowest.  This function also * determines if all coherent NB frequencies are equivalent. * * @param[in]  NbPstate                    NB P-state number to check (0 = fastest) * @param[in]  PlatformConfig              Platform profile/build option config structure. * @param[out] SystemNbCofNumerator        NB frequency numerator for the system in MHz * @param[out] SystemNbCofDenominator      NB frequency denominator for the system * @param[out] SystemNbCofsMatch           Whether or not all NB frequencies are equivalent * @param[out] NbPstateIsEnabledOnAllCPUs  Whether or not NbPstate is valid on all CPUs * @param[in]  StdHeader                   Config handle for library and services * * @retval     TRUE                        At least one processor has NbPstate enabled. * @retval     FALSE                       NbPstate is disabled on all CPUs * */BOOLEANGetSystemNbCofMulti (  IN       UINT32 NbPstate,  IN       PLATFORM_CONFIGURATION *PlatformConfig,     OUT   UINT32 *SystemNbCofNumerator,     OUT   UINT32 *SystemNbCofDenominator,     OUT   BOOLEAN *SystemNbCofsMatch,     OUT   BOOLEAN *NbPstateIsEnabledOnAllCPUs,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT32   Socket;  UINT8    Module;  UINT32   CurrentNbCof;  UINT32   CurrentDivisor;  UINT32   CurrentFreq;  UINT32   LowFrequency;  UINT32   Ignored32;  BOOLEAN  FirstCofNotFound;  BOOLEAN  NbPstateDisabled;  BOOLEAN  IsNbPstateEnabledOnAny;  PCI_ADDR PciAddress;  AGESA_STATUS Ignored;  CPU_SPECIFIC_SERVICES *FamilySpecificServices;  // Find the slowest NB COF in the system & whether or not all are equivalent  LowFrequency = 0xFFFFFFFF;  *SystemNbCofsMatch = TRUE;  *NbPstateIsEnabledOnAllCPUs = FALSE;  IsNbPstateEnabledOnAny = FALSE;  FirstCofNotFound = TRUE;  NbPstateDisabled = FALSE;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {        if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored)) {          break;        }      }      if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,                                                   PlatformConfig,                                                   &PciAddress,                                                   NbPstate,                                                   &CurrentNbCof,                                                   &CurrentDivisor,                                                   &Ignored32,                                                   StdHeader)) {        ASSERT (CurrentDivisor != 0);        CurrentFreq = (CurrentNbCof / CurrentDivisor);        if (FirstCofNotFound) {          *SystemNbCofNumerator = CurrentNbCof;          *SystemNbCofDenominator = CurrentDivisor;          LowFrequency = CurrentFreq;          IsNbPstateEnabledOnAny = TRUE;          if (!NbPstateDisabled) {            *NbPstateIsEnabledOnAllCPUs = TRUE;          }          FirstCofNotFound = FALSE;        } else {          if (CurrentFreq != LowFrequency) {            *SystemNbCofsMatch = FALSE;            if (CurrentFreq < LowFrequency) {              LowFrequency = CurrentFreq;              *SystemNbCofNumerator = CurrentNbCof;              *SystemNbCofDenominator = CurrentDivisor;            }          }        }      } else {        NbPstateDisabled = TRUE;        *NbPstateIsEnabledOnAllCPUs = FALSE;      }    }  }  return IsNbPstateEnabledOnAny;}

/** *  Save and Restore or Initialize the content of the mailbox registers. * * The registers used for AP mailbox should have the content related to their function * preserved. * * @param[in]    EntryPoint         Timepoint designator. * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @return       AGESA_SUCCESS      Always succeeds. * */AGESA_STATUSSTATICPreserveMailboxes (  IN       UINT64                 EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices;  UINT32 Socket;  UINT32 Module;  PCI_ADDR BaseAddress;  PCI_ADDR MailboxRegister;  PCI_ADDR *NextRegister;  AGESA_STATUS IgnoredStatus;  AGESA_STATUS HeapStatus;  UINT32 Value;  ALLOCATE_HEAP_PARAMS AllocateParams;  LOCATE_HEAP_PTR LocateParams;  UINT32 RegisterEntryIndex;  BaseAddress.AddressValue = ILLEGAL_SBDFO;  if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) {    // The save step.  Save either the register content or zero (for cold boot, if family specifies that).    AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;    AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES)));    AllocateParams.Persist = HEAP_SYSTEM_MEM;    HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader);    ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL));    LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader);    RegisterEntryIndex = 0;    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {        if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {          GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);          ASSERT (FamilySpecificServices != NULL);          NextRegister = FamilySpecificServices->RegisterList;          while (NextRegister->AddressValue != ILLEGAL_SBDFO) {            ASSERT (RegisterEntryIndex <                    (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));            if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) {              Value = 0;            } else {              MailboxRegister = BaseAddress;              MailboxRegister.Address.Function = NextRegister->Address.Function;              MailboxRegister.Address.Register = NextRegister->Address.Register;              LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader);            }            (* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value;            RegisterEntryIndex++;            NextRegister++;          }        }      }    }  } else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) {    // The restore step.  Just write out the saved content in the buffer.    LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;    HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader);    ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL));    RegisterEntryIndex = 0;    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {        if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {          GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);          NextRegister = FamilySpecificServices->RegisterList;          while (NextRegister->AddressValue != ILLEGAL_SBDFO) {            ASSERT (RegisterEntryIndex <                    (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));            MailboxRegister = BaseAddress;            MailboxRegister.Address.Function = NextRegister->Address.Function;            MailboxRegister.Address.Register = NextRegister->Address.Register;            Value = (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex];            LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader);            RegisterEntryIndex++;            NextRegister++;          }        }      }    }    HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader);  }  return AGESA_SUCCESS;}

/** * Set down core register on Orochi * * This function set F3x190 Downcore Control Register[5:0] * * @param[in]   FamilySpecificServices   The current Family Specific Services. * @param[in]   Socket                   Socket ID. * @param[in]   Module                   Module ID in socket. * @param[in]   LeveledCores             Number of core. * @param[in]   CoreLevelMode            Core level mode. * @param[in]   StdHeader                Header for library and services. * * @retval      TRUE                     Down Core register is updated. * @retval      FALSE                    Down Core register is not updated. */BOOLEANF15OrSetDownCoreRegister (  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,  IN       UINT32 *Socket,  IN       UINT32 *Module,  IN       UINT32 *LeveledCores,  IN       CORE_LEVELING_TYPE CoreLevelMode,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT8     Xbar2SriFreeListCBC;  UINT8     L3FreeListCBC;  UINT32    TempVar32_a;  UINT32    CoreDisableBits;  UINT32    NumberOfEnabledCores;  UINT32    NumberOfEnabledCU;  PCI_ADDR  PciAddress;  BOOLEAN   IsUpdated;  AGESA_STATUS                    AgesaStatus;  NB_CAPS_REGISTER                NbCaps;  FREE_LIST_BUFFER_COUNT_REGISTER FreeListBufferCount;  L3_BUFFER_COUNT_REGISTER        L3BufferCnt;  IsUpdated = FALSE;  if (CoreLevelMode == CORE_LEVEL_COMPUTE_UNIT) {    switch (*LeveledCores) {    case 1:      CoreDisableBits = DOWNCORE_MASK_SINGLE;      break;    case 2:      CoreDisableBits = DOWNCORE_MASK_DUAL_COMPUTE_UNIT;      break;    case 3:      CoreDisableBits = DOWNCORE_MASK_TRI_COMPUTE_UNIT;      break;    case 4:      CoreDisableBits = DOWNCORE_MASK_FOUR_COMPUTE_UNIT;      break;    default:      CoreDisableBits = 0;      break;    }  } else {    switch (*LeveledCores) {    case 1:      CoreDisableBits = DOWNCORE_MASK_SINGLE;      break;    case 2:      CoreDisableBits = DOWNCORE_MASK_DUAL;      break;    case 4:      CoreDisableBits = DOWNCORE_MASK_FOUR;      break;    case 6:      CoreDisableBits = DOWNCORE_MASK_SIX;      break;    default:      CoreDisableBits = 0;      break;    }  }  if (CoreDisableBits != 0) {    if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {      PciAddress.Address.Function = FUNC_5;      PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_2_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);      TempVar32_a = (TempVar32_a & 0xFF) + 1;      TempVar32_a = (1 << TempVar32_a) - 1;      CoreDisableBits &= TempVar32_a;      NumberOfEnabledCores = ~(CoreDisableBits | ~(TempVar32_a));      PciAddress.Address.Function = FUNC_3;      PciAddress.Address.Register = DOWNCORE_CTRL;      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);      if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {        TempVar32_a |= CoreDisableBits;        LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);        IsUpdated = TRUE;        for (NumberOfEnabledCU = 0; NumberOfEnabledCores != 0; NumberOfEnabledCores >>= 2) {          NumberOfEnabledCU += ((NumberOfEnabledCores & 3) != 0) ? 1 : 0;        }//.........这里部分代码省略.........

/** * Restores the context of a 'conditional' PCI device. * * This traverses the provided register list restoring PCI registers when appropriate. * * @param[in]     StdHeader      AMD standard header config param. * @param[in]     Device         'conditional' PCI device to restore. * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or *                               AMD_S3LATE_RESTORE. * @param[in,out] OrMask         Current buffer pointer of raw register values. * */VOIDRestoreConditionalPciDevice (  IN       AMD_CONFIG_PARAMS                 *StdHeader,  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,  IN       CALL_POINTS                       CallPoint,  IN OUT   VOID                              **OrMask  ){  UINT8   RegSizeInBytes;  UINT8   SpecialCaseIndex;  UINT8   *IntermediatePtr;  UINT8   BootMode;  UINT16  i;  UINT32  Socket;  UINT32  Module;  UINT32  RegValueRead;  UINT32  RegValueWrite;  UINT32  AndMask;  ACCESS_WIDTH AccessWidth;  AGESA_STATUS IgnoredSts;  PCI_ADDR PciAddress;  CPCI_REGISTER_BLOCK_HEADER *RegisterHdr;  GetSocketModuleOfNode ((UINT32) Device->Node,                               &Socket,                               &Module,                               StdHeader);  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);  if (CallPoint == INIT_RESUME) {    MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);  } else {    S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);  }  BootMode = S3_RESUME_MODE;  if (StdHeader->Func == AMD_INIT_POST) {    BootMode = RESTORE_TRAINING_MODE | CAPSULE_REBOOT_MODE;  }  for (i = 0; i < RegisterHdr->NumRegisters; i++) {    if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&        ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {      PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;      PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;      RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;      switch (RegSizeInBytes) {      case 1:        AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);        RegValueWrite = **(UINT8 **)OrMask;        AccessWidth = AccessS3SaveWidth8;        break;      case 2:        AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);        RegValueWrite = **(UINT16 **)OrMask;        AccessWidth = AccessS3SaveWidth16;        break;      case 3:        // In this case, we don't need to restore a register. We just need to call a special        //  function to do certain things in the save and resume sequence.        // This should not be used in a non-special case.        AndMask = 0;        RegValueWrite = 0;        RegSizeInBytes = 0;        AccessWidth = 0;        break;      default:        AndMask = RegisterHdr->RegisterList[i].AndMask;        RegSizeInBytes = 4;        RegValueWrite = **(UINT32 **)OrMask;        AccessWidth = AccessS3SaveWidth32;        break;      }      if ((RegisterHdr->RegisterList[i].BootMode == 0) || ((BootMode & RegisterHdr->RegisterList[i].BootMode) != 0)) {        // Do not restore the register if not in the right boot mode        // Pointer to the saved data buffer still needs to be adjusted as data will be saved regardless of boot mode        if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {          LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader);          RegValueWrite |= RegValueRead & (~AndMask);          LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader);        } else {          SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;          if (AndMask != 0) {            RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth,                                               PciAddress,                                               &RegValueRead,                                               StdHeader);            RegValueWrite |= RegValueRead & (~AndMask);//.........这里部分代码省略.........

/** *  Should message-based C1e be enabled * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               Message-based C1e is supported. * @retval       FALSE              Message-based C1e cannot be enabled. * */BOOLEANSTATICIsMsgBasedC1eFeatureEnabled (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINTN                         Link;  UINTN                         LinkCount;  UINT32                        Socket;  UINT32                        Module;  BOOLEAN                       IsEnabled;  PCI_ADDR                      PciAddress;  AGESA_STATUS                  AgesaStatus;  HT_HOST_FEATS                 HtHostFeats;  CPU_SPECIFIC_SERVICES         *CpuServices;  MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;  ASSERT (PlatformConfig->C1eMode < MaxC1eMode);  IsEnabled = FALSE;  if (PlatformConfig->C1eMode == C1eModeMsgBased) {    ASSERT (PlatformConfig->C1ePlatformData < 0x10000);    ASSERT (PlatformConfig->C1ePlatformData != 0);    if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) {      IsEnabled = TRUE;      for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {        if (IsProcessorPresent (Socket, StdHeader)) {          GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);          if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) {            IsEnabled = FALSE;            break;          } else {            // If the CPU revision supports message-based C1e, check whether the feature should            // be disabled based on the speed of ncHT links (HT1).            GetCpuServicesOfSocket (Socket, &CpuServices, StdHeader);            for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {              if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {                HtHostFeats.HtHostValue = 0;                for (LinkCount = 0; LinkCount < 8; LinkCount++) {                  if (FindHtHostCapability (LinkCount, &PciAddress, StdHeader)) {                    CpuServices->GetHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader);                    if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) {                      IsEnabled = FALSE;                      break;                    }                  }                }              }              // Exit for (Module = 0; Module < GetPlatformNumberOfModules; Module++)              if (!IsEnabled) {                break;              }            }          }        }        // Exit for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++)        if (!IsEnabled) {          break;        }      }    }  }  return IsEnabled;}

/** * Saves the context of a 'conditional' PCI device. * * This traverses the provided register list saving PCI registers when appropriate. * * @param[in]     StdHeader      AMD standard header config param. * @param[in]     Device         'conditional' PCI device to restore. * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or *                               AMD_S3LATE_RESTORE. * @param[in,out] OrMask         Current buffer pointer of raw register values. * */VOIDSaveConditionalPciDevice (  IN       AMD_CONFIG_PARAMS                 *StdHeader,  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,  IN       CALL_POINTS                       CallPoint,  IN OUT   VOID                              **OrMask  ){  UINT8   RegSizeInBytes;  UINT8   SpecialCaseIndex;  UINT8   *IntermediatePtr;  UINT16  i;  UINT32  Socket;  UINT32  Module;  UINT32  AndMask;  ACCESS_WIDTH AccessWidth;  AGESA_STATUS IgnoredSts;  PCI_ADDR PciAddress;  CPCI_REGISTER_BLOCK_HEADER *RegisterHdr;  GetSocketModuleOfNode ((UINT32) Device->Node,                               &Socket,                               &Module,                               StdHeader);  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);  if (CallPoint == INIT_RESUME) {    MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);  } else {    S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);  }  for (i = 0; i < RegisterHdr->NumRegisters; i++) {    if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&        ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {      PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;      PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;      RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;      switch (RegSizeInBytes) {      case 1:        AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);        AccessWidth = AccessS3SaveWidth8;        break;      case 2:        AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);        AccessWidth = AccessS3SaveWidth16;        break;      case 3:        // In this case, we don't need to save a register. We just need to call a special        // function to do certain things in the save and resume sequence.        // This should not be used in a non-special case.        AndMask = 0;        RegSizeInBytes = 0;        AccessWidth = 0;        break;      default:        AndMask = RegisterHdr->RegisterList[i].AndMask;        RegSizeInBytes = 4;        AccessWidth = AccessS3SaveWidth32;        break;      }      if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {        ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0));        LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader);      } else {        SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;        RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader);      }      if (AndMask != 0) {        // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask        **((UINT32 **) OrMask) &= AndMask;      }      if ((RegSizeInBytes == 0) && (**((UINT32 **) OrMask) == RESTART_FROM_BEGINNING_LIST)) {        // Restart from the beginning of the register list        i = 0xFFFF;      }      IntermediatePtr = (UINT8 *) *OrMask;      *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;    }  }}

/** * Restores the context of a PCI device. * * This traverses the provided register list restoring PCI registers. * * @param[in]     StdHeader      AMD standard header config param. * @param[in]     Device         'conditional' PCI device to restore. * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or *                               AMD_S3LATE_RESTORE. * @param[in,out] OrMask         Current buffer pointer of raw register values. * */VOIDRestorePciDevice (  IN       AMD_CONFIG_PARAMS     *StdHeader,  IN       PCI_DEVICE_DESCRIPTOR *Device,  IN       CALL_POINTS           CallPoint,  IN OUT   VOID                  **OrMask  ){  UINT8   RegSizeInBytes;  UINT8   SpecialCaseIndex;  UINT8   *IntermediatePtr;  UINT16  i;  UINT32  Socket;  UINT32  Module;  UINT32  AndMask;  UINT32  RegValueRead;  UINT32  RegValueWrite;  ACCESS_WIDTH AccessWidth;  AGESA_STATUS IgnoredSts;  PCI_ADDR PciAddress;  PCI_REGISTER_BLOCK_HEADER *RegisterHdr;  GetSocketModuleOfNode ((UINT32) Device->Node,                               &Socket,                               &Module,                               StdHeader);  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);  if (CallPoint == INIT_RESUME) {    MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);  } else {    S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);  }  for (i = 0; i < RegisterHdr->NumRegisters; i++) {    PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;    PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;    RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;    switch (RegSizeInBytes) {    case 1:      AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);      RegValueWrite = **(UINT8 **)OrMask;      AccessWidth = AccessS3SaveWidth8;      break;    case 2:      AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);      RegValueWrite = **(UINT16 **)OrMask;      AccessWidth = AccessS3SaveWidth16;      break;    case 3:      // In this case, we don't need to restore a register. We just need to call a special      // function to do certain things in the save and resume sequence.      // This should not be used in a non-special case.      AndMask = 0;      RegValueWrite = 0;      RegSizeInBytes = 0;      AccessWidth = 0;      break;    default:      AndMask = RegisterHdr->RegisterList[i].AndMask;      RegSizeInBytes = 4;      RegValueWrite = **(UINT32 **)OrMask;      AccessWidth = AccessS3SaveWidth32;      break;    }    if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {      ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0));      LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader);      RegValueWrite |= RegValueRead & (~AndMask);      LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader);    } else {      SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;      if (AndMask != 0) {        RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth,                                             PciAddress,                                             &RegValueRead,                                             StdHeader);        RegValueWrite |= RegValueRead & (~AndMask);      }      RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth,                                             PciAddress,                                             &RegValueWrite,                                             StdHeader);    }    IntermediatePtr = (UINT8 *) *OrMask;    *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;  }}