自学教程：C++ GetPlatformNumberOfSockets函数代码示例

/** *  Should L3 features be enabled * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               L3 Features are supported * @retval       FALSE              L3 Features are not supported * */BOOLEANSTATICIsL3FeatureEnabled (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  BOOLEAN          IsEnabled;  UINT32           Socket;  L3_FEATURE_FAMILY_SERVICES *FamilyServices;  IsEnabled = FALSE;  if (PlatformConfig->PlatformProfile.UseHtAssist ||      PlatformConfig->PlatformProfile.UseAtmMode) {    IsEnabled = TRUE;    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {      if (IsProcessorPresent (Socket, StdHeader)) {        GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (const VOID **) &FamilyServices, StdHeader);        if ((FamilyServices == NULL) || !FamilyServices->IsL3FeatureSupported (FamilyServices, Socket, StdHeader)) {          IsEnabled = FALSE;          break;        }      }    }  }  return IsEnabled;}

/** * Ids Write PCI register to All node * * * @param[in] PciAddress    Pci address * @param[in]   Highbit       High bit position of the field in DWORD * @param[in]   Lowbit        Low bit position of the field in DWORD * @param[in] Value         Pointer to input value * @param[in] StdHeader     Standard configuration header * */VOIDIdsLibPciWriteBitsToAllNode (  IN       PCI_ADDR PciAddress,  IN       UINT8 Highbit,  IN       UINT8 Lowbit,  IN       UINT32 *Value,  IN OUT   AMD_CONFIG_PARAMS *StdHeader  ){  UINT32 Socket;  UINT32 Module;  AGESA_STATUS IgnoreStatus;  PCI_ADDR PciAddr;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {      if (GetPciAddress (StdHeader, Socket, Module, &PciAddr, &IgnoreStatus)) {        PciAddr.Address.Function = PciAddress.Address.Function;        PciAddr.Address.Register = PciAddress.Address.Register;        LibAmdPciWriteBits (PciAddr, Highbit, Lowbit, Value, StdHeader);      }    }  }}

/** *  Should C6 be enabled * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               C6 is supported. * @retval       FALSE              C6 cannot be enabled. * */BOOLEANSTATICIsC6FeatureEnabled (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32             Socket;  BOOLEAN            IsEnabled;  C6_FAMILY_SERVICES *FamilyServices;  IsEnabled = FALSE;  if (PlatformConfig->CStateMode == CStateModeC6) {    IsEnabled = TRUE;    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {      if (IsProcessorPresent (Socket, StdHeader)) {        GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);        if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, PlatformConfig, StdHeader)) {          IsEnabled = FALSE;          break;        }      }    }  }  return IsEnabled;}

/** * Multisocket BSC call to start all system core 0s to perform a standard AP_TASK. * * This function loops through all possible socket locations, starting core 0 of * each populated socket to perform the passed in AP_TASK.  After starting all * other core 0s, the BSC will perform the AP_TASK as well.  This must be run by * the system BSC only. * * @param[in]  TaskPtr           Function descriptor * @param[in]  StdHeader         Config handle for library and services * @param[in]  ConfigParams      AMD entry point's CPU parameter structure * */VOIDRunCodeOnAllSystemCore0sMulti (  IN       AP_TASK *TaskPtr,  IN       AMD_CONFIG_PARAMS *StdHeader,  IN       VOID *ConfigParams  ){  UINT32 BscSocket;  UINT32 BscModule;  UINT32 BscCoreNum;  UINT8  Socket;  UINT32 NumberOfSockets;  AGESA_STATUS DummyStatus;  ASSERT (IsBsp (StdHeader, &DummyStatus));  NumberOfSockets = GetPlatformNumberOfSockets ();  IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus);  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (Socket != BscSocket) {      if (IsProcessorPresent (Socket, StdHeader)) {        ApUtilRunCodeOnSocketCore (Socket, 0, TaskPtr, StdHeader);      }    }  }  ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams);}

/** * Runs the given task on all cores (including self) on the socket of the executing * core 0. * * This function is used to invoke all APs on the socket of the executing core 0 to * run a specified AGESA procedure. * * @param[in]  TaskPtr      Function descriptor * @param[in]  StdHeader    Config handle for library and services * */VOIDIdsApRunCodeOnAllLocalCores (  IN       AP_TASK *TaskPtr,  IN OUT   AMD_CONFIG_PARAMS *StdHeader  ){  UINT32 Core;  UINT32 BscCoreNum;  UINT32 Socket;  UINT32 BscSocket;  UINT32 IgnoredModule;  UINT32 NumberOfCores;  UINT32 NumberOfSockets;  AGESA_STATUS IgnoredSts;  IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts);  NumberOfSockets = GetPlatformNumberOfSockets ();  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {      for (Core = 0; Core < NumberOfCores; Core++) {        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, TaskPtr, StdHeader);        }      }    }  } // BSP codes  ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, NULL);}

/** *  Should Application Power Management (APM) be enabled * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               APM is supported. * @retval       FALSE              APM cannot be enabled. * */STATIC BOOLEANIsApmFeatureEnabled (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32              Socket;  BOOLEAN             IsEnabled;  APM_FAMILY_SERVICES *FamilyServices;  IsEnabled = FALSE;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetFeatureServicesOfSocket (&ApmFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);      if (FamilyServices != NULL) {        if (FamilyServices->IsApmSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {          IsEnabled = TRUE;          break;        }      }    }  }  return IsEnabled;}

/** * *  FeatureLeveling * *    CPU feature leveling. Set least common features set of all CPUs * *    @param[in,out]   StdHeader   - Pointer to AMD_CONFIG_PARAMS struct. * */VOIDFeatureLeveling (  IN OUT   AMD_CONFIG_PARAMS *StdHeader  ){  UINT32 BscSocket;  UINT32 Ignored;  UINT32 BscCoreNum;  UINT32 Socket;  UINT32 Core;  UINT32 NumberOfSockets;  UINT32 NumberOfCores;  BOOLEAN *FirstTime;  BOOLEAN *NeedLeveling;  AGESA_STATUS IgnoredSts;  CPU_FEATURES_LIST *globalCpuFeatureList;  AP_TASK  TaskPtr;  ASSERT (IsBsp (StdHeader, &IgnoredSts));  GetGlobalCpuFeatureListAddress ((UINT64 **) &globalCpuFeatureList, StdHeader);  FirstTime = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST));  NeedLeveling = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN));  *FirstTime = TRUE;  *NeedLeveling = FALSE;  LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader);  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);  NumberOfSockets = GetPlatformNumberOfSockets ();  TaskPtr.FuncAddress.PfApTaskI = SaveFeatures;  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (CPU_FEATURES_LIST);  TaskPtr.ExeFlags = WAIT_FOR_CORE;  TaskPtr.DataTransfer.DataPtr = globalCpuFeatureList;  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      if (Socket !=  BscSocket) {        ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);      }    }  }  ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);  if (*NeedLeveling) {    TaskPtr.FuncAddress.PfApTaskI  = WriteFeatures;    for (Socket = 0; Socket < NumberOfSockets; Socket++) {      if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {        for (Core = 0; Core < NumberOfCores; Core++) {          if ((Socket != BscSocket) || (Core != BscCoreNum)) {            ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);          }        }      }    }    ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);  }}

/** *  Should CPB be enabled * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               CPB is supported. * @retval       FALSE              CPB cannot be enabled. * */BOOLEANSTATICIsCpbFeatureEnabled (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32              Socket;  BOOLEAN             IsEnabled;  CPB_FAMILY_SERVICES *FamilyServices;  IsEnabled = FALSE;  ASSERT (PlatformConfig->CpbMode < MaxCpbMode);  if (PlatformConfig->CpbMode == CpbModeAuto) {    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {      if (IsProcessorPresent (Socket, StdHeader)) {        GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);        if (FamilyServices != NULL) {          if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {            IsEnabled = TRUE;            break;          }        }      }    }  }  return IsEnabled;}

/** *  Should IO Cstate be enabled *  If all processors support IO Cstate, return TRUE. Otherwise, return FALSE * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               IO Cstate is supported. * @retval       FALSE              IO Cstate cannot be enabled. * */BOOLEANSTATICIsIoCstateFeatureSupported (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32                    Socket;  BOOLEAN                   IsSupported;  IO_CSTATE_FAMILY_SERVICES *IoCstateServices;  IsSupported = FALSE;  if ((PlatformConfig->CStateIoBaseAddress != 0) && (PlatformConfig->CStateIoBaseAddress <= 0xFFF8)) {    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {      if (IsProcessorPresent (Socket, StdHeader)) {        GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, (CONST VOID **)&IoCstateServices, StdHeader);        if (IoCstateServices != NULL) {          if (IoCstateServices->IsIoCstateSupported (IoCstateServices, Socket, StdHeader)) {            IsSupported = TRUE;          } else {            // Stop checking remaining socket(s) once we find one that does not support IO Cstates            IsSupported = FALSE;            break;          }        } else {          // Exit the for loop if we found a socket that does not have the IO Cstates feature installed          IsSupported = FALSE;          break;        }      }    }  }  return IsSupported;}

/** * This routine checks whether any non-coherent links in the system * runs in HT1 mode; used to determine whether certain features * should be disabled when this routine returns TRUE. * * @param[in]      StdHeader  Standard AMD configuration parameters. * * @retval         TRUE       One of the non-coherent links in the *                            system runs in HT1 mode * @retval         FALSE      None of the non-coherent links in the *                            system is running in HT1 mode */BOOLEANIsNonCoherentHt1 (  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINTN                 Link;  UINT32                Socket;  UINT32                Module;  PCI_ADDR              PciAddress;  AGESA_STATUS          AgesaStatus;  HT_HOST_FEATS         HtHostFeats;  CPU_SPECIFIC_SERVICES *CpuServices;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetCpuServicesOfSocket (Socket, &CpuServices, StdHeader);      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {        if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {          HtHostFeats.HtHostValue = 0;          Link = 0;          while (CpuServices->GetNextHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader)) {            // Return TRUE and exit routine once we find a non-coherent link in HT1            if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) {              return TRUE;            }          }        }      }    }  }  return FALSE;}

/** * Clear EnableCf8ExtCfg on all socket * * Clear F3x8C bit 14 EnableCf8ExtCfg * * @param[in]  StdHeader         Config handle for library and services * * */VOIDDisableCf8ExtCfg (  IN       AMD_CONFIG_PARAMS   *StdHeader  ){  AGESA_STATUS  AgesaStatus;  PCI_ADDR PciAddress;  UINT32 Socket;  UINT32 Module;  UINT32 PciData;  UINT32 LegacyPciAccess;  ASSERT (IsBsp (StdHeader, &AgesaStatus));  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {      if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {        PciAddress.Address.Function = FUNC_3;        PciAddress.Address.Register = NB_CFG_HIGH_REG;        LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));        // read from PCI register        LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);        LibAmdIoRead (AccessWidth32, IOCFC, &PciData, StdHeader);        // Disable Cf8ExtCfg        PciData &= 0xFFFFBFFF;        // write to PCI register        LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);        LibAmdIoWrite (AccessWidth32, IOCFC, &PciData, StdHeader);      }    }  }}

/** * Multisocket BSC call to determine the maximum number of steps that any single * processor needs to execute. * * This function loops through all possible socket locations, gathering the number * of power management steps each populated socket requires, and returns the * highest number. * * @param[out] NumSystemSteps    Maximum number of system steps required * @param[in]  StdHeader         Config handle for library and services * */VOIDGetNumberOfSystemPmStepsPtrMulti (     OUT   UINT8 *NumSystemSteps,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT8  NumberOfSteps;  UINT32 NumberOfSockets;  UINT32 Socket;  SYS_PM_TBL_STEP *Ignored;  CPU_SPECIFIC_SERVICES *FamilySpecificServices;  NumberOfSockets = GetPlatformNumberOfSockets ();  *NumSystemSteps = 0;  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);      FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &Ignored, &NumberOfSteps, StdHeader);      if (NumberOfSteps > *NumSystemSteps) {        *NumSystemSteps = NumberOfSteps;      }    }  }}

/** * Multisocket call to determine if the BIOS is responsible for updating the * northbridge operating frequency and voltage. * * This function loops through all possible socket locations, checking whether * any populated sockets require NB COF VID programming. * * @param[in]  StdHeader         Config handle for library and services * * @retval     TRUE    BIOS needs to set up NB frequency and voltage * @retval     FALSE   BIOS does not need to set up NB frequency and voltage * */BOOLEANGetSystemNbCofVidUpdateMulti (  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT8    Module;  UINT32   Socket;  UINT32   NumberOfSockets;  BOOLEAN  IgnoredBool;  BOOLEAN  AtLeast1RequiresUpdate;  PCI_ADDR PciAddress;  AGESA_STATUS Ignored;  CPU_SPECIFIC_SERVICES *FamilySpecificServices;  NumberOfSockets = GetPlatformNumberOfSockets ();  AtLeast1RequiresUpdate = FALSE;  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {        if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) {          break;        }      }      if (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &IgnoredBool, StdHeader)) {        AtLeast1RequiresUpdate = TRUE;        break;      }    }  }  return AtLeast1RequiresUpdate;}

/** *  Should P-state HPC mode be enabled *  If PlatformConfig->PStatesInHpcMode is TRUE, return TRUE, otherwise reture FALSE * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               P-state HPC mode is supported. * @retval       FALSE              P-state HPC mode cannot be enabled. * */BOOLEANSTATICIsPstateHpcModeFeatureSupported (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  BOOLEAN          IsEnabled;  UINT32           Socket;  PSTATE_HPC_MODE_FAMILY_SERVICES *FamilyServices;  IsEnabled = TRUE;  if (PlatformConfig->PStatesInHpcMode) {    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {      if (IsProcessorPresent (Socket, StdHeader)) {        GetFeatureServicesOfSocket (&PstateHpcModeFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);        if (FamilyServices == NULL) {          IsEnabled = FALSE;          break;        }      }    }  } else {    IsEnabled = FALSE;  }  return IsEnabled;}

/** *  Should Low Power P-state be enabled *  If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               Low Power P-state is supported. * @retval       FALSE              Low Power P-state cannot be enabled. * */BOOLEANSTATICIsLowPwrPstateFeatureSupported (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32              Socket;  BOOLEAN             IsSupported;  LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices;  IsSupported = FALSE;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);      if (FamilyServices != NULL) {        if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {          IsSupported = TRUE;        } else {          IsSupported = FALSE;          break;        }      } else {        IsSupported = FALSE;        break;      }    }  }  IDS_OPTION_HOOK (IDS_LOW_POWER_PSTATE, &IsSupported, StdHeader);  return IsSupported;}

/** *  Enable core performance boost * * @param[in]    EntryPoint         Timepoint designator. * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       AGESA_SUCCESS      Always succeeds. * */AGESA_STATUSSTATICInitializeCpbFeature (  IN       UINT64                 EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32              Socket;  AGESA_STATUS        AgesaStatus;  AGESA_STATUS        CalledStatus;  CPB_FAMILY_SERVICES *FamilyServices;  AgesaStatus = AGESA_SUCCESS;  CalledStatus = AGESA_SUCCESS;  IDS_HDT_CONSOLE (CPU_TRACE, "    Boost is enabled/n");  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);      if (FamilyServices != NULL) {        if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {          CalledStatus = FamilyServices->EnableCpbOnSocket (FamilyServices, PlatformConfig, EntryPoint, Socket, StdHeader);          if (CalledStatus > AgesaStatus) {            AgesaStatus = CalledStatus;          }        }      }    }  }  return AgesaStatus;}

/** *  Enable Application Power Management (APM) * * @param[in]    EntryPoint         Timepoint designator. * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       AGESA_SUCCESS      Always succeeds. * */STATIC AGESA_STATUSInitializeApmFeature (  IN       UINT64                 EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32       BscSocket;  UINT32       Ignored;  UINT32       Socket;  UINT32       NumberOfSockets;  AP_TASK      TaskPtr;  AGESA_STATUS IgnoredSts;  IDS_HDT_CONSOLE (CPU_TRACE, "    APM mode is enabled/n");  IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts);  NumberOfSockets = GetPlatformNumberOfSockets ();  TaskPtr.FuncAddress.PfApTask = EnableApmOnSocket;  TaskPtr.DataTransfer.DataSizeInDwords = 0;  TaskPtr.ExeFlags = WAIT_FOR_CORE;  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      if (Socket != BscSocket) {        ApUtilRunCodeOnSocketCore ((UINT8) Socket, 0, &TaskPtr, StdHeader);      }    }  }  EnableApmOnSocket (StdHeader);  return AGESA_SUCCESS;}

 /**  *  * This function checks the status of BIST and places the error status in the event log  * if there are any errors  *  * @param[in]      StdHeader              Header for library and services  *  * @retval         AGESA_SUCCESS          No BIST errors have been logged.  * @retval         AGESA_ALERT            BIST errors have been detected and added to the  *                                        event log.  */AGESA_STATUSCheckBistStatus (  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT32                Socket;  UINT32                Core;  UINT32                BscSocket;  UINT32                BscCoreNum;  UINT32                NumberOfSockets;  UINT32                NumberOfCores;  UINT32                Ignored;  UINT32                ReturnCode;  AGESA_STATUS          IgnoredSts;  AGESA_STATUS          AgesaStatus;  AP_TASK               TaskPtr;  // Make sure that Standard Header is valid  ASSERT (StdHeader != NULL);  ASSERT (IsBsp (StdHeader, &IgnoredSts));  AgesaStatus = AGESA_SUCCESS;  // Get the BscSocket, BscCoreNum and NumberOfSockets in the system  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);  NumberOfSockets = GetPlatformNumberOfSockets ();  // Setup TaskPtr struct to execute routine on APs  TaskPtr.FuncAddress.PfApTaskO = GetBistResults;  TaskPtr.DataTransfer.DataSizeInDwords = 0;  TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE;  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {      for (Core = 0; Core < NumberOfCores; Core++) {        if ((Socket != BscSocket) || (Core != BscCoreNum)) {          ReturnCode = ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);        } else {          ReturnCode = TaskPtr.FuncAddress.PfApTaskO (StdHeader);        }        // If BIST value is non-zero, add to BSP's event log        if (ReturnCode != 0) {          IDS_HDT_CONSOLE (CPU_TRACE, "  BIST failure: socket %d core %d, status = 0x%x/n", Socket, Core, ReturnCode);          AgesaStatus = AGESA_ALERT;          PutEventLog (AGESA_ALERT,                       CPU_EVENT_BIST_ERROR,                       ReturnCode, Socket, Core, 0, StdHeader);        }      }    }  }  return AgesaStatus;}

/** * *  InitializeCacheFlushOnHaltFeature * *    CPU feature leveling. Enable Cpu Cache Flush On Halt Function * *    @param[in]       EntryPoint       Timepoint designator. *    @param[in]       PlatformConfig   Contains the runtime modifiable feature input data. *    @param[in,out]   StdHeader        Pointer to AMD_CONFIG_PARAMS struct. * *    @return          The most severe status of any family specific service. */STATIC AGESA_STATUSInitializeCacheFlushOnHaltFeature (  IN       UINT64                 EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN OUT   AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32 Socket;  UINT32 Module;  UINT32 AndMask;  UINT32 OrMask;  UINT32 PciRegister;  PCI_ADDR PciAddress;  PCI_ADDR CfohPciAddress;  AGESA_STATUS AgesaStatus;  CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices;  ASSERT (IsBsp (StdHeader, &AgesaStatus));  FamilySpecificServices = NULL;  AndMask = 0xFFFFFFFF;  OrMask = 0x00000000;  PciRegister = 0;  AgesaStatus = AGESA_SUCCESS;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      // Get services for the socket      GetFeatureServicesOfSocket (&CacheFlushOnHaltFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);      if (FamilySpecificServices != NULL) {        FamilySpecificServices->GetCacheFlushOnHaltRegister (FamilySpecificServices, &CfohPciAddress, &AndMask, &OrMask, StdHeader);        // Get the Or Mask value from IDS        IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);        // Set Cache Flush On Halt register        for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {          if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {            PciAddress.Address.Function = CfohPciAddress.Address.Function;            PciAddress.Address.Register = CfohPciAddress.Address.Register;            LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);            PciRegister &= AndMask;            PciRegister |= OrMask;            LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);          }        }      }    }  }  return AgesaStatus;}

/** * Multisocket call to loop through all possible socket locations and Nb Pstates, * comparing the NB frequencies to determine the slowest system and P0 frequency * * @param[in]  PlatformConfig      Platform profile/build option config structure. * @param[out] MinSysNbFreq        NB frequency numerator for the system in MHz * @param[out] MinP0NbFreq         NB frequency numerator for P0 in MHz * @param[in]  StdHeader           Config handle for library and services */VOIDGetMinNbCofMulti (  IN       PLATFORM_CONFIGURATION *PlatformConfig,     OUT   UINT32                 *MinSysNbFreq,     OUT   UINT32                 *MinP0NbFreq,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32                Socket;  UINT32                Module;  UINT32                CurrMinFreq;  UINT32                CurrMaxFreq;  PCI_ADDR              PciAddress;  AGESA_STATUS          Ignored;  CPU_SPECIFIC_SERVICES *FamilySpecificServices;  AGESA_STATUS AgesaStatus;  *MinSysNbFreq = 0xFFFFFFFF;  *MinP0NbFreq  = 0xFFFFFFFF;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {        if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored )) {          break;        }      }      AgesaStatus = FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices,                                                      PlatformConfig,                                                      &PciAddress,                                                      &CurrMinFreq,                                                      &CurrMaxFreq,                                                      StdHeader);      ASSERT (AgesaStatus == AGESA_SUCCESS);      ASSERT ((CurrMinFreq != 0) && (CurrMaxFreq != 0));      // Determine the slowest NB Pmin frequency      if (CurrMinFreq < *MinSysNbFreq) {        *MinSysNbFreq = CurrMinFreq;      }      // Determine the slowest NB P0 frequency      if (CurrMaxFreq < *MinP0NbFreq) {        *MinP0NbFreq = CurrMaxFreq;      }    }  }}

/** * * *     This function get start end socket according to input SocketId * *     @param[in]   SocketId   - 0xFF means all sockets, other value Specifies real SokcetId *     @param[in,out]   StartSocket    - Point to start Socket *     @param[in,out]   EndSocket   - Point to end Socket * */VOIDIdsGetStartEndSocket (  IN       UINT8  SocketId,  IN OUT   UINT8 *StartSocket,  IN OUT   UINT8 *EndSocket  ){  if (SocketId == 0xFF) {    *StartSocket = 0;    *EndSocket = (UINT8) (GetPlatformNumberOfSockets () - 1);  } else {    *StartSocket = SocketId;    *EndSocket = SocketId;  }}

/** * * *     This function get start end Module according to input ModuleId * *     @param[in]   ModuleId   - 0xFF means all nodes, other value Specifies real NodeId *     @param[in,out]   StartModule    - Point to start Node *     @param[in,out]   EndModule   - Point to end Node * */VOIDIdsGetStartEndModule (  IN       UINT8  ModuleId,  IN OUT   UINT8 *StartModule,  IN OUT   UINT8 *EndModule  ){  if (ModuleId == 0xFF) {    *StartModule = 0;    *EndModule = (UINT8) (GetPlatformNumberOfSockets () * GetPlatformNumberOfModules () - 1);    if (*EndModule > 7) {      *EndModule = 7;    }  } else {    *StartModule = ModuleId;    *EndModule = ModuleId;  }}

/** *  Enable high performance computing (HPC mode) * * @param[in]    EntryPoint         Timepoint designator. * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       AGESA_SUCCESS      Always succeeds. * */AGESA_STATUSSTATICInitializePstateHpcModeFeature (  IN       UINT64                 EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32       BscSocket;  UINT32       Ignored;  UINT32       BscCoreNum;  UINT32       Core;  UINT32       Socket;  UINT32       NumberOfSockets;  UINT32       NumberOfCores;  AP_TASK      TaskPtr;  AGESA_STATUS IgnoredSts;  if (!IsWarmReset (StdHeader)) {    IDS_HDT_CONSOLE (CPU_TRACE, "    P-state HPC mode is enabled/n");    IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);    NumberOfSockets = GetPlatformNumberOfSockets ();    TaskPtr.FuncAddress.PfApTaskI = EnablePstateHpcModeOnAps;    TaskPtr.DataTransfer.DataSizeInDwords = 2;    TaskPtr.DataTransfer.DataPtr = PlatformConfig;    TaskPtr.DataTransfer.DataTransferFlags = 0;    TaskPtr.ExeFlags = WAIT_FOR_CORE;    for (Socket = 0; Socket < NumberOfSockets; Socket++) {      if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {        for (Core = 0; Core < NumberOfCores; Core++) {          if ((Socket != BscSocket) || (Core != BscCoreNum)) {            ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);          }        }      }    }    EnablePstateHpcModeOnAps (PlatformConfig, StdHeader);  }  return AGESA_SUCCESS;}

/** * * Run code on every AP in the system. * * @param[in] ApParams       AP task pointer. * @param[in] StdHeader      Handle to config for library and services * * @return    The most severe AGESA_STATUS returned by an AP. * */AGESA_STATUSRunLateApTaskOnAllAPs (  IN       AP_EXE_PARAMS     *ApParams,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT32                  NumberOfSockets;  UINT32                  NumberOfCores;  UINT8                   Socket;  UINT8                   Core;  UINT8                   ApicId;  UINT32                  BscSocket;  UINT32                  Ignored;  UINT32                  BscCoreNum;  AGESA_STATUS            CalledStatus;  AGESA_STATUS            IgnoredStatus;  AGESA_STATUS            AgesaStatus;  ASSERT (IsBsp (StdHeader, &IgnoredStatus));  AgesaStatus = AGESA_SUCCESS;  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredStatus);  NumberOfSockets = GetPlatformNumberOfSockets ();  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {      for (Core = 0; Core < NumberOfCores; Core++) {        if ((Socket != BscSocket) || (Core != BscCoreNum)) {          GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus);          AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader);          CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);          AGESA_TESTPOINT (TpIfAfterRunApFromAllAps, StdHeader);          if (CalledStatus > AgesaStatus) {            AgesaStatus = CalledStatus;          }        }      }    }  }  return AgesaStatus;}

/** * This function will set msr on all cores of all nodes. * * @param[in]     CpuAmdPState  Pointer to S_CPU_AMD_PSTATE. * @param[in]     StdHeader     Header for library and services. * * @retval        AGESA_SUCCESS  Always succeeds * */AGESA_STATUSStartPstateMsrModify (  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,  IN       AMD_CONFIG_PARAMS   *StdHeader  ){  AP_TASK                 TaskPtr;  UINT32                  BscSocket;  UINT32                  Ignored;  UINT32                  BscCoreNum;  UINT32                  Core;  UINT32                  Socket;  UINT32                  NumberOfSockets;  UINT32                  NumberOfCores;  AGESA_STATUS            IgnoredSts;  TaskPtr.FuncAddress.PfApTaskI = CorePstateRegModify;  TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) (CpuAmdPState->SizeOfBytes / 4 + 1);  TaskPtr.ExeFlags = WAIT_FOR_CORE;  TaskPtr.DataTransfer.DataPtr = CpuAmdPState;  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);  NumberOfSockets = GetPlatformNumberOfSockets ();  CorePstateRegModify (CpuAmdPState, StdHeader);  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {      for (Core = 0; Core < NumberOfCores; Core++) {        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);        }      }    }  }  return AGESA_SUCCESS;}

/** *--------------------------------------------------------------------------------------- * *  PutAllCoreInPState0 * *  Description: *    This function will put core pstate to p0. * *  Parameters: *    @param[in,out]    *PStateBufferPtr *    @param[in]        *StdHeader * *    @retval          AGESA_STATUS * *--------------------------------------------------------------------------------------- **/AGESA_STATUSPutAllCoreInPState0 (  IN OUT   PSTATE_LEVELING    *PStateBufferPtr,  IN       AMD_CONFIG_PARAMS  *StdHeader  ){  AP_TASK                 TaskPtr;  UINT32                  BscSocket;  UINT32                  Ignored;  UINT32                  BscCoreNum;  UINT32                  Core;  UINT32                  Socket;  UINT32                  NumberOfSockets;  UINT32                  NumberOfCores;  AGESA_STATUS            IgnoredSts;  TaskPtr.FuncAddress.PfApTaskI = PutCoreInPState0;  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PSTATE_LEVELING);  TaskPtr.ExeFlags = WAIT_FOR_CORE;  TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);  NumberOfSockets = GetPlatformNumberOfSockets ();  PutCoreInPState0 (PStateBufferPtr, StdHeader);  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {      for (Core = 0; Core < NumberOfCores; Core++) {        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);        }      }    }  }  return AGESA_SUCCESS;}

/** * *  Exit function for HDT out Function of S3 Resume * *  Restore debug register and Deallocate heap, and will also fire a HDTOUT *  Command to let hdtout script do corresponding things. * *  @param[in,out] StdHeader    The Pointer of AGESA Header * **/VOIDAmdIdsHdtOutS3ApExit (  IN OUT   AMD_CONFIG_PARAMS *StdHeader  ){  AP_TASK TaskPtr;  UINT32  Ignored;  UINT32  BscSocket;  UINT32  BscCoreNum;  UINT32  Core;  UINT32  Socket;  UINT32  NumberOfSockets;  UINT32  NumberOfCores;  AGESA_STATUS IgnoredSts;  if (AmdIdsHdtOutSupport ()) {    // run code on all APs except BSP    TaskPtr.FuncAddress.PfApTaskI = (PF_AP_TASK_I)AmdIdsHdtOutExitCoreTask;    TaskPtr.DataTransfer.DataSizeInDwords = 0;    TaskPtr.DataTransfer.DataPtr = NULL;    TaskPtr.DataTransfer.DataTransferFlags = 0;    TaskPtr.ExeFlags = WAIT_FOR_CORE;    NumberOfSockets = GetPlatformNumberOfSockets ();    IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);    for (Socket = 0; Socket < NumberOfSockets; Socket++) {      if (IsProcessorPresent (Socket, StdHeader)) {        if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {          for (Core = 0; Core < NumberOfCores; Core++) {            if ((Socket != BscSocket) || (Core != BscCoreNum)) {              ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);            }          }        }      }    }  }}

/** * * Run code on core 0 of every socket in the system. * * @param[in] ApParams       AP task pointer. * @param[in] StdHeader      Handle to config for library and services * * @return    The most severe AGESA_STATUS returned by an AP. * */AGESA_STATUSRunLateApTaskOnAllCore0s (  IN       AP_EXE_PARAMS     *ApParams,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT32                  NumberOfSockets;  UINT8                   Socket;  UINT8                   ApicId;  UINT32                  BscSocket;  UINT32                  IgnoredModule;  UINT32                  IgnoredCore;  AGESA_STATUS            CalledStatus;  AGESA_STATUS            IgnoredStatus;  AGESA_STATUS            AgesaStatus;  ASSERT (IsBsp (StdHeader, &IgnoredStatus));  AgesaStatus = AGESA_SUCCESS;  IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &IgnoredCore, &IgnoredStatus);  NumberOfSockets = GetPlatformNumberOfSockets ();  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      if (Socket != BscSocket) {        GetApicId (StdHeader, Socket, 0, &ApicId, &IgnoredStatus);        AGESA_TESTPOINT (TpIfBeforeRunApFromAllCore0s, StdHeader);        CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);        AGESA_TESTPOINT (TpIfAfterRunApFromAllCore0s, StdHeader);        if (CalledStatus > AgesaStatus) {          AgesaStatus = CalledStatus;        }      }    }  }  return AgesaStatus;}

/** *  Should Power Status Indicator (PSI) be enabled * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               PSI is supported. * @retval       FALSE              PSI cannot be enabled. * */BOOLEANSTATICIsPsiFeatureEnabled (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32                Socket;  BOOLEAN               IsEnabled;  PSI_FAMILY_SERVICES   *PsiFamilyServices;  UINT32                VrmType;  IsEnabled = FALSE;  for (VrmType = 0; VrmType < MaxVrmType; VrmType++) {    if (PlatformConfig->VrmProperties[VrmType].LowPowerThreshold != 0) {      IsEnabled = TRUE;      break;    }  }  if (!IsEnabled) {    return FALSE;  }  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetFeatureServicesOfSocket (&PsiFamilyServiceTable, Socket, (CONST VOID **)&PsiFamilyServices, StdHeader);      if ((PsiFamilyServices == NULL) || (!PsiFamilyServices->IsPsiSupported (PsiFamilyServices, Socket, PlatformConfig, StdHeader))) {        IsEnabled = FALSE;        break;      }    }  }  return IsEnabled;}

/** *  Should message-based C1e be enabled * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               Message-based C1e is supported. * @retval       FALSE              Message-based C1e cannot be enabled. * */BOOLEANSTATICIsMsgBasedC1eFeatureEnabled (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  BOOLEAN          IsEnabled;  UINT32           Socket;  MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;  ASSERT (PlatformConfig->C1eMode < MaxC1eMode);  IsEnabled = FALSE;  if ((PlatformConfig->C1eMode == C1eModeMsgBased) || (PlatformConfig->C1eMode == C1eModeAuto)) {    ASSERT (PlatformConfig->C1ePlatformData < 0x10000);    ASSERT (PlatformConfig->C1ePlatformData != 0);    if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) {      IsEnabled = TRUE;      if (IsNonCoherentHt1 (StdHeader)) {        IsEnabled = FALSE;      } else {        for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {          if (IsProcessorPresent (Socket, StdHeader)) {            GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);            if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) {              IsEnabled = FALSE;              break;            }          }        }      }    }  }  return IsEnabled;}