自学教程：C++ HALDEBUG函数代码示例

/* * Control Adaptive Noise Immunity Parameters */HAL_BOOLar9300_ani_control(struct ath_hal *ah, HAL_ANI_CMD cmd, int param){    struct ath_hal_9300 *ahp = AH9300(ah);    struct ar9300_ani_state *ani_state = ahp->ah_curani;    const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;    int32_t value, value2;    u_int level = param;    u_int is_on;    if (chan == NULL && cmd != HAL_ANI_MODE) {        HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,            "%s: ignoring cmd 0x%02x - no channel/n", __func__, cmd);        return AH_FALSE;    }    switch (cmd & ahp->ah_ani_function) {    case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION:         {            int m1_thresh_low, m2_thresh_low;            int m1_thresh, m2_thresh;            int m2_count_thr, m2_count_thr_low;            int m1_thresh_low_ext, m2_thresh_low_ext;            int m1_thresh_ext, m2_thresh_ext;            /*             * is_on == 1 means ofdm weak signal detection is ON             * (default, less noise imm)             * is_on == 0 means ofdm weak signal detection is OFF             * (more noise imm)             */            is_on = param ? 1 : 0;            if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah))                goto skip_ws_det;            /*             * make register setting for default (weak sig detect ON)             * come from INI file             */            m1_thresh_low    = is_on ?                ani_state->ini_def.m1_thresh_low    : m1_thresh_low_off;            m2_thresh_low    = is_on ?                ani_state->ini_def.m2_thresh_low    : m2_thresh_low_off;            m1_thresh       = is_on ?                ani_state->ini_def.m1_thresh       : m1_thresh_off;            m2_thresh       = is_on ?                ani_state->ini_def.m2_thresh       : m2_thresh_off;            m2_count_thr     = is_on ?                ani_state->ini_def.m2_count_thr     : m2_count_thr_off;            m2_count_thr_low  = is_on ?                ani_state->ini_def.m2_count_thr_low  : m2_count_thr_low_off;            m1_thresh_low_ext = is_on ?                ani_state->ini_def.m1_thresh_low_ext : m1_thresh_low_ext_off;            m2_thresh_low_ext = is_on ?                ani_state->ini_def.m2_thresh_low_ext : m2_thresh_low_ext_off;            m1_thresh_ext    = is_on ?                ani_state->ini_def.m1_thresh_ext    : m1_thresh_ext_off;            m2_thresh_ext    = is_on ?                ani_state->ini_def.m2_thresh_ext    : m2_thresh_ext_off;            OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,                AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low);            OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,                AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low);            OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M1_THRESH,                m1_thresh);            OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2_THRESH,                m2_thresh);            OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2COUNT_THR,                m2_count_thr);            OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,                AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low);            OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,                AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low_ext);            OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,                AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low_ext);            OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH,                m1_thresh_ext);            OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M2_THRESH,                m2_thresh_ext);skip_ws_det:            if (is_on) {                OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,                    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);            } else {                OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,                    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);            }            if (!(is_on != ani_state->ofdm_weak_sig_detect_off)) {                HALDEBUG(ah, HAL_DEBUG_ANI,                    "%s: ** ch %d: ofdm weak signal: %s=>%s/n",                    __func__, chan->ic_freq,                    !ani_state->ofdm_weak_sig_detect_off ? "on" : "off",                    is_on ? "on" : "off");                if (is_on) {                    ahp->ah_stats.ast_ani_ofdmon++;                } else {                    ahp->ah_stats.ast_ani_ofdmoff++;//.........这里部分代码省略.........

/* * Reads EEPROM header info from device structure and programs * all rf registers * * REQUIRES: Access to the analog rf device */static HAL_BOOLar2316SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain){#define	RF_BANK_SETUP(_priv, _ix, _col) do {				    /	int i;								    /	for (i = 0; i < N(ar5212Bank##_ix##_2316); i++)			    /		(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2316[i][_col];/} while (0)	struct ath_hal_5212 *ahp = AH5212(ah);	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;	uint16_t ob2GHz = 0, db2GHz = 0;	struct ar2316State *priv = AR2316(ah);	int regWrites = 0;	HALDEBUG(ah, HAL_DEBUG_RFPARAM,	    "%s: chan 0x%x flag 0x%x modesIndex 0x%x/n",	    __func__, chan->channel, chan->channelFlags, modesIndex);	HALASSERT(priv != AH_NULL);	/* Setup rf parameters */	switch (chan->channelFlags & CHANNEL_ALL) {	case CHANNEL_B:		ob2GHz = ee->ee_obFor24;		db2GHz = ee->ee_dbFor24;		break;	case CHANNEL_G:	case CHANNEL_108G:		ob2GHz = ee->ee_obFor24g;		db2GHz = ee->ee_dbFor24g;		break;	default:		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x/n",		    __func__, chan->channelFlags);		return AH_FALSE;	}	/* Bank 1 Write */	RF_BANK_SETUP(priv, 1, 1);	/* Bank 2 Write */	RF_BANK_SETUP(priv, 2, modesIndex);	/* Bank 3 Write */	RF_BANK_SETUP(priv, 3, modesIndex);	/* Bank 6 Write */	RF_BANK_SETUP(priv, 6, modesIndex);	ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz,   3, 178, 0);	ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz,   3, 175, 0);	/* Bank 7 Setup */	RF_BANK_SETUP(priv, 7, modesIndex);	/* Write Analog registers */	HAL_INI_WRITE_BANK(ah, ar5212Bank1_2316, priv->Bank1Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank2_2316, priv->Bank2Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank3_2316, priv->Bank3Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank6_2316, priv->Bank6Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank7_2316, priv->Bank7Data, regWrites);	/* Now that we have reprogrammed rfgain value, clear the flag. */	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;	return AH_TRUE;#undef	RF_BANK_SETUP}

static HAL_BOOLar2316SetPowerTable(struct ath_hal *ah,	int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan, 	uint16_t *rfXpdGain){	struct ath_hal_5212 *ahp = AH5212(ah);	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;	const RAW_DATA_STRUCT_2316 *pRawDataset = AH_NULL;	uint16_t pdGainOverlap_t2;	int16_t minCalPower2316_t2;	uint16_t *pdadcValues = ahp->ah_pcdacTable;	uint16_t gainBoundaries[4];	uint32_t reg32, regoffset;	int i, numPdGainsUsed;#ifndef AH_USE_INIPDGAIN	uint32_t tpcrg1;#endif	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x/n",	    __func__, chan->channel,chan->channelFlags);	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];	else if (IS_CHAN_B(chan))		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];	else {		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode/n", __func__);		return AH_FALSE;	}	pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),					  AR_PHY_TPCRG5_PD_GAIN_OVERLAP);    	numPdGainsUsed = ar2316getGainBoundariesAndPdadcsForPowers(ah,		chan->channel, pRawDataset, pdGainOverlap_t2,		&minCalPower2316_t2,gainBoundaries, rfXpdGain, pdadcValues);	HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);#ifdef AH_USE_INIPDGAIN	/*	 * Use pd_gains curve from eeprom; Atheros always uses	 * the default curve from the ini file but some vendors	 * (e.g. Zcomax) want to override this curve and not	 * honoring their settings results in tx power 5dBm low.	 */	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 			 (pRawDataset->pDataPerChannel[0].numPdGains - 1));#else	tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);	tpcrg1 = (tpcrg1 &~ AR_PHY_TPCRG1_NUM_PD_GAIN)		  | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);	switch (numPdGainsUsed) {	case 3:		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING3;		tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);		/* fall thru... */	case 2:		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING2;		tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);		/* fall thru... */	case 1:		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING1;		tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);		break;	}#ifdef AH_DEBUG	if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "		    "pd_gains (default 0x%x, calculated 0x%x)/n",		    __func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);#endif	OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);#endif	/*	 * Note the pdadc table may not start at 0 dBm power, could be	 * negative or greater than 0.  Need to offset the power	 * values by the amount of minPower for griffin	 */	if (minCalPower2316_t2 != 0)		ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2316_t2);	else		ahp->ah_txPowerIndexOffset = 0;	/* Finally, write the power values into the baseband power table */	regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */	for (i = 0; i < 32; i++) {		reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0)  | 			((pdadcValues[4*i + 1] & 0xFF) << 8)  |			((pdadcValues[4*i + 2] & 0xFF) << 16) |			((pdadcValues[4*i + 3] & 0xFF) << 24) ;        		OS_REG_WRITE(ah, regoffset, reg32);		regoffset += 4;	}	OS_REG_WRITE(ah, AR_PHY_TPCRG5, 		     SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 		     SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |		     SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |		     SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |//.........这里部分代码省略.........

/* * Cleanup any ANI state setup. */voidar5416AniDetach(struct ath_hal *ah){	HALDEBUG(ah, HAL_DEBUG_ANI, "Detaching Ani/n");	disableAniMIBCounters(ah);}

/* * Restore/reset the ANI parameters and reset the statistics. * This routine must be called for every channel change. * * NOTE: This is where ah_curani is set; other ani code assumes *       it is setup to reflect the current channel. */voidar5416AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,	HAL_OPMODE opmode, int restore){	struct ath_hal_5212 *ahp = AH5212(ah);	HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);	/* XXX bounds check ic_devdata */	struct ar5212AniState *aniState = &ahp->ah_ani[chan->ic_devdata];	uint32_t rxfilter;	if ((ichan->privFlags & CHANNEL_ANI_INIT) == 0) {		OS_MEMZERO(aniState, sizeof(*aniState));		if (IEEE80211_IS_CHAN_2GHZ(chan))			aniState->params = &ahp->ah_aniParams24;		else			aniState->params = &ahp->ah_aniParams5;		ichan->privFlags |= CHANNEL_ANI_INIT;		HALASSERT((ichan->privFlags & CHANNEL_ANI_SETUP) == 0);	}	ahp->ah_curani = aniState;#if 0	ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s/n",	    __func__, chan->ic_freq, chan->ic_flags, restore, opmode,	    ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");#else	HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s/n",	    __func__, chan->ic_freq, chan->ic_flags, restore, opmode,	    ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");#endif	OS_MARK(ah, AH_MARK_ANI_RESET, opmode);	/*	 * Turn off PHY error frame delivery while we futz with settings.	 */	rxfilter = ar5212GetRxFilter(ah);	ar5212SetRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);	/*	 * Automatic processing is done only in station mode right now.	 */	if (opmode == HAL_M_STA)		ahp->ah_procPhyErr |= HAL_RSSI_ANI_ENA;	else		ahp->ah_procPhyErr &= ~HAL_RSSI_ANI_ENA;	/*	 * Set all ani parameters.  We either set them to initial	 * values or restore the previous ones for the channel.	 * XXX if ANI follows hardware, we don't care what mode we're	 * XXX in, we should keep the ani parameters	 */	if (restore && (ichan->privFlags & CHANNEL_ANI_SETUP)) {		ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,				 aniState->noiseImmunityLevel);		ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,				 aniState->spurImmunityLevel);		ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,				 !aniState->ofdmWeakSigDetectOff);		ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,				 aniState->cckWeakSigThreshold);		ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,				 aniState->firstepLevel);	} else {		ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);		ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);		ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,			AH_TRUE);		ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);		ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);		ichan->privFlags |= CHANNEL_ANI_SETUP;	}	ar5416AniRestart(ah, aniState);	/* restore RX filter mask */	ar5212SetRxFilter(ah, rxfilter);}

/* * Attach for an AR9280 part. */static struct ath_hal *ar9280Attach(uint16_t devid, HAL_SOFTC sc,             HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status){    struct ath_hal_9280 *ahp9280;    struct ath_hal_5212 *ahp;    struct ath_hal *ah;    uint32_t val;    HAL_STATUS ecode;    HAL_BOOL rfStatus;    HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p/n",             __func__, sc, (void*) st, (void*) sh);    /* NB: memory is returned zero'd */    ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280));    if (ahp9280 == AH_NULL) {        HALDEBUG(AH_NULL, HAL_DEBUG_ANY,                 "%s: cannot allocate memory for state block/n", __func__);        *status = HAL_ENOMEM;        return AH_NULL;    }    ahp = AH5212(ahp9280);    ah = &ahp->ah_priv.h;    ar5416InitState(AH5416(ah), devid, sc, st, sh, status);    /* XXX override with 9280 specific state */    /* override 5416 methods for our needs */    ah->ah_setAntennaSwitch		= ar9280SetAntennaSwitch;    ah->ah_configPCIE		= ar9280ConfigPCIE;    AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;    AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;    AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;    AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;    AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;    AH5416(ah)->ah_spurMitigate	= ar9280SpurMitigate;    AH5416(ah)->ah_writeIni		= ar9280WriteIni;    AH5416(ah)->ah_rx_chainmask	= AR9280_DEFAULT_RXCHAINMASK;    AH5416(ah)->ah_tx_chainmask	= AR9280_DEFAULT_TXCHAINMASK;    if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {        /* reset chip */        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip/n",                 __func__);        ecode = HAL_EIO;        goto bad;    }    if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip/n",                 __func__);        ecode = HAL_EIO;        goto bad;    }    /* Read Revisions from Chips before taking out of reset */    val = OS_REG_READ(ah, AR_SREV);    HALDEBUG(ah, HAL_DEBUG_ATTACH,             "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x/n",             __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),             MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));    /* NB: include chip type to differentiate from pre-Sowl versions */    AH_PRIVATE(ah)->ah_macVersion =        (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;    AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);    AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;    /* setup common ini data; rf backends handle remainder */    if (AR_SREV_MERLIN_20_OR_LATER(ah)) {        HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);        HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);        HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,                     ar9280PciePhy_clkreq_always_on_L1_v2, 2);        HAL_INI_INIT(&ahp9280->ah_ini_xmodes,                     ar9280Modes_fast_clock_v2, 3);    } else {        HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6);        HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2);        HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,                     ar9280PciePhy_v1, 2);    }    ar5416AttachPCIE(ah);    ecode = ath_hal_v14EepromAttach(ah);    if (ecode != HAL_OK)        goto bad;    if (!ar5416ChipReset(ah, AH_NULL)) {	/* reset chip */        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed/n", __func__);        ecode = HAL_EIO;        goto bad;    }    AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);//.........这里部分代码省略.........

static voidar5312AniSetup(struct ath_hal *ah){	static const struct ar5212AniParams aniparams = {		.maxNoiseImmunityLevel	= 4,	/* levels 0..4 */		.totalSizeDesired	= { -41, -41, -48, -48, -48 },		.coarseHigh		= { -18, -18, -16, -14, -12 },		.coarseLow		= { -56, -56, -60, -60, -60 },		.firpwr			= { -72, -72, -75, -78, -80 },		.maxSpurImmunityLevel	= 2,		.cycPwrThr1		= { 2, 4, 6 },		.maxFirstepLevel	= 2,	/* levels 0..2 */		.firstep		= { 0, 4, 8 },		.ofdmTrigHigh		= 500,		.ofdmTrigLow		= 200,		.cckTrigHigh		= 200,		.cckTrigLow		= 100,		.rssiThrHigh		= 40,		.rssiThrLow		= 7,		.period			= 100,	};	ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);}/* * Attach for an AR5312 part. */static struct ath_hal *ar5312Attach(uint16_t devid, HAL_SOFTC sc,	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,	HAL_OPS_CONFIG *ah_config, HAL_STATUS *status){	struct ath_hal_5212 *ahp = AH_NULL;	struct ath_hal *ah;	struct ath_hal_rf *rf;	uint32_t val;	uint16_t eeval;	HAL_STATUS ecode;	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p/n",		 __func__, sc, st, (void*) sh);	/* NB: memory is returned zero'd */	ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));	if (ahp == AH_NULL) {		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,		    "%s: cannot allocate memory for state block/n", __func__);		*status = HAL_ENOMEM;		return AH_NULL;	}	ar5212InitState(ahp, devid, sc, st, sh, status);	ah = &ahp->ah_priv.h;	/* override 5212 methods for our needs */	ah->ah_reset			= ar5312Reset;	ah->ah_phyDisable		= ar5312PhyDisable;	ah->ah_setLedState		= ar5312SetLedState;	ah->ah_detectCardPresent	= ar5312DetectCardPresent;	ah->ah_setPowerMode		= ar5312SetPowerMode;	ah->ah_getPowerMode		= ar5312GetPowerMode;	ah->ah_isInterruptPending	= ar5312IsInterruptPending;	ahp->ah_priv.ah_eepromRead	= ar5312EepromRead;#ifdef AH_SUPPORT_WRITE_EEPROM	ahp->ah_priv.ah_eepromWrite	= ar5312EepromWrite;#endif#if ( AH_SUPPORT_2316 || AH_SUPPORT_2317)	if (IS_5315(ah)) {		ahp->ah_priv.ah_gpioCfgOutput	= ar5315GpioCfgOutput;		ahp->ah_priv.ah_gpioCfgInput	= ar5315GpioCfgInput;		ahp->ah_priv.ah_gpioGet		= ar5315GpioGet;		ahp->ah_priv.ah_gpioSet		= ar5315GpioSet;		ahp->ah_priv.ah_gpioSetIntr	= ar5315GpioSetIntr;	} else#endif	{		ahp->ah_priv.ah_gpioCfgOutput	= ar5312GpioCfgOutput;		ahp->ah_priv.ah_gpioCfgInput	= ar5312GpioCfgInput;		ahp->ah_priv.ah_gpioGet		= ar5312GpioGet;		ahp->ah_priv.ah_gpioSet		= ar5312GpioSet;		ahp->ah_priv.ah_gpioSetIntr	= ar5312GpioSetIntr;	}	ah->ah_gpioCfgInput		= ahp->ah_priv.ah_gpioCfgInput;	ah->ah_gpioCfgOutput		= ahp->ah_priv.ah_gpioCfgOutput;	ah->ah_gpioGet			= ahp->ah_priv.ah_gpioGet;	ah->ah_gpioSet			= ahp->ah_priv.ah_gpioSet;	ah->ah_gpioSetIntr		= ahp->ah_priv.ah_gpioSetIntr;	/* setup common ini data; rf backends handle remainder */	HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);	HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);	if (!ar5312ChipReset(ah, AH_NULL)) {	/* reset chip */		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed/n", __func__);		ecode = HAL_EIO;		goto bad;	}#if ( AH_SUPPORT_2316 || AH_SUPPORT_2317)//.........这里部分代码省略.........

HAL_BOOLar5416ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs,    uint64_t fulltsf, const char *buf, HAL_DFS_EVENT *event){	HAL_BOOL doDfsExtCh;	HAL_BOOL doDfsEnhanced;	HAL_BOOL doDfsCombinedRssi;	uint8_t rssi = 0, ext_rssi = 0;	uint8_t pulse_bw_info = 0, pulse_length_ext = 0, pulse_length_pri = 0;	uint32_t dur = 0;	int pri_found = 1, ext_found = 0;	int early_ext = 0;	int is_dc = 0;	uint16_t datalen;		/* length from the RX status field */	/* Check whether the given phy error is a radar event */	if ((rxs->rs_phyerr != HAL_PHYERR_RADAR) &&	    (rxs->rs_phyerr != HAL_PHYERR_FALSE_RADAR_EXT)) {		return AH_FALSE;	}	/* Grab copies of the capabilities; just to make the code clearer */	doDfsExtCh = AH_PRIVATE(ah)->ah_caps.halExtChanDfsSupport;	doDfsEnhanced = AH_PRIVATE(ah)->ah_caps.halEnhancedDfsSupport;	doDfsCombinedRssi = AH_PRIVATE(ah)->ah_caps.halUseCombinedRadarRssi;	datalen = rxs->rs_datalen;	/* If hardware supports it, use combined RSSI, else use chain 0 RSSI */	if (doDfsCombinedRssi)		rssi = (uint8_t) rxs->rs_rssi;	else				rssi = (uint8_t) rxs->rs_rssi_ctl[0];	/* Set this; but only use it if doDfsExtCh is set */	ext_rssi = (uint8_t) rxs->rs_rssi_ext[0];	/* Cap it at 0 if the RSSI is a negative number */	if (rssi & 0x80)		rssi = 0;	if (ext_rssi & 0x80)		ext_rssi = 0;	/*	 * Fetch the relevant data from the frame	 */	if (doDfsExtCh) {		if (datalen < 3)			return AH_FALSE;		/* Last three bytes of the frame are of interest */		pulse_length_pri = *(buf + datalen - 3);		pulse_length_ext = *(buf + datalen - 2);		pulse_bw_info = *(buf + datalen - 1);		HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, ext_rssi=%d, pulse_length_pri=%d,"		    " pulse_length_ext=%d, pulse_bw_info=%x/n",		    __func__, rssi, ext_rssi, pulse_length_pri, pulse_length_ext,		    pulse_bw_info);	} else {		/* The pulse width is byte 0 of the data */		if (datalen >= 1)			dur = ((uint8_t) buf[0]) & 0xff;		else			dur = 0;		if (dur == 0 && rssi == 0) {			HALDEBUG(ah, HAL_DEBUG_DFS, "%s: dur and rssi are 0/n", __func__);			return AH_FALSE;		}		HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, dur=%d/n", __func__, rssi, dur);		/* Single-channel only */		pri_found = 1;		ext_found = 0;	}	/*	 * If doing extended channel data, pulse_bw_info must	 * have one of the flags set.	 */	if (doDfsExtCh && pulse_bw_info == 0x0)		return AH_FALSE;			/*	 * If the extended channel data is available, calculate	 * which to pay attention to.	 */	if (doDfsExtCh) {		/* If pulse is on DC, take the larger duration of the two */		if ((pulse_bw_info & EXT_CH_RADAR_FOUND) &&		    (pulse_bw_info & PRI_CH_RADAR_FOUND)) {			is_dc = 1;			if (pulse_length_ext > pulse_length_pri) {				dur = pulse_length_ext;				pri_found = 0;				ext_found = 1;			} else {//.........这里部分代码省略.........

/* * Places the device in and out of reset and then places sane * values in the registers based on EEPROM config, initialization * vectors (as determined by the mode), and station configuration * * bChannelChange is used to preserve DMA/PCU registers across * a HW Reset during channel change. */HAL_BOOLar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,	struct ieee80211_channel *chan,	HAL_BOOL bChannelChange,	HAL_RESET_TYPE resetType,	HAL_STATUS *status){#define	N(a)	(sizeof (a) / sizeof (a[0]))#define	FAIL(_code)	do { ecode = _code; goto bad; } while (0)	struct ath_hal_5212 *ahp = AH5212(ah);	HAL_CHANNEL_INTERNAL *ichan;	const HAL_EEPROM *ee;	uint32_t saveFrameSeqCount, saveDefAntenna;	uint32_t macStaId1, synthDelay, txFrm2TxDStart;	uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL];	int16_t cckOfdmPwrDelta = 0;	u_int modesIndex, freqIndex;	HAL_STATUS ecode;	int i, regWrites = 0;	uint32_t testReg;	uint32_t saveLedState = 0;	HALASSERT(ah->ah_magic == AR5212_MAGIC);	ee = AH_PRIVATE(ah)->ah_eeprom;	OS_MARK(ah, AH_MARK_RESET, bChannelChange);	/*	 * Map public channel to private.	 */	ichan = ath_hal_checkchannel(ah, chan);	if (ichan == AH_NULL) {		HALDEBUG(ah, HAL_DEBUG_ANY,		    "%s: invalid channel %u/0x%x; no mapping/n",		    __func__, chan->ic_freq, chan->ic_flags);		FAIL(HAL_EINVAL);	}	switch (opmode) {	case HAL_M_STA:	case HAL_M_IBSS:	case HAL_M_HOSTAP:	case HAL_M_MONITOR:		break;	default:		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u/n",		    __func__, opmode);		FAIL(HAL_EINVAL);		break;	}	HALASSERT(ahp->ah_eeversion >= AR_EEPROM_VER3);	/* Preserve certain DMA hardware registers on a channel change */	if (bChannelChange) {		/*		 * On Venice, the TSF is almost preserved across a reset;		 * it requires the doubling writes to the RESET_TSF		 * bit in the AR_BEACON register; it also has the quirk		 * of the TSF going back in time on the station (station		 * latches onto the last beacon's tsf during a reset 50%		 * of the times); the latter is not a problem for adhoc		 * stations since as long as the TSF is behind, it will		 * get resynchronized on receiving the next beacon; the		 * TSF going backwards in time could be a problem for the		 * sleep operation (supported on infrastructure stations		 * only) - the best and most general fix for this situation		 * is to resynchronize the various sleep/beacon timers on		 * the receipt of the next beacon i.e. when the TSF itself		 * gets resynchronized to the AP's TSF - power save is		 * needed to be temporarily disabled until that time		 *		 * Need to save the sequence number to restore it after		 * the reset!		 */		saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);	} else		saveFrameSeqCount = 0;		/* NB: silence compiler */	/* If the channel change is across the same mode - perform a fast channel change */	if ((IS_2413(ah) || IS_5413(ah))) {		/*		 * Channel change can only be used when:		 *  -channel change requested - so it's not the initial reset.		 *  -it's not a change to the current channel - often called when switching modes		 *   on a channel		 *  -the modes of the previous and requested channel are the same - some ugly code for XR		 */		if (bChannelChange &&		    AH_PRIVATE(ah)->ah_curchan != AH_NULL &&		    (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) &&		    ((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) ==		     (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) {			if (ar5212ChannelChange(ah, chan))				/* If ChannelChange completed - skip the rest of reset *///.........这里部分代码省略.........

/* * Places the hardware into reset and then pulls it out of reset * * TODO: Only write the PLL if we're changing to or from CCK mode *  * WARNING: The order of the PLL and mode registers must be correct. */HAL_BOOLar5312ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan){	OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);	/*	 * Reset the HW 	 */	if (!ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB)) {		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed/n",		    __func__);		return AH_FALSE;	}	/* Bring out of sleep mode (AGAIN) */	if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetPowerMode failed/n",		    __func__);		return AH_FALSE;	}	/* Clear warm reset register */	if (!ar5312SetResetReg(ah, 0)) {		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed/n",		    __func__);		return AH_FALSE;	}	/*	 * Perform warm reset before the mode/PLL/turbo registers	 * are changed in order to deactivate the radio.  Mode changes	 * with an active radio can result in corrupted shifts to the	 * radio device.	 */	/*	 * Set CCK and Turbo modes correctly.	 */	if (chan != AH_NULL) {		/* NB: can be null during attach */		uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo;		if (IS_RAD5112_ANY(ah)) {			rfMode = AR_PHY_MODE_AR5112;			if (!IS_5315(ah)) {				if (IEEE80211_IS_CHAN_CCK(chan)) {					phyPLL = AR_PHY_PLL_CTL_44_5312;				} else {					if (IEEE80211_IS_CHAN_HALF(chan)) {						phyPLL = AR_PHY_PLL_CTL_40_5312_HALF;					} else if (IEEE80211_IS_CHAN_QUARTER(chan)) {						phyPLL = AR_PHY_PLL_CTL_40_5312_QUARTER;					} else {						phyPLL = AR_PHY_PLL_CTL_40_5312;					}				}			} else {				if (IEEE80211_IS_CHAN_CCK(chan))					phyPLL = AR_PHY_PLL_CTL_44_5112;				else					phyPLL = AR_PHY_PLL_CTL_40_5112;				if (IEEE80211_IS_CHAN_HALF(chan))					phyPLL |= AR_PHY_PLL_CTL_HALF;				else if (IEEE80211_IS_CHAN_QUARTER(chan))					phyPLL |= AR_PHY_PLL_CTL_QUARTER;			}		} else {			rfMode = AR_PHY_MODE_AR5111;			if (IEEE80211_IS_CHAN_CCK(chan))				phyPLL = AR_PHY_PLL_CTL_44;			else				phyPLL = AR_PHY_PLL_CTL_40;			if (IEEE80211_IS_CHAN_HALF(chan))				phyPLL = AR_PHY_PLL_CTL_HALF;			else if (IEEE80211_IS_CHAN_QUARTER(chan))				phyPLL = AR_PHY_PLL_CTL_QUARTER;		}		if (IEEE80211_IS_CHAN_G(chan))			rfMode |= AR_PHY_MODE_DYNAMIC;		else if (IEEE80211_IS_CHAN_OFDM(chan))			rfMode |= AR_PHY_MODE_OFDM;		else			rfMode |= AR_PHY_MODE_CCK;		if (IEEE80211_IS_CHAN_5GHZ(chan))			rfMode |= AR_PHY_MODE_RF5GHZ;		else			rfMode |= AR_PHY_MODE_RF2GHZ;		turbo = IEEE80211_IS_CHAN_TURBO(chan) ?			(AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0;		curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);		/*		 * PLL, Mode, and Turbo values must be written in the correct		 * order to ensure://.........这里部分代码省略.........

/* * Restore the ANI parameters in the HAL and reset the statistics. * This routine should be called for every hardware reset and for * every channel change. */voidar9300_ani_reset(struct ath_hal *ah, HAL_BOOL is_scanning){    struct ath_hal_9300 *ahp = AH9300(ah);    struct ar9300_ani_state *ani_state;    const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;    HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);    int index;    HALASSERT(chan != AH_NULL);    if (!DO_ANI(ah)) {        return;    }    /*     * we need to re-point to the correct ANI state since the channel     * may have changed due to a fast channel change    */    index = ar9300_get_ani_channel_index(ah, chan);    ani_state = &ahp->ah_ani[index];    HALASSERT(ani_state != AH_NULL);    ahp->ah_curani = ani_state;    ahp->ah_stats.ast_ani_reset++;    ani_state->phy_noise_spur = 0;    /* only allow a subset of functions in AP mode */    if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) {        if (IS_CHAN_2GHZ(ichan)) {            ahp->ah_ani_function = (HAL_ANI_SPUR_IMMUNITY_LEVEL |                                    HAL_ANI_FIRSTEP_LEVEL |                                    HAL_ANI_MRC_CCK);        } else {            ahp->ah_ani_function = 0;        }    }    /* always allow mode (on/off) to be controlled */    ahp->ah_ani_function |= HAL_ANI_MODE;    if (is_scanning ||        (AH_PRIVATE(ah)->ah_opmode != HAL_M_STA &&         AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS))    {        /*         * If we're scanning or in AP mode, the defaults (ini) should be         * in place.         * For an AP we assume the historical levels for this channel are         * probably outdated so start from defaults instead.         */        if (ani_state->ofdm_noise_immunity_level != HAL_ANI_OFDM_DEF_LEVEL ||            ani_state->cck_noise_immunity_level != HAL_ANI_CCK_DEF_LEVEL)        {            HALDEBUG(ah, HAL_DEBUG_ANI,                "%s: Restore defaults: opmode %u chan %d Mhz/0x%x "                "is_scanning=%d restore=%d ofdm:%d cck:%d/n",                __func__, AH_PRIVATE(ah)->ah_opmode, chan->ic_freq,                chan->ic_flags, is_scanning, ani_state->must_restore,                ani_state->ofdm_noise_immunity_level,                ani_state->cck_noise_immunity_level);            /*             * for STA/IBSS, we want to restore the historical values later             * (when we're not scanning)             */            if (AH_PRIVATE(ah)->ah_opmode == HAL_M_STA ||                AH_PRIVATE(ah)->ah_opmode == HAL_M_IBSS)            {                ar9300_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,                    HAL_ANI_DEF_SPUR_IMMUNE_LVL);                ar9300_ani_control(                    ah, HAL_ANI_FIRSTEP_LEVEL, HAL_ANI_DEF_FIRSTEP_LVL);                ar9300_ani_control(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,                    HAL_ANI_USE_OFDM_WEAK_SIG);                ar9300_ani_control(ah, HAL_ANI_MRC_CCK, HAL_ANI_ENABLE_MRC_CCK);                ani_state->must_restore = AH_TRUE;            } else {                ar9300_ani_set_odfm_noise_immunity_level(                    ah, HAL_ANI_OFDM_DEF_LEVEL);                ar9300_ani_set_cck_noise_immunity_level(                    ah, HAL_ANI_CCK_DEF_LEVEL);            }        }    } else {        /*         * restore historical levels for this channel         */        HALDEBUG(ah, HAL_DEBUG_ANI,            "%s: Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d "            "restore=%d ofdm:%d cck:%d/n",            __func__, AH_PRIVATE(ah)->ah_opmode, chan->ic_freq,            chan->ic_flags, is_scanning, ani_state->must_restore,            ani_state->ofdm_noise_immunity_level,            ani_state->cck_noise_immunity_level);        ar9300_ani_set_odfm_noise_immunity_level(//.........这里部分代码省略.........

/* * Internal interface to schedule periodic calibration work. */HAL_BOOLar5416PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,	u_int rxchainmask, HAL_BOOL longcal, HAL_BOOL *isCalDone){	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;	HAL_CAL_LIST *currCal = cal->cal_curr;	HAL_CHANNEL_INTERNAL *ichan;	int r;	OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq);	*isCalDone = AH_TRUE;	/*	 * Since ath_hal calls the PerCal method with rxchainmask=0x1;	 * override it with the current chainmask. The upper levels currently	 * doesn't know about the chainmask.	 */	rxchainmask = AH5416(ah)->ah_rx_chainmask;	/* Invalid channel check */	ichan = ath_hal_checkchannel(ah, chan);	if (ichan == AH_NULL) {		HALDEBUG(ah, HAL_DEBUG_ANY,		    "%s: invalid channel %u/0x%x; no mapping/n",		    __func__, chan->ic_freq, chan->ic_flags);		return AH_FALSE;	}	/*	 * For given calibration:	 * 1. Call generic cal routine	 * 2. When this cal is done (isCalDone) if we have more cals waiting	 *    (eg after reset), mask this to upper layers by not propagating	 *    isCalDone if it is set to TRUE.	 *    Instead, change isCalDone to FALSE and setup the waiting cal(s)	 *    to be run.	 */	if (currCal != AH_NULL &&	    (currCal->calState == CAL_RUNNING ||	     currCal->calState == CAL_WAITING)) {		ar5416DoCalibration(ah, ichan, rxchainmask, currCal, isCalDone);		if (*isCalDone == AH_TRUE) {			cal->cal_curr = currCal = currCal->calNext;			if (currCal->calState == CAL_WAITING) {				*isCalDone = AH_FALSE;				ar5416ResetMeasurement(ah, currCal);			}		}	}	/* Do NF cal only at longer intervals */	if (longcal) {		/* Do PA calibration if the chipset supports */		if (AH5416(ah)->ah_cal_pacal)			AH5416(ah)->ah_cal_pacal(ah, AH_FALSE);		/* Do open-loop temperature compensation if the chipset needs it */		if (ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))			AH5416(ah)->ah_olcTempCompensation(ah);		/*		 * Get the value from the previous NF cal		 * and update the history buffer.		 */		r = ar5416GetNf(ah, chan);		if (r == 0 || r == -1) {			/* NF calibration result isn't valid */			HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: NF calibration"			    " didn't finish; delaying CCA/n", __func__);		} else {			int ret;			/* 			 * NF calibration result is valid.			 *			 * Load the NF from history buffer of the current channel.			 * NF is slow time-variant, so it is OK to use a			 * historical value.			 */			ret = ar5416LoadNF(ah, AH_PRIVATE(ah)->ah_curchan);			/* start NF calibration, without updating BB NF register*/			ar5416StartNFCal(ah);			/*			 * If we failed calibration then tell the driver			 * we failed and it should do a full chip reset			 */			if (! ret)				return AH_FALSE;		}	}	return AH_TRUE;}

/* * Use HW data to do IQ Mismatch Calibration */voidar5416IQCalibration(struct ath_hal *ah, uint8_t numChains){	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;	int i;	for (i = 0; i < numChains; i++) {		uint32_t powerMeasI = cal->totalPowerMeasI(i);		uint32_t powerMeasQ = cal->totalPowerMeasQ(i);		uint32_t iqCorrMeas = cal->totalIqCorrMeas(i);		uint32_t qCoffDenom, iCoffDenom;		int iqCorrNeg;		HALDEBUG(ah, HAL_DEBUG_PERCAL,		    "Start IQ Cal and Correction for Chain %d/n", i);		HALDEBUG(ah, HAL_DEBUG_PERCAL,		    "Orignal: iq_corr_meas = 0x%08x/n", iqCorrMeas);		iqCorrNeg = 0;		/* iqCorrMeas is always negative. */ 		if (iqCorrMeas > 0x80000000)  {			iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;			iqCorrNeg = 1;		}		HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_i = 0x%08x/n",		    powerMeasI);		HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_q = 0x%08x/n",		    powerMeasQ);		HALDEBUG(ah, HAL_DEBUG_PERCAL, " iqCorrNeg is 0x%08x/n",		    iqCorrNeg);		iCoffDenom = (powerMeasI/2 + powerMeasQ/2)/ 128;		qCoffDenom = powerMeasQ / 64;		/* Protect against divide-by-0 */		if (powerMeasQ != 0) {			/* IQ corr_meas is already negated if iqcorr_neg == 1 */			int32_t iCoff = iqCorrMeas/iCoffDenom;			int32_t qCoff = powerMeasI/qCoffDenom - 64;			HALDEBUG(ah, HAL_DEBUG_PERCAL, " iCoff = 0x%08x/n",			    iCoff);			HALDEBUG(ah, HAL_DEBUG_PERCAL, " qCoff = 0x%08x/n",			    qCoff);	 			/* Negate iCoff if iqCorrNeg == 0 */			iCoff = iCoff & 0x3f;			HALDEBUG(ah, HAL_DEBUG_PERCAL,			    "New:  iCoff = 0x%08x/n", iCoff);			if (iqCorrNeg == 0x0)				iCoff = 0x40 - iCoff;			if (qCoff > 15)				qCoff = 15;			else if (qCoff <= -16)				qCoff = -16;			HALDEBUG(ah, HAL_DEBUG_PERCAL,			    " : iCoff = 0x%x  qCoff = 0x%x/n", iCoff, qCoff);			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),			    AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff);			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),			    AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff);			HALDEBUG(ah, HAL_DEBUG_PERCAL,			    "IQ Cal and Correction done for Chain %d/n", i);		}	}	OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,	    AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);}

static HAL_BOOLar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan){	static const uint32_t ar5416_cca_regs[] = {		AR_PHY_CCA,		AR_PHY_CH1_CCA,		AR_PHY_CH2_CCA,		AR_PHY_EXT_CCA,		AR_PHY_CH1_EXT_CCA,		AR_PHY_CH2_EXT_CCA	};	struct ar5212NfCalHist *h;	int i;	int32_t val;	uint8_t chainmask;	int16_t default_nf = ar5416GetDefaultNF(ah, chan);	/*	 * Force NF calibration for all chains.	 */	if (AR_SREV_KITE(ah)) {		/* Kite has only one chain */		chainmask = 0x9;	} else if (AR_SREV_MERLIN(ah) || AR_SREV_KIWI(ah)) {		/* Merlin/Kiwi has only two chains */		chainmask = 0x1B;	} else {		chainmask = 0x3F;	}	/*	 * Write filtered NF values into maxCCApwr register parameter	 * so we can load below.	 */	h = AH5416(ah)->ah_cal.nfCalHist;	HALDEBUG(ah, HAL_DEBUG_NFCAL, "CCA: ");	for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {		/* Don't write to EXT radio CCA registers unless in HT/40 mode */		/* XXX this check should really be cleaner! */		if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan))			continue;		if (chainmask & (1 << i)) { 			int16_t nf_val;			if (h)				nf_val = h[i].privNF;			else				nf_val = default_nf;			val = OS_REG_READ(ah, ar5416_cca_regs[i]);			val &= 0xFFFFFE00;			val |= (((uint32_t) nf_val << 1) & 0x1ff);			HALDEBUG(ah, HAL_DEBUG_NFCAL, "[%d: %d]", i, nf_val);			OS_REG_WRITE(ah, ar5416_cca_regs[i], val);		}	}	HALDEBUG(ah, HAL_DEBUG_NFCAL, "/n");	/* Load software filtered NF value into baseband internal minCCApwr variable. */	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);	/* Wait for load to complete, should be fast, a few 10s of us. */	if (! ar5212WaitNFCalComplete(ah, 1000)) {		/*		 * We timed out waiting for the noisefloor to load, probably due to an		 * in-progress rx. Simply return here and allow the load plenty of time		 * to complete before the next calibration interval.  We need to avoid		 * trying to load -50 (which happens below) while the previous load is		 * still in progress as this can cause rx deafness. Instead by returning		 * here, the baseband nf cal will just be capped by our present		 * noisefloor until the next calibration timer.		 */		HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "Timeout while waiting for "		    "nf to load: AR_PHY_AGC_CONTROL=0x%x/n",		    OS_REG_READ(ah, AR_PHY_AGC_CONTROL));		return AH_FALSE;	}	/*	 * Restore maxCCAPower register parameter again so that we're not capped	 * by the median we just loaded.  This will be initial (and max) value	 * of next noise floor calibration the baseband does.  	 */	for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {		/* Don't write to EXT radio CCA registers unless in HT/40 mode */		/* XXX this check should really be cleaner! */		if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan))			continue;		if (chainmask & (1 << i)) {				val = OS_REG_READ(ah, ar5416_cca_regs[i]);			val &= 0xFFFFFE00;			val |= (((uint32_t)(-50) << 1) & 0x1ff);			OS_REG_WRITE(ah, ar5416_cca_regs[i], val);		}//.........这里部分代码省略.........

static voidar9287AniSetup(struct ath_hal *ah){	/*	 * These are the parameters from the AR5416 ANI code;	 * they likely need quite a bit of adjustment for the	 * AR9287.	 */        static const struct ar5212AniParams aniparams = {                .maxNoiseImmunityLevel  = 4,    /* levels 0..4 */                .totalSizeDesired       = { -55, -55, -55, -55, -62 },                .coarseHigh             = { -14, -14, -14, -14, -12 },                .coarseLow              = { -64, -64, -64, -64, -70 },                .firpwr                 = { -78, -78, -78, -78, -80 },                .maxSpurImmunityLevel   = 7,                .cycPwrThr1             = { 2, 4, 6, 8, 10, 12, 14, 16 },                .maxFirstepLevel        = 2,    /* levels 0..2 */                .firstep                = { 0, 4, 8 },                .ofdmTrigHigh           = 500,                .ofdmTrigLow            = 200,                .cckTrigHigh            = 200,                .cckTrigLow             = 100,                .rssiThrHigh            = 40,                .rssiThrLow             = 7,                .period                 = 100,        };	/* NB: disable ANI noise immmunity for reliable RIFS rx */	AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL;        /* NB: ANI is not enabled yet */        ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);}/* * Attach for an AR9287 part. */static struct ath_hal *ar9287Attach(uint16_t devid, HAL_SOFTC sc,	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,	HAL_STATUS *status){	struct ath_hal_9287 *ahp9287;	struct ath_hal_5212 *ahp;	struct ath_hal *ah;	uint32_t val;	HAL_STATUS ecode;	HAL_BOOL rfStatus;	int8_t pwr_table_offset;	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p/n",	    __func__, sc, (void*) st, (void*) sh);	/* NB: memory is returned zero'd */	ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287));	if (ahp9287 == AH_NULL) {		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,		    "%s: cannot allocate memory for state block/n", __func__);		*status = HAL_ENOMEM;		return AH_NULL;	}	ahp = AH5212(ahp9287);	ah = &ahp->ah_priv.h;	ar5416InitState(AH5416(ah), devid, sc, st, sh, status);	if (eepromdata != AH_NULL) {		AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;		AH_PRIVATE(ah)->ah_eepromWrite = NULL;		ah->ah_eepromdata = eepromdata;	}	/* XXX override with 9280 specific state */	/* override 5416 methods for our needs */	AH5416(ah)->ah_initPLL = ar9280InitPLL;	ah->ah_setAntennaSwitch		= ar9287SetAntennaSwitch;	ah->ah_configPCIE		= ar9287ConfigPCIE;	ah->ah_disablePCIE		= ar9287DisablePCIE;	AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal;	AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal;	AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal;	AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal;	/* Better performance without ADC Gain Calibration */	AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL;	AH5416(ah)->ah_spurMitigate	= ar9280SpurMitigate;	AH5416(ah)->ah_writeIni		= ar9287WriteIni;	ah->ah_setTxPower		= ar9287SetTransmitPower;	ah->ah_setBoardValues		= ar9287SetBoardValues;	AH5416(ah)->ah_olcInit		= ar9287olcInit;	AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation;	//AH5416(ah)->ah_setPowerCalTable	= ar9287SetPowerCalTable;	AH5416(ah)->ah_cal_initcal	= ar9287InitCalHardware;	AH5416(ah)->ah_cal_pacal	= ar9287PACal;	/* XXX NF calibration *///.........这里部分代码省略.........

/* * Reads EEPROM header info from device structure and programs * all rf registers * * REQUIRES: Access to the analog rf device */static HAL_BOOLar2413SetRfRegs(struct ath_hal *ah,	const struct ieee80211_channel *chan,	uint16_t modesIndex, uint16_t *rfXpdGain){#define	RF_BANK_SETUP(_priv, _ix, _col) do {				    /	int i;								    /	for (i = 0; i < N(ar5212Bank##_ix##_2413); i++)			    /		(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2413[i][_col];/} while (0)	struct ath_hal_5212 *ahp = AH5212(ah);	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;	uint16_t ob2GHz = 0, db2GHz = 0;	struct ar2413State *priv = AR2413(ah);	int regWrites = 0;	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u/n",	    __func__, chan->ic_freq, chan->ic_flags, modesIndex);	HALASSERT(priv);	/* Setup rf parameters */	if (IEEE80211_IS_CHAN_B(chan)) {		ob2GHz = ee->ee_obFor24;		db2GHz = ee->ee_dbFor24;	} else {		ob2GHz = ee->ee_obFor24g;		db2GHz = ee->ee_dbFor24g;	}	/* Bank 1 Write */	RF_BANK_SETUP(priv, 1, 1);	/* Bank 2 Write */	RF_BANK_SETUP(priv, 2, modesIndex);	/* Bank 3 Write */	RF_BANK_SETUP(priv, 3, modesIndex);	/* Bank 6 Write */	RF_BANK_SETUP(priv, 6, modesIndex);	ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz,   3, 168, 0);	ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz,   3, 165, 0);	/* Bank 7 Setup */	RF_BANK_SETUP(priv, 7, modesIndex);	/* Write Analog registers */	HAL_INI_WRITE_BANK(ah, ar5212Bank1_2413, priv->Bank1Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank2_2413, priv->Bank2Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank3_2413, priv->Bank3Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank6_2413, priv->Bank6Data, regWrites);	HAL_INI_WRITE_BANK(ah, ar5212Bank7_2413, priv->Bank7Data, regWrites);	/* Now that we have reprogrammed rfgain value, clear the flag. */	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;	return AH_TRUE;#undef	RF_BANK_SETUP}

/* * Set all the beacon related bits on the h/w for stations * i.e. initializes the corresponding h/w timers; * also tells the h/w whether to anticipate PCF beacons */voidar5211SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs){	struct ath_hal_5211 *ahp = AH5211(ah);	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers/n", __func__);	HALASSERT(bs->bs_intval != 0);	/* if the AP will do PCF */	if (bs->bs_cfpmaxduration != 0) {		/* tell the h/w that the associated AP is PCF capable */		OS_REG_WRITE(ah, AR_STA_ID1,			OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);		/* set CFP_PERIOD(1.024ms) register */		OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);		/* set CFP_DUR(1.024ms) register to max cfp duration */		OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);		/* set TIMER2(128us) to anticipated time of next CFP */		OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);	} else {		/* tell the h/w that the associated AP is not PCF capable */		OS_REG_WRITE(ah, AR_STA_ID1,			OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);	}	/*	 * Set TIMER0(1.024ms) to the anticipated time of the next beacon.	 */	OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);	/*	 * Start the beacon timers by setting the BEACON register	 * to the beacon interval; also write the tim offset which	 * we should know by now.  The code, in ar5211WriteAssocid,	 * also sets the tim offset once the AID is known which can	 * be left as such for now.	 */	OS_REG_WRITE(ah, AR_BEACON, 		(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))		| SM(bs->bs_intval, AR_BEACON_PERIOD)		| SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)	);	/*	 * Configure the BMISS interrupt.  Note that we	 * assume the caller blocks interrupts while enabling	 * the threshold.	 */	HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));	ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)			| SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);	/*	 * Set the sleep duration in 1/8 TU's.	 */#define	SLEEP_SLOP	3	OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR,		(bs->bs_sleepduration - SLEEP_SLOP) << 3);#undef SLEEP_SLOP}

/* * Take the MHz channel value and set the Channel value * * ASSUMES: Writes enabled to analog bus */static HAL_BOOLar2413SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan){	uint16_t freq = ath_hal_gethwchannel(ah, chan);	uint32_t channelSel  = 0;	uint32_t bModeSynth  = 0;	uint32_t aModeRefSel = 0;	uint32_t reg32       = 0;	OS_MARK(ah, AH_MARK_SETCHANNEL, freq);	if (freq < 4800) {		uint32_t txctl;		if (((freq - 2192) % 5) == 0) {			channelSel = ((freq - 672) * 2 - 3040)/10;			bModeSynth = 0;		} else if (((freq - 2224) % 5) == 0) {			channelSel = ((freq - 704) * 2 - 3040) / 10;			bModeSynth = 1;		} else {			HALDEBUG(ah, HAL_DEBUG_ANY,			    "%s: invalid channel %u MHz/n",			    __func__, freq);			return AH_FALSE;		}		channelSel = (channelSel << 2) & 0xff;		channelSel = ath_hal_reverseBits(channelSel, 8);		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);		if (freq == 2484) {			/* Enable channel spreading for channel 14 */			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);		} else {			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,				txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);		}	} else if (((freq % 5) == 2) && (freq <= 5435)) {		freq = freq - 2; /* Align to even 5MHz raster */		channelSel = ath_hal_reverseBits(			(uint32_t)(((freq - 4800)*10)/25 + 1), 8);            	aModeRefSel = ath_hal_reverseBits(0, 2);	} else if ((freq % 20) == 0 && freq >= 5120) {		channelSel = ath_hal_reverseBits(			((freq - 4800) / 20 << 2), 8);		aModeRefSel = ath_hal_reverseBits(3, 2);	} else if ((freq % 10) == 0) {		channelSel = ath_hal_reverseBits(			((freq - 4800) / 10 << 1), 8);		aModeRefSel = ath_hal_reverseBits(2, 2);	} else if ((freq % 5) == 0) {		channelSel = ath_hal_reverseBits(			(freq - 4800) / 5, 8);		aModeRefSel = ath_hal_reverseBits(1, 2);	} else {		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz/n",		    __func__, freq);		return AH_FALSE;	}	reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |			(1 << 12) | 0x1;	OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);	reg32 >>= 8;	OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);	AH_PRIVATE(ah)->ah_curchan = chan;	return AH_TRUE;}

/* * Control Adaptive Noise Immunity Parameters */HAL_BOOLar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param){	typedef int TABLE[];	struct ath_hal_5212 *ahp = AH5212(ah);	struct ar5212AniState *aniState = ahp->ah_curani;	const struct ar5212AniParams *params = aniState->params;	OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);	switch (cmd) {	case HAL_ANI_NOISE_IMMUNITY_LEVEL: {		u_int level = param;		if (level >= params->maxNoiseImmunityLevel) {			HALDEBUG(ah, HAL_DEBUG_ANY,			    "%s: immunity level out of range (%u > %u)/n",			    __func__, level, params->maxNoiseImmunityLevel);			return AH_FALSE;		}		OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,		    AR_PHY_DESIRED_SZ_TOT_DES, params->totalSizeDesired[level]);		OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,		    AR_PHY_AGC_CTL1_COARSE_LOW, params->coarseLow[level]);		OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,		    AR_PHY_AGC_CTL1_COARSE_HIGH, params->coarseHigh[level]);		OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,		    AR_PHY_FIND_SIG_FIRPWR, params->firpwr[level]);		if (level > aniState->noiseImmunityLevel)			ahp->ah_stats.ast_ani_niup++;		else if (level < aniState->noiseImmunityLevel)			ahp->ah_stats.ast_ani_nidown++;		aniState->noiseImmunityLevel = level;		break;	}	case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: {		static const TABLE m1ThreshLow   = { 127,   50 };		static const TABLE m2ThreshLow   = { 127,   40 };		static const TABLE m1Thresh      = { 127, 0x4d };		static const TABLE m2Thresh      = { 127, 0x40 };		static const TABLE m2CountThr    = {  31,   16 };		static const TABLE m2CountThrLow = {  63,   48 };		u_int on = param ? 1 : 0;		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,			AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1ThreshLow[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,			AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2ThreshLow[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,			AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,			AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,			AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,			AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,			AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,			AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,			AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,			AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);		if (on) {			OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,				AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);		} else {			OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,				AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);		}		if (on)			ahp->ah_stats.ast_ani_ofdmon++;		else			ahp->ah_stats.ast_ani_ofdmoff++;		aniState->ofdmWeakSigDetectOff = !on;		break;	}	case HAL_ANI_CCK_WEAK_SIGNAL_THR: {		static const TABLE weakSigThrCck = { 8, 6 };		u_int high = param ? 1 : 0;		OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,		    AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, weakSigThrCck[high]);		if (high)			ahp->ah_stats.ast_ani_cckhigh++;		else			ahp->ah_stats.ast_ani_ccklow++;		aniState->cckWeakSigThreshold = high;		break;	}	case HAL_ANI_FIRSTEP_LEVEL: {		u_int level = param;//.........这里部分代码省略.........

/* * Process a MIB interrupt.  We may potentially be invoked because * any of the MIB counters overflow/trigger so don't assume we're * here because a PHY error counter triggered. */voidar5416ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats){	struct ath_hal_5212 *ahp = AH5212(ah);	uint32_t phyCnt1, phyCnt2;	HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "	    "filtofdm 0x%x filtcck 0x%x/n",	    __func__, OS_REG_READ(ah, AR_MIBC),	    OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),	    OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));	/*	 * First order of business is to clear whatever caused	 * the interrupt so we don't keep getting interrupted.	 * We have the usual mib counters that are reset-on-read	 * and the additional counters that appeared starting in	 * Hainan.  We collect the mib counters and explicitly	 * zero additional counters we are not using.  Anything	 * else is reset only if it caused the interrupt.	 */	/* NB: these are not reset-on-read */	phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);	phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);	/* not used, always reset them in case they are the cause */	OS_REG_WRITE(ah, AR_FILTOFDM, 0);	OS_REG_WRITE(ah, AR_FILTCCK, 0);	if ((OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING) == 0)		OS_REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);	/* Clear the mib counters and save them in the stats */	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);	ahp->ah_stats.ast_nodestats = *stats;	/*	 * Check for an ani stat hitting the trigger threshold.	 * When this happens we get a MIB interrupt and the top	 * 2 bits of the counter register will be 0b11, hence	 * the mask check of phyCnt?.	 */	if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || 	    ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {		struct ar5212AniState *aniState = ahp->ah_curani;		const struct ar5212AniParams *params = aniState->params;		uint32_t ofdmPhyErrCnt, cckPhyErrCnt;		ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;		ahp->ah_stats.ast_ani_ofdmerrs +=			ofdmPhyErrCnt - aniState->ofdmPhyErrCount;		aniState->ofdmPhyErrCount = ofdmPhyErrCnt;		cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;		ahp->ah_stats.ast_ani_cckerrs +=			cckPhyErrCnt - aniState->cckPhyErrCount;		aniState->cckPhyErrCount = cckPhyErrCnt;		/*		 * NB: figure out which counter triggered.  If both		 * trigger we'll only deal with one as the processing		 * clobbers the error counter so the trigger threshold		 * check will never be true.		 */		if (aniState->ofdmPhyErrCount > params->ofdmTrigHigh)			ar5416AniOfdmErrTrigger(ah);		if (aniState->cckPhyErrCount > params->cckTrigHigh)			ar5416AniCckErrTrigger(ah);		/* NB: always restart to insure the h/w counters are reset */		ar5416AniRestart(ah, aniState);	}}

/* * Uses the data points read from EEPROM to reconstruct the pdadc power table * Called by ar2316SetPowerTable() */static int ar2316getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,		const RAW_DATA_STRUCT_2316 *pRawDataset,		uint16_t pdGainOverlap_t2, 		int16_t  *pMinCalPower, uint16_t pPdGainBoundaries[], 		uint16_t pPdGainValues[], uint16_t pPDADCValues[]) {	struct ar2316State *priv = AR2316(ah);#define	VpdTable_L	priv->vpdTable_L#define	VpdTable_R	priv->vpdTable_R#define	VpdTable_I	priv->vpdTable_I	uint32_t ii, jj, kk;	int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */	uint32_t idxL, idxR;	uint32_t numPdGainsUsed = 0;	/* 	 * If desired to support -ve power levels in future, just	 * change pwr_I_0 to signed 5-bits.	 */	int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];	/* to accommodate -ve power levels later on. */	int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];	/* to accommodate -ve power levels later on */	uint16_t numVpd = 0;	uint16_t Vpd_step;	int16_t tmpVal ; 	uint32_t sizeCurrVpdTable, maxIndex, tgtIndex;	/* Get upper lower index */	GetLowerUpperIndex(channel, pRawDataset->pChannels,				 pRawDataset->numChannels, &(idxL), &(idxR));	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;		/* work backwards 'cause highest pdGain for lowest power */		numVpd = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].numVpd;		if (numVpd > 0) {			pPdGainValues[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pd_gain;			Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0];			if (Pmin_t2[numPdGainsUsed] >pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]) {				Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0];			}			Pmin_t2[numPdGainsUsed] = (int16_t)				(Pmin_t2[numPdGainsUsed] / 2);			Pmax_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[numVpd-1];			if (Pmax_t2[numPdGainsUsed] > pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1])				Pmax_t2[numPdGainsUsed] = 					pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1];			Pmax_t2[numPdGainsUsed] = (int16_t)(Pmax_t2[numPdGainsUsed] / 2);			ar2316FillVpdTable(					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0]), 					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_L					   );			ar2316FillVpdTable(					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]),					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_R					   );			for (kk = 0; kk < (uint16_t)(Pmax_t2[numPdGainsUsed] - Pmin_t2[numPdGainsUsed]); kk++) {				VpdTable_I[numPdGainsUsed][kk] = 					interpolate_signed(							   channel, pRawDataset->pChannels[idxL], pRawDataset->pChannels[idxR],							   (int16_t)VpdTable_L[numPdGainsUsed][kk], (int16_t)VpdTable_R[numPdGainsUsed][kk]);			}			/* fill VpdTable_I for this pdGain */			numPdGainsUsed++;		}		/* if this pdGain is used */	}	*pMinCalPower = Pmin_t2[0];	kk = 0; /* index for the final table */	for (ii = 0; ii < numPdGainsUsed; ii++) {		if (ii == (numPdGainsUsed - 1))			pPdGainBoundaries[ii] = Pmax_t2[ii] +				PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB;		else 			pPdGainBoundaries[ii] = (uint16_t)				((Pmax_t2[ii] + Pmin_t2[ii+1]) / 2 );		if (pPdGainBoundaries[ii] > 63) {			HALDEBUG(ah, HAL_DEBUG_ANY,			    "%s: clamp pPdGainBoundaries[%d] %d/n",			    __func__, ii, pPdGainBoundaries[ii]);/*XXX*/			pPdGainBoundaries[ii] = 63;		}		/* Find starting index for this pdGain */		if (ii == 0) 			ss = 0; /* for the first pdGain, start from index 0 */		else 			ss = (pPdGainBoundaries[ii-1] - Pmin_t2[ii]) - 				pdGainOverlap_t2;		Vpd_step = (uint16_t)(VpdTable_I[ii][1] - VpdTable_I[ii][0]);		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);		/*//.........这里部分代码省略.........

HAL_BOOLar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan){	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;	HAL_CHANNEL_INTERNAL *ichan;	ichan = ath_hal_checkchannel(ah, chan);	HALASSERT(ichan != AH_NULL);	/* Do initial chipset-specific calibration */	if (! AH5416(ah)->ah_cal_initcal(ah, chan)) {		HALDEBUG(ah, HAL_DEBUG_ANY,		    "%s: initial chipset calibration did "		    "not complete in time; noisy environment?/n", __func__);		return AH_FALSE;	}	/* If there's PA Cal, do it */	if (AH5416(ah)->ah_cal_pacal)		AH5416(ah)->ah_cal_pacal(ah, AH_TRUE);	/* 	 * Do NF calibration after DC offset and other CALs.	 * Per system engineers, noise floor value can sometimes be 20 dB	 * higher than normal value if DC offset and noise floor cal are	 * triggered at the same time.	 */	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);	/*	 * This may take a while to run; make sure subsequent	 * calibration routines check that this has completed	 * before reading the value and triggering a subsequent	 * calibration.	 */	/* Initialize list pointers */	cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL;	/*	 * Enable IQ, ADC Gain, ADC DC Offset Cals	 */	if (AR_SREV_HOWL(ah) || AR_SREV_SOWL_10_OR_LATER(ah)) {		/* Setup all non-periodic, init time only calibrations */		/* XXX: Init DC Offset not working yet */#if 0		if (ar5416IsCalSupp(ah, chan, ADC_DC_INIT_CAL)) {			INIT_CAL(&cal->adcDcCalInitData);			INSERT_CAL(cal, &cal->adcDcCalInitData);		}		/* Initialize current pointer to first element in list */		cal->cal_curr = cal->cal_list;		if (cal->ah_cal_curr != AH_NULL && !ar5416RunInitCals(ah, 0))			return AH_FALSE;#endif	}	/* If Cals are supported, add them to list via INIT/INSERT_CAL */	if (ar5416IsCalSupp(ah, chan, ADC_GAIN_CAL)) {		INIT_CAL(&cal->adcGainCalData);		INSERT_CAL(cal, &cal->adcGainCalData);		HALDEBUG(ah, HAL_DEBUG_PERCAL,		    "%s: enable ADC Gain Calibration./n", __func__);	}	if (ar5416IsCalSupp(ah, chan, ADC_DC_CAL)) {		INIT_CAL(&cal->adcDcCalData);		INSERT_CAL(cal, &cal->adcDcCalData);		HALDEBUG(ah, HAL_DEBUG_PERCAL,		    "%s: enable ADC DC Calibration./n", __func__);	}	if (ar5416IsCalSupp(ah, chan, IQ_MISMATCH_CAL)) {		INIT_CAL(&cal->iqCalData);		INSERT_CAL(cal, &cal->iqCalData);		HALDEBUG(ah, HAL_DEBUG_PERCAL,		    "%s: enable IQ Calibration./n", __func__);	}	/* Initialize current pointer to first element in list */	cal->cal_curr = cal->cal_list;	/* Kick off measurements for the first cal */	if (cal->cal_curr != AH_NULL)		ar5416ResetMeasurement(ah, cal->cal_curr);	/* Mark all calibrations on this channel as being invalid */	ichan->calValid = 0;	return AH_TRUE;#undef	MAX_CAL_CHECK}

/* * Take the MHz channel value and set the Channel value * * ASSUMES: Writes enabled to analog bus */static HAL_BOOLar2316SetChannel(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan){	uint32_t channelSel  = 0;	uint32_t bModeSynth  = 0;	uint32_t aModeRefSel = 0;	uint32_t reg32       = 0;	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);	if (chan->channel < 4800) {		uint32_t txctl;		if (((chan->channel - 2192) % 5) == 0) {			channelSel = ((chan->channel - 672) * 2 - 3040)/10;			bModeSynth = 0;		} else if (((chan->channel - 2224) % 5) == 0) {			channelSel = ((chan->channel - 704) * 2 - 3040) / 10;			bModeSynth = 1;		} else {			HALDEBUG(ah, HAL_DEBUG_ANY,			    "%s: invalid channel %u MHz/n",			    __func__, chan->channel);			return AH_FALSE;		}		channelSel = (channelSel << 2) & 0xff;		channelSel = ath_hal_reverseBits(channelSel, 8);		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);		if (chan->channel == 2484) {			/* Enable channel spreading for channel 14 */			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);		} else {			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,				txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);		}	} else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {		channelSel = ath_hal_reverseBits(			((chan->channel - 4800) / 20 << 2), 8);		aModeRefSel = ath_hal_reverseBits(3, 2);	} else if ((chan->channel % 10) == 0) {		channelSel = ath_hal_reverseBits(			((chan->channel - 4800) / 10 << 1), 8);		aModeRefSel = ath_hal_reverseBits(2, 2);	} else if ((chan->channel % 5) == 0) {		channelSel = ath_hal_reverseBits(			(chan->channel - 4800) / 5, 8);		aModeRefSel = ath_hal_reverseBits(1, 2);	} else {		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz/n",		    __func__, chan->channel);		return AH_FALSE;	}	reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |			(1 << 12) | 0x1;	OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);	reg32 >>= 8;	OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);	AH_PRIVATE(ah)->ah_curchan = chan;	return AH_TRUE;}

/* * Do periodic processing.  This routine is called from a timer */voidar9300_ani_ar_poll(struct ath_hal *ah, const HAL_NODE_STATS *stats,                const struct ieee80211_channel *chan, HAL_ANISTATS *ani_stats){    struct ath_hal_9300 *ahp = AH9300(ah);    struct ar9300_ani_state *ani_state;    int32_t listen_time;    u_int32_t ofdm_phy_err_rate, cck_phy_err_rate;    u_int32_t ofdm_phy_err_cnt, cck_phy_err_cnt;    HAL_BOOL old_phy_noise_spur;    ani_state = ahp->ah_curani;    ahp->ah_stats.ast_nodestats = *stats;        /* XXX optimize? */    if (ani_state == NULL) {        /* should not happen */        HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,            "%s: can't poll - no ANI not initialized for this channel/n",            __func__);        return;    }    /*     * ar9300_ani_ar_poll is never called while scanning but we may have been     * scanning and now just restarted polling.  In this case we need to     * restore historical values.     */    if (ani_state->must_restore) {        HALDEBUG(ah, HAL_DEBUG_ANI,            "%s: must restore - calling ar9300_ani_restart/n", __func__);        ar9300_ani_reset(ah, AH_FALSE);        return;    }    listen_time = ar9300_ani_get_listen_time(ah, ani_stats);    if (listen_time <= 0) {        ahp->ah_stats.ast_ani_lneg++;        /* restart ANI period if listen_time is invalid */        HALDEBUG(ah, HAL_DEBUG_ANI,            "%s: listen_time=%d - calling ar9300_ani_restart/n",            __func__, listen_time);        ar9300_ani_restart(ah);        return;    }    /* XXX beware of overflow? */    ani_state->listen_time += listen_time;    /* Clear the mib counters and save them in the stats */    ar9300_update_mib_mac_stats(ah);    /* NB: these are not reset-on-read */    ofdm_phy_err_cnt = OS_REG_READ(ah, AR_PHY_ERR_1);    cck_phy_err_cnt = OS_REG_READ(ah, AR_PHY_ERR_2);    /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */    ahp->ah_stats.ast_ani_ofdmerrs +=        ofdm_phy_err_cnt - ani_state->ofdm_phy_err_count;    ani_state->ofdm_phy_err_count = ofdm_phy_err_cnt;    ahp->ah_stats.ast_ani_cckerrs +=        cck_phy_err_cnt - ani_state->cck_phy_err_count;    ani_state->cck_phy_err_count = cck_phy_err_cnt;#if HAL_ANI_DEBUG    HALDEBUG(ah, HAL_DEBUG_ANI,        "%s: Errors: OFDM=0x%08x-0x0=%d   CCK=0x%08x-0x0=%d/n",        __func__, ofdm_phy_err_cnt, ofdm_phy_err_cnt,        cck_phy_err_cnt, cck_phy_err_cnt);#endif    /*     * If ani is not enabled, return after we've collected     * statistics     */    if (!DO_ANI(ah)) {        return;    }    ofdm_phy_err_rate =        ani_state->ofdm_phy_err_count * 1000 / ani_state->listen_time;    cck_phy_err_rate =        ani_state->cck_phy_err_count * 1000 / ani_state->listen_time;    HALDEBUG(ah, HAL_DEBUG_ANI,        "%s: listen_time=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d/n",        __func__, listen_time,        ani_state->ofdm_noise_immunity_level, ofdm_phy_err_rate,        ani_state->cck_noise_immunity_level, cck_phy_err_rate,        ani_state->ofdms_turn);    if (ani_state->listen_time >= HAL_NOISE_DETECT_PERIOD) {        old_phy_noise_spur = ani_state->phy_noise_spur;        if (ofdm_phy_err_rate <= ani_state->ofdm_trig_low &&            cck_phy_err_rate <= ani_state->cck_trig_low) {            if (ani_state->listen_time >= HAL_NOISE_RECOVER_PERIOD) {                ani_state->phy_noise_spur = 0;//.........这里部分代码省略.........