自学教程：C++ HAL_DMA_Start_IT函数代码示例

/**  * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains  *                the configuration information for SDRAM module.  * @param  pAddress: Pointer to write start address  * @param  pSrcBuffer: Pointer to source buffer to write    * @param  BufferSize: Size of the buffer to write to memory  * @retval HAL status  */HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize){  uint32_t tmp = 0U;    /* Process Locked */  __HAL_LOCK(hsdram);    /* Check the SDRAM controller state */    tmp = hsdram->State;    if(tmp == HAL_SDRAM_STATE_BUSY)  {    return HAL_BUSY;  }  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))  {    return  HAL_ERROR;   }      /* Configure DMA user callbacks */  hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;  hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;    /* Enable the DMA Stream */  HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);    /* Process Unlocked */  __HAL_UNLOCK(hsdram);    return HAL_OK;}

/**  * @brief Receive an amount of data (Control Flow) with DMA   * @param hspdif: SPDIFRX handle  * @param pData: a 32-bit pointer to the Receive data buffer.  * @param Size: number of data (Control Flow) sample to be received :  * @retval HAL status  */HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size){    if((pData == NULL) || (Size == 0))   {    return  HAL_ERROR;                                      }    if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))  {        hspdif->pCsBuffPtr = pData;    hspdif->CsXferSize = Size;    hspdif->CsXferCount = Size;    /* Process Locked */    __HAL_LOCK(hspdif);        hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;    hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;        /* Set the SPDIFRX Rx DMA Half transfer complete callback */    hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;        /* Set the SPDIFRX Rx DMA transfer complete callback */    hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;        /* Set the DMA error callback */    hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;           /* Enable the DMA request */    HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);    /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/    hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;            if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00))         {        /* Start synchronization */        __HAL_SPDIFRX_SYNC(hspdif);                /* Wait until SYNCD flag is set */      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK)      {         return HAL_TIMEOUT;      }                      /* Start reception */          __HAL_SPDIFRX_RCV(hspdif);        }            /* Process Unlocked */    __HAL_UNLOCK(hspdif);        return HAL_OK;  }  else  {    return HAL_BUSY;   }}

/**  * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains  *                the configuration information for SRAM module.  * @param  pAddress: Pointer to write start address  * @param  pSrcBuffer: Pointer to source buffer to write    * @param  BufferSize: Size of the buffer to write to memory  * @retval HAL status  */HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize){  /* Check the SRAM controller state */  if(hsram->State == HAL_SRAM_STATE_PROTECTED)  {    return  HAL_ERROR;   }    /* Process Locked */  __HAL_LOCK(hsram);    /* Update the SRAM controller state */  hsram->State = HAL_SRAM_STATE_BUSY;     /* Configure DMA user callbacks */  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;  /* Enable the DMA Stream */  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);    /* Update the SRAM controller state */  hsram->State = HAL_SRAM_STATE_READY;      /* Process unlocked */  __HAL_UNLOCK(hsram);      return HAL_OK;}

/**  * @brief  Sends an amount of data in non blocking mode.   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains  *                the configuration information for the specified IRDA module.  * @param  pData: Pointer to data buffer  * @param  Size: Amount of data to be sent  * @retval HAL status  */HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size){  uint32_t *tmp;  uint32_t  tmp1 = 0;    tmp1 = hirda->State;     if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))  {    if((pData == NULL) || (Size == 0))     {      return HAL_ERROR;    }        /* Process Locked */    __HAL_LOCK(hirda);        hirda->pTxBuffPtr = pData;    hirda->TxXferSize = Size;    hirda->TxXferCount = Size;    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;         if(hirda->State == HAL_IRDA_STATE_BUSY_RX)     {      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;    }    else    {      hirda->State = HAL_IRDA_STATE_BUSY_TX;    }        /* Set the IRDA DMA transfer complete callback */    hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;        /* Set the IRDA DMA half transfer complete callback */    hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;        /* Set the DMA error callback */    hirda->hdmatx->XferErrorCallback = IRDA_DMAError;        /* Enable the IRDA transmit DMA Stream */    tmp = (uint32_t*)&pData;    HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);        /* Clear the TC flag in the SR register by writing 0 to it */    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);        /* Enable the DMA transfer for transmit request by setting the DMAT bit       in the USART CR3 register */    hirda->Instance->CR3 |= USART_CR3_DMAT;        /* Process Unlocked */    __HAL_UNLOCK(hirda);        return HAL_OK;  }  else  {    return HAL_BUSY;     }}

int main(void) {  HAL_Init();  Nucleo_BSP_Init();  hdma_usart2_tx.Instance = DMA1_Channel7;  hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;  hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;  hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;  hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;  hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;  hdma_usart2_tx.Init.Mode = DMA_NORMAL;  hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;  hdma_usart2_tx.XferCpltCallback = &DMATransferComplete;  HAL_DMA_Init(&hdma_usart2_tx);  /* DMA interrupt init */  HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);  HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);  HAL_DMA_Start_IT(&hdma_usart2_tx,  (uint32_t)msg,  (uint32_t)&huart2.Instance->DR, strlen(msg));  //Enable UART in DMA mode  huart2.Instance->CR3 |= USART_CR3_DMAT;  /* Infinite loop */  while (1);}

/**  * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral    * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains  *         the configuration information for the specified ADC.  * @param  pData: The destination Buffer address.  * @param  Length: The length of data to be transferred from ADC peripheral to memory.  * @retval HAL status  */HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length){  uint16_t i = 0;    /* Check the parameters */  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));    /* Process locked */  __HAL_LOCK(hadc);    /* Enable ADC overrun interrupt */  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);    /* Enable ADC DMA mode */  hadc->Instance->CR2 |= ADC_CR2_DMA;    /* Set the DMA transfer complete callback */  hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;    /* Set the DMA half transfer complete callback */  hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;       /* Set the DMA error callback */  hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;    /* Enable the DMA Stream */  HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);    /* Change ADC state */  hadc->State = HAL_ADC_STATE_BUSY_REG;     /* Check if ADC peripheral is disabled in order to enable it and wait during      Tstab time the ADC's stabilization */  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)  {      /* Enable the Peripheral */    __HAL_ADC_ENABLE(hadc);        /* Delay inserted to wait during Tstab time the ADC's stabilazation */    for(; i <= 540; i++)    {      __NOP();    }  }    /* if no external trigger present enable software conversion of regular channels */  if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)  {    /* Enable the selected ADC software conversion for regular group */    hadc->Instance->CR2 |= ADC_CR2_SWSTART;  }    /* Process unlocked */  __HAL_UNLOCK(hadc);    /* Return function status */  return HAL_OK;}

/**  * @brief Send an amount of data in non blocking mode   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains  *                the configuration information for SMARTCARD module.  * @param pData: pointer to data buffer  * @param Size: amount of data to be sent  * @retval HAL status  */HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size){  uint32_t *tmp;  uint32_t tmp1 = 0;    tmp1 = hsc->State;  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))  {    if((pData == NULL) || (Size == 0))     {      return HAL_ERROR;    }    /* Process Locked */    __HAL_LOCK(hsc);    hsc->pTxBuffPtr = pData;    hsc->TxXferSize = Size;    hsc->TxXferCount = Size;    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;    /* Check if a non-blocking receive process is ongoing or not */    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)     {      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;    }    else    {      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;    }    /* Set the SMARTCARD DMA transfer complete callback */    hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;    /* Set the DMA error callback */    hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;    /* Enable the SMARTCARD transmit DMA Stream */    tmp = (uint32_t*)&pData;    HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);     /* Clear the TC flag in the SR register by writing 0 to it */    __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);        /* Enable the DMA transfer for transmit request by setting the DMAT bit    in the SMARTCARD CR3 register */    hsc->Instance->CR3 |= USART_CR3_DMAT;    /* Process Unlocked */    __HAL_UNLOCK(hsc);    return HAL_OK;  }  else  {    return HAL_BUSY;  }}

/**  * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains  *         the configuration information for the specified ADC.  * @param  pData: The destination Buffer address.  * @param  Length: The length of data to be transferred from ADC peripheral to memory.  * @retval HAL status  */HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length){    __IO uint32_t counter = 0;    /* Check the parameters */    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));    assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));    /* Process locked */    __HAL_LOCK(hadc);    /* Enable ADC overrun interrupt */    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);    /* Enable ADC DMA mode */    hadc->Instance->CR2 |= ADC_CR2_DMA;    /* Set the DMA transfer complete callback */    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;    /* Set the DMA half transfer complete callback */    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;    /* Set the DMA error callback */    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;    /* Enable the DMA Stream */    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);    /* Change ADC state */    hadc->State = HAL_ADC_STATE_BUSY_REG;    /* Process unlocked */    __HAL_UNLOCK(hadc);    /* Check if ADC peripheral is disabled in order to enable it and wait during       Tstab time the ADC's stabilization */    if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) {        /* Enable the Peripheral */        __HAL_ADC_ENABLE(hadc);        /* Delay for ADC stabilization time */        /* Compute number of CPU cycles to wait for */        counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));        while (counter != 0) {            counter--;        }    }    /* if no external trigger present enable software conversion of regular channels */    if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) {        /* Enable the selected ADC software conversion for regular group */        hadc->Instance->CR2 |= ADC_CR2_SWSTART;    }    /* Return function status */    return HAL_OK;}

/**  * @brief  Receive an amount of data in non-blocking mode.   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains  *                the configuration information for the specified IRDA module.  * @param  pData: Pointer to data buffer  * @param  Size: Amount of data to be received  * @note   When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.  * @retval HAL status  */HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size){  uint32_t *tmp = 0;  uint32_t tmp_state = 0;  tmp_state = hirda->State;  if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX))  {    if((pData == NULL) || (Size == 0))    {      return HAL_ERROR;    }    /* Process Locked */    __HAL_LOCK(hirda);    hirda->pRxBuffPtr = pData;    hirda->RxXferSize = Size;    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;    if(hirda->State == HAL_IRDA_STATE_BUSY_TX)    {      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;    }    else    {      hirda->State = HAL_IRDA_STATE_BUSY_RX;    }    /* Set the IRDA DMA transfer complete callback */    hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;    /* Set the IRDA DMA half transfert complete callback */    hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;    /* Set the DMA error callback */    hirda->hdmarx->XferErrorCallback = IRDA_DMAError;    /* Enable the DMA channel */    tmp = (uint32_t*)&pData;    HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);    /* Enable the DMA transfer for the receiver request by setting the DMAR bit        in the USART CR3 register */    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);    /* Process Unlocked */    __HAL_UNLOCK(hirda);    return HAL_OK;  }  else  {    return HAL_BUSY;  }}

/**  * @brief Receive an amount of data in DMA mode   * @param hsc: SMARTCARD handle  * @param pData: pointer to data buffer  * @param Size: amount of data to be received  * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),   *         the received data contain the parity bit (MSB position)     * @retval HAL status  */HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size){  uint32_t *tmp;    /* Check that a Rx process is not already ongoing */  if(hsc->RxState == HAL_SMARTCARD_STATE_READY)  {    if((pData == NULL) || (Size == 0U))     {      return HAL_ERROR;    }    /* Process Locked */    __HAL_LOCK(hsc);    hsc->pRxBuffPtr = pData;    hsc->RxXferSize = Size;    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;    hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;    /* Set the SMARTCARD DMA transfer complete callback */    hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;    /* Set the SMARTCARD DMA error callback */    hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;        /* Set the DMA abort callback */    hsc->hdmatx->XferAbortCallback = NULL;    /* Enable the DMA Stream */    tmp = (uint32_t*)&pData;    HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->RDR, *(uint32_t*)tmp, Size);        /* Process Unlocked */    __HAL_UNLOCK(hsc);        /* Enable the SMARTCARD Parity Error Interrupt */    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */    SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);    /* Enable the DMA transfer for the receiver request by setting the DMAR bit     in the SMARTCARD associated USART CR3 register */    SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);    return HAL_OK;  }  else  {    return HAL_BUSY;  }}

/**  * @brief  Configure the DMA controller according to the Stream parameters  *         defined in main.h file  * @note  This function is used to :  *        -1- Enable DMA2 clock  *        -2- Select the DMA functional Parameters  *        -3- Select the DMA instance to be used for the transfer  *        -4- Select Callbacks functions called after Transfer complete and                Transfer error interrupt detection  *        -5- Initialize the DMA stream  *        -6- Configure NVIC for DMA transfer complete/error interrupts  *        -7- Start the DMA transfer using the interrupt mode  * @param  None  * @retval None  */static void DMA_Config(void){     /*## -1- Enable DMA2 clock #################################################*/  __HAL_RCC_DMA2_CLK_ENABLE();  /*##-2- Select the DMA functional Parameters ###############################*/  DmaHandle.Init.Channel = DMA_CHANNEL;                     /* DMA_CHANNEL_0                    */                       DmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY;          /* M2M transfer mode                */             DmaHandle.Init.PeriphInc = DMA_PINC_ENABLE;               /* Peripheral increment mode Enable */                   DmaHandle.Init.MemInc = DMA_MINC_ENABLE;                  /* Memory increment mode Enable     */                     DmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; /* Peripheral data alignment : Word */      DmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;    /* memory data alignment : Word     */       DmaHandle.Init.Mode = DMA_NORMAL;                         /* Normal DMA mode                  */    DmaHandle.Init.Priority = DMA_PRIORITY_HIGH;              /* priority level : high            */    DmaHandle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;           /* FIFO mode disabled               */          DmaHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;    DmaHandle.Init.MemBurst = DMA_MBURST_SINGLE;              /* Memory burst                     */    DmaHandle.Init.PeriphBurst = DMA_PBURST_SINGLE;           /* Peripheral burst                 */    /*##-3- Select the DMA instance to be used for the transfer : DMA2_Stream0 #*/  DmaHandle.Instance = DMA_STREAM;  /*##-4- Select Callbacks functions called after Transfer complete and Transfer error */  DmaHandle.XferCpltCallback  = TransferComplete;  DmaHandle.XferErrorCallback = TransferError;    /*##-5- Initialize the DMA stream ##########################################*/  if(HAL_DMA_Init(&DmaHandle) != HAL_OK)  {    /* Turn LED3/LED4 on: in case of Initialization Error */    BSP_LED_On(LED3);    BSP_LED_On(LED4);    while(1)    {    }  }    /*##-6- Configure NVIC for DMA transfer complete/error interrupts ##########*/  HAL_NVIC_SetPriority(DMA_STREAM_IRQ, 0, 0);  HAL_NVIC_EnableIRQ(DMA_STREAM_IRQ);  /*##-7- Start the DMA transfer using the interrupt mode ####################*/  /* Configure the source, destination and buffer size DMA fields and Start DMA Stream transfer */  /* Enable All the DMA interrupts */  if(HAL_DMA_Start_IT(&DmaHandle, (uint32_t)&aSRC_Const_Buffer, (uint32_t)&aDST_Buffer, BUFFER_SIZE) != HAL_OK)  {    /* Turn LED3/LED4 on: Transfer error */    BSP_LED_On(LED3);    BSP_LED_On(LED4);    while(1)    {    }     }           }

/**  * @brief  Receive an amount of data in non-blocking mode.   * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains  *                the configuration information for the specified SMARTCARD module.  * @param  pData: Pointer to data buffer  * @param  Size: Amount of data to be received  * @note   When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.  * @retval HAL status  */HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size){  uint32_t *tmp = 0;  uint32_t tmp1 = 0;    tmp1 = hsc->State;  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))  {    if((pData == HAL_NULL) || (Size == 0))    {      return HAL_ERROR;    }    /* Process Locked */    __HAL_LOCK(hsc);    hsc->pRxBuffPtr = pData;    hsc->RxXferSize = Size;    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;    /* Check if a non-blocking transmit process is ongoing or not */    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)     {      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;    }    else    {      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;    }    /* Set the SMARTCARD DMA transfer complete callback */    hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;    /* Set the DMA error callback */    hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;    /* Enable the DMA channel */    tmp = (uint32_t*)&pData;    HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);    /* Enable the DMA transfer for the receiver request by setting the DMAR bit     in the SMARTCARD CR3 register */    SET_BIT(hsc->Instance->CR3,USART_CR3_DMAR);    /* Process Unlocked */    __HAL_UNLOCK(hsc);    return HAL_OK;  }  else  {    return HAL_BUSY;  }}

/**  * @brief Send an amount of data in DMA mode   * @param hsc: SMARTCARD handle  * @param pData: pointer to data buffer  * @param Size: amount of data to be sent  * @retval HAL status  */HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size){  uint32_t *tmp;    /* Check that a Tx process is not already ongoing */  if(hsc->gState == HAL_SMARTCARD_STATE_READY)  {    if((pData == NULL) || (Size == 0U))     {      return HAL_ERROR;    }    /* Process Locked */    __HAL_LOCK(hsc);    hsc->pTxBuffPtr = pData;    hsc->TxXferSize = Size;    hsc->TxXferCount = Size;    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;    hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;    /* Set the SMARTCARD DMA transfer complete callback */    hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;    /* Set the SMARTCARD error callback */    hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;        /* Set the DMA abort callback */    hsc->hdmatx->XferAbortCallback = NULL;    /* Enable the SMARTCARD transmit DMA Stream */    tmp = (uint32_t*)&pData;    HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->TDR, Size);    	/* Clear the TC flag in the SR register by writing 0 to it */    __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_FLAG_TC);        /* Process Unlocked */    __HAL_UNLOCK(hsc);    /* Enable the DMA transfer for transmit request by setting the DMAT bit       in the SMARTCARD associated USART CR3 register */    SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);    return HAL_OK;  }  else  {    return HAL_BUSY;  }}

bool LCD_DisAPhoto_DMA(uint16_t x0, uint16_t y0, uint16_t high, uint16_t wide, void *pData){	if(LCD_DMA_busy){		return false;	}	uint32_t length;	length = high * wide; //RGB565 每一像素点占用两个字节	LCD_OpenWin(x0, y0, x0+high-1, y0+wide-1);	//HAL_Delay(1);  if(HAL_DMA_Start_IT(&hDmaLCD, (uint32_t)pData, (uint32_t)&(LCD->LCD_RAM), length) != HAL_OK)  {		return false;  }	LCD_DMA_busy = 1;	return true;}

/**  * @brief  Receives an amount of data in non blocking mode.  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains  *                the configuration information for the specified IRDA module.  * @param  pData: Pointer to data buffer  * @param  Size: Amount of data to be received  * @note   When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.  * @retval HAL status  */HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size){  uint32_t *tmp;  /* Check that a Rx process is not already ongoing */  if(hirda->RxState == HAL_IRDA_STATE_READY)  {    if((pData == NULL) || (Size == 0U))    {      return HAL_ERROR;    }    /* Process Locked */    __HAL_LOCK(hirda);    hirda->pRxBuffPtr = pData;    hirda->RxXferSize = Size;    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;    /* Set the IRDA DMA transfer complete callback */    hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;    /* Set the IRDA DMA half transfer complete callback */    hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;    /* Set the DMA error callback */    hirda->hdmarx->XferErrorCallback = IRDA_DMAError;    /* Enable the DMA Stream */    tmp = (uint32_t*)&pData;    HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);    /* Enable the DMA transfer for the receiver request by setting the DMAR bit       in the USART CR3 register */    hirda->Instance->CR3 |= USART_CR3_DMAR;    /* Process Unlocked */    __HAL_UNLOCK(hirda);    return HAL_OK;  }  else  {    return HAL_BUSY;  }}

/**  * @brief  Configure the DMA controller according to the Stream parameters  *         defined in main.h file  * @note  This function is used to :  *        -1- Enable DMA1 clock  *        -2- Select the DMA functional Parameters  *        -3- Select the DMA instance to be used for the transfer  *        -4- Select Callbacks functions called after Transfer complete and               Transfer error interrupt detection  *        -5- Initialize the DMA channel  *        -6- Configure NVIC for DMA transfer complete/error interrupts  *        -7- Start the DMA transfer using the interrupt mode  * @param  None  * @retval None  */static void DMA_Config(void){  /*## -1- Enable DMA1 clock #################################################*/  __HAL_RCC_DMA1_CLK_ENABLE();  /*##-2- Select the DMA functional Parameters ###############################*/  DmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY;          /* M2M transfer mode                */  DmaHandle.Init.PeriphInc = DMA_PINC_ENABLE;               /* Peripheral increment mode Enable */  DmaHandle.Init.MemInc = DMA_MINC_ENABLE;                  /* Memory increment mode Enable     */  DmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; /* Peripheral data alignment : Word */  DmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;    /* memory data alignment : Word     */  DmaHandle.Init.Mode = DMA_NORMAL;                         /* Normal DMA mode                  */  DmaHandle.Init.Priority = DMA_PRIORITY_HIGH;              /* priority level : high            */  /*##-3- Select the DMA instance to be used for the transfer : DMA1_Channel1 #*/  DmaHandle.Instance = DMA_INSTANCE;  /*##-4- Select Callbacks functions called after Transfer complete and Transfer error */  DmaHandle.XferCpltCallback  = TransferComplete;  DmaHandle.XferErrorCallback = TransferError;  /*##-5- Initialize the DMA channel ##########################################*/  if (HAL_DMA_Init(&DmaHandle) != HAL_OK)  {    /* Initialization Error */    Error_Handler();  }  /*##-6- Configure NVIC for DMA transfer complete/error interrupts ##########*/  /* Set Interrupt Group Priority */  HAL_NVIC_SetPriority(DMA_INSTANCE_IRQ, 0, 0);  /* Enable the DMA STREAM global Interrupt */  HAL_NVIC_EnableIRQ(DMA_INSTANCE_IRQ);  /*##-7- Start the DMA transfer using the interrupt mode ####################*/  /* Configure the source, destination and buffer size DMA fields and Start DMA Channel transfer */  /* Enable All the DMA interrupts */  if (HAL_DMA_Start_IT(&DmaHandle, (uint32_t)&aSRC_Const_Buffer, (uint32_t)&aDST_Buffer, BUFFER_SIZE) != HAL_OK)  {    /* Transfer Error */    Error_Handler();  }}

/**  * @brief  Reads a Words data from the SRAM memory using DMA transfer.  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains  *                the configuration information for SRAM module.  * @param  pAddress: Pointer to read start address  * @param  pDstBuffer: Pointer to destination buffer    * @param  BufferSize: Size of the buffer to read from memory  * @retval HAL status  */HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize){  /* Process Locked */  __HAL_LOCK(hsram);      /* Update the SRAM controller state */  hsram->State = HAL_SRAM_STATE_BUSY;       /* Configure DMA user callbacks */  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;  /* Enable the DMA Channel */  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);    /* Update the SRAM controller state */  hsram->State = HAL_SRAM_STATE_READY;     /* Process unlocked */  __HAL_UNLOCK(hsram);      return HAL_OK; }

//.........这里部分代码省略.........    /* Process locked */    __HAL_LOCK(hdac);    /* Change DAC state */    hdac->State = HAL_DAC_STATE_BUSY;    if(Channel == DAC_CHANNEL_1)    {        /* Set the DMA transfer complete callback for channel1 */        hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;        /* Set the DMA half transfer complete callback for channel1 */        hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;        /* Set the DMA error callback for channel1 */        hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;        /* Enable the selected DAC channel1 DMA request */        hdac->Instance->CR |= DAC_CR_DMAEN1;        /* Case of use of channel 1 */        switch(Alignment)        {        case DAC_ALIGN_12B_R:            /* Get DHR12R1 address */            tmpreg = (uint32_t)&hdac->Instance->DHR12R1;            break;        case DAC_ALIGN_12B_L:            /* Get DHR12L1 address */            tmpreg = (uint32_t)&hdac->Instance->DHR12L1;            break;        case DAC_ALIGN_8B_R:            /* Get DHR8R1 address */            tmpreg = (uint32_t)&hdac->Instance->DHR8R1;            break;        default:            break;        }    }    else    {        /* Set the DMA transfer complete callback for channel2 */        hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;        /* Set the DMA half transfer complete callback for channel2 */        hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;        /* Set the DMA error callback for channel2 */        hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;        /* Enable the selected DAC channel2 DMA request */        hdac->Instance->CR |= DAC_CR_DMAEN2;        /* Case of use of channel 2 */        switch(Alignment)        {        case DAC_ALIGN_12B_R:            /* Get DHR12R2 address */            tmpreg = (uint32_t)&hdac->Instance->DHR12R2;            break;        case DAC_ALIGN_12B_L:            /* Get DHR12L2 address */            tmpreg = (uint32_t)&hdac->Instance->DHR12L2;            break;        case DAC_ALIGN_8B_R:            /* Get DHR8R2 address */            tmpreg = (uint32_t)&hdac->Instance->DHR8R2;            break;        default:            break;        }    }    /* Enable the DMA Stream */    if(Channel == DAC_CHANNEL_1)    {        /* Enable the DAC DMA underrun interrupt */        __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);        /* Enable the DMA Stream */        HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);    }    else    {        /* Enable the DAC DMA underrun interrupt */        __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);        /* Enable the DMA Stream */        HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);    }    /* Enable the Peripheral */    __HAL_DAC_ENABLE(hdac, Channel);    /* Process Unlocked */    __HAL_UNLOCK(hdac);    /* Return function status */    return HAL_OK;}

/**  * @brief Receive an amount of data in non-blocking mode with DMA interrupt.  * @param hswpmi: SWPMI handle  * @param pData: pointer to data buffer  * @param Size: amount of data to be received  * @retval HAL status  */HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size){  HAL_StatusTypeDef status = HAL_OK;  if((pData == NULL ) || (Size == 0))  {    status =  HAL_ERROR;  }  else  {    /* Process Locked */    __HAL_LOCK(hswpmi);    if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX))    {      /* Update handle */      hswpmi->pRxBuffPtr = pData;      hswpmi->RxXferSize = Size;      hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;      /* Check if a transmit process is ongoing or not */      if(hswpmi->State == HAL_SWPMI_STATE_READY)      {        hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;        /* Enable SWPMI peripheral if not */        SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT);      }      else      {        hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX;      }      /* Set the SWPMI DMA transfer complete callback */      hswpmi->hdmarx->XferCpltCallback = SWPMI_DMAReceiveCplt;      /* Set the SWPMI DMA Half transfer complete callback */      hswpmi->hdmarx->XferHalfCpltCallback = SWPMI_DMARxHalfCplt;      /* Set the DMA error callback */      hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError;      /* Enable the DMA request */      HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size);      /* Process Unlocked */      __HAL_UNLOCK(hswpmi);      /* Enable the DMA transfer for the receiver request by setting the RXDMA bit         in the SWPMI CR register */      SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);    }    else    {      status = HAL_BUSY;      /* Process Unlocked */      __HAL_UNLOCK(hswpmi);    }  }  return status;}

/**  * @brief Receive an amount of data in non-blocking mode with DMA   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains  *         the configuration information for I2S module  * @param pData: a 16-bit pointer to the Receive data buffer.  * @param Size: number of data sample to be sent:  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S  *       configuration phase, the Size parameter means the number of 16-bit data length   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected   *       the Size parameter means the number of 16-bit data length.   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization   *       between Master and Slave(example: audio streaming).  * @retval HAL status  */HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size){  uint32_t *tmp;  uint32_t tmp1 = 0, tmp2 = 0;      if((pData == NULL) || (Size == 0))  {    return  HAL_ERROR;  }  if(hi2s->State == HAL_I2S_STATE_READY)  {    hi2s->pRxBuffPtr = pData;    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);    if((tmp1 == I2S_DATAFORMAT_24B)|| /      (tmp2 == I2S_DATAFORMAT_32B))    {      hi2s->RxXferSize = Size*2;      hi2s->RxXferCount = Size*2;    }    else    {      hi2s->RxXferSize = Size;      hi2s->RxXferCount = Size;    }    /* Process Locked */    __HAL_LOCK(hi2s);        hi2s->State = HAL_I2S_STATE_BUSY_RX;    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;        /* Set the I2S Rx DMA Half transfer complete callback */    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;        /* Set the I2S Rx DMA transfer complete callback */    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;        /* Set the DMA error callback */    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;        /* Check if Master Receiver mode is selected */    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)    {      /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read      access to the SPI_SR register. */       __HAL_I2S_CLEAR_OVRFLAG(hi2s);    }        /* Enable the Rx DMA Stream */    tmp = (uint32_t*)&pData;    HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);        /* Check if the I2S is already enabled */     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)    {      /* Enable I2S peripheral */      __HAL_I2S_ENABLE(hi2s);    }     /* Check if the I2S Rx request is already enabled */     if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)    {      /* Enable Rx DMA Request */        hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;    }    /* Process Unlocked */    __HAL_UNLOCK(hi2s);    return HAL_OK;  }  else  {    return HAL_BUSY;  }}

/**  * @brief Transmit an amount of data in non-blocking mode with DMA  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains  *         the configuration information for I2S module  * @param pData: a 16-bit pointer to the Transmit data buffer.  * @param Size: number of data sample to be sent:  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S  *       configuration phase, the Size parameter means the number of 16-bit data length   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected   *       the Size parameter means the number of 16-bit data length.   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization   *       between Master and Slave(example: audio streaming).  * @retval HAL status  */HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size){  uint32_t *tmp;  uint32_t tmp1 = 0, tmp2 = 0;         if((pData == NULL) || (Size == 0))   {    return  HAL_ERROR;  }  if(hi2s->State == HAL_I2S_STATE_READY)  {      hi2s->pTxBuffPtr = pData;    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);    if((tmp1 == I2S_DATAFORMAT_24B)|| /      (tmp2 == I2S_DATAFORMAT_32B))    {      hi2s->TxXferSize = Size*2;      hi2s->TxXferCount = Size*2;    }    else    {      hi2s->TxXferSize = Size;      hi2s->TxXferCount = Size;    }    /* Process Locked */    __HAL_LOCK(hi2s);    hi2s->State = HAL_I2S_STATE_BUSY_TX;    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;    /* Set the I2S Tx DMA Half transfer complete callback */    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;    /* Set the I2S Tx DMA transfer complete callback */    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;    /* Set the DMA error callback */    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;    /* Enable the Tx DMA Stream */    tmp = (uint32_t*)&pData;    HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);    /* Check if the I2S is already enabled */     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)    {      /* Enable I2S peripheral */      __HAL_I2S_ENABLE(hi2s);    }     /* Check if the I2S Tx request is already enabled */     if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)    {      /* Enable Tx DMA Request */        hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;    }    /* Process Unlocked */    __HAL_UNLOCK(hi2s);        return HAL_OK;  }  else  {    return HAL_BUSY;  }}

//.........这里部分代码省略.........  /* Set a temporary handle of the ADC slave associated to the ADC master     */  ADC_MULTI_SLAVE(hadc, &tmphadcSlave);    /* On STM32F1 devices, ADC slave regular group must be configured with      */  /* conversion trigger ADC_SOFTWARE_START.                                   */  /* Note: External trigger of ADC slave must be enabled, it is already done  */  /*       into function "HAL_ADC_Init()".                                    */  if ((tmphadcSlave.Instance == NULL)                 ||      (! ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave))  )  {    /* Update ADC state machine to error */    hadc->State = HAL_ADC_STATE_ERROR;        /* Process unlocked */    __HAL_UNLOCK(hadc);        return HAL_ERROR;  }  /* Enable the ADC peripherals: master and slave (in case if not already     */  /* enabled previously)                                                      */  tmp_hal_status = ADC_Enable(hadc);  if (tmp_hal_status != HAL_ERROR)  {    tmp_hal_status = ADC_Enable(&tmphadcSlave);  }    /* Start conversion all ADCs of multimode are effectively enabled */  if (tmp_hal_status != HAL_ERROR)  {    /* State machine update (ADC master): Check if an injected conversion is  */    /* ongoing.                                                               */    if(hadc->State == HAL_ADC_STATE_BUSY_INJ)    {      /* Change ADC state */      hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;    }    else    {      /* Change ADC state */      hadc->State = HAL_ADC_STATE_BUSY_REG;    }          /* Process unlocked */    /* Unlock before starting ADC conversions: in case of potential           */    /* interruption, to let the process to ADC IRQ Handler.                   */    __HAL_UNLOCK(hadc);      /* Set ADC error code to none */    ADC_CLEAR_ERRORCODE(hadc);            /* Set the DMA transfer complete callback */    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;           /* Set the DMA half transfer complete callback */    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;        /* Set the DMA error callback */    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;        /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */    /* start (in case of SW start):                                           */        /* Clear regular group conversion flag and overrun flag */    /* (To ensure of no unknown state from potential previous ADC operations) */    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);        /* Enable ADC DMA mode of ADC master */    SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);        /* Start the DMA channel */    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);        /* Start conversion of regular group if software start has been selected. */    /* If external trigger has been selected, conversion will start at next   */    /* trigger event.                                                         */    /* Note: Alternate trigger for single conversion could be to force an     */    /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/    if (ADC_IS_SOFTWARE_START_REGULAR(hadc))    {      /* Start ADC conversion on regular group with SW start */      SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));    }    else    {      /* Start ADC conversion on regular group with external trigger */      SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);    }  }  else  {    /* Process unlocked */    __HAL_UNLOCK(hadc);  }    /* Return function status */  return tmp_hal_status;}

/**  * @brief  Enables DCMI DMA request and enables DCMI capture    * @param  hdcmi:     pointer to a DCMI_HandleTypeDef structure that contains  *                    the configuration information for DCMI.  * @param  DCMI_Mode: DCMI capture mode snapshot or continuous grab.  * @param  pData:     The destination memory Buffer address (LCD Frame buffer).  * @param  Length:    The length of capture to be transferred.  * @retval HAL status  */HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length){    /* Initialize the second memory address */  uint32_t SecondMemAddress = 0;  /* Check function parameters */  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));  /* Process Locked */  __HAL_LOCK(hdcmi);  /* Lock the DCMI peripheral state */  hdcmi->State = HAL_DCMI_STATE_BUSY;  /* Check the parameters */  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));  /* Configure the DCMI Mode */  hdcmi->Instance->CR &= ~(DCMI_CR_CM);  hdcmi->Instance->CR |=  (uint32_t)(DCMI_Mode);  /* Set the DMA memory0 conversion complete callback */  hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAConvCplt;  /* Set the DMA error callback */  hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;  if(Length <= 0xFFFF)  {    /* Enable the DMA Stream */    HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);  }  else /* DCMI_DOUBLE_BUFFER Mode */  {    /* Set the DMA memory1 conversion complete callback */    hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt;     /* Initialize transfer parameters */    hdcmi->XferCount = 1;    hdcmi->XferSize = Length;    hdcmi->pBuffPtr = pData;          /* Get the number of buffer */    while(hdcmi->XferSize > 0xFFFF)    {      hdcmi->XferSize = (hdcmi->XferSize/2);      hdcmi->XferCount = hdcmi->XferCount*2;    }    /* Update DCMI counter  and transfer number*/    hdcmi->XferCount = (hdcmi->XferCount - 2);    hdcmi->XferTransferNumber = hdcmi->XferCount;    /* Update second memory address */    SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));    /* Start DMA multi buffer transfer */    HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);  }  /* Enable Capture */  DCMI->CR |= DCMI_CR_CAPTURE;  /* Return function status */  return HAL_OK;}

/**  * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA    * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains  *         the configuration information for I2S module  * @param pTxData: a 16-bit pointer to the Transmit data buffer.  * @param pRxData: a 16-bit pointer to the Receive data buffer.  * @param Size: number of data sample to be sent:  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S  *       configuration phase, the Size parameter means the number of 16-bit data length   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected   *       the Size parameter means the number of 16-bit data length.   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization   *       between Master and Slave(example: audio streaming).  * @retval HAL status  */HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size){  uint32_t *tmp;  uint32_t tmp1 = 0, tmp2 = 0;      if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))   {    return  HAL_ERROR;  }  if(hi2s->State == HAL_I2S_STATE_READY)  {    hi2s->pTxBuffPtr = pTxData;    hi2s->pRxBuffPtr = pRxData;    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);    /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended        is selected during the I2S configuration phase, the Size parameter means the number       of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data        frame is selected the Size parameter means the number of 16-bit data length. */    if((tmp1 == I2S_DATAFORMAT_24B)||/       (tmp2 == I2S_DATAFORMAT_32B))    {      hi2s->TxXferSize = Size*2;      hi2s->TxXferCount = Size*2;      hi2s->RxXferSize = Size*2;      hi2s->RxXferCount = Size*2;    }    else    {      hi2s->TxXferSize = Size;      hi2s->TxXferCount = Size;      hi2s->RxXferSize = Size;      hi2s->RxXferCount = Size;    }    /* Process Locked */    __HAL_LOCK(hi2s);    hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;    /* Set the I2S Rx DMA Half transfert complete callback */    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;    /* Set the I2S Rx DMA transfert complete callback */    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;    /* Set the I2S Rx DMA error callback */    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;    /* Set the I2S Tx DMA Half transfert complete callback */    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;    /* Set the I2S Tx DMA transfert complete callback */    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;    /* Set the I2S Tx DMA error callback */    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;    tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))    {      /* Enable the Rx DMA Stream */      tmp = (uint32_t*)&pRxData;      HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);      /* Enable Rx DMA Request */        I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;      /* Enable the Tx DMA Stream */      tmp = (uint32_t*)&pTxData;      HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);      /* Enable Tx DMA Request */        hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;      /* Check if the I2S is already enabled */       if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)      {        /* Enable I2Sext(receiver) before enabling I2Sx peripheral */        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;//.........这里部分代码省略.........

/**  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains  *         the configuration information for I2S module  * @param  pTxData: a 16-bit pointer to the Transmit data buffer.  * @param  pRxData: a 16-bit pointer to the Receive data buffer.  * @param  Size: number of frames to be sent.  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization   *         between Master and Slave(example: audio streaming).  * @retval HAL status  */HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size){  /* Check Mode parameter */  assert_param(IS_I2S_FD_MODE(hi2s->Init.Mode));  if((pTxData == NULL) || (Size == 0U))   {    return  HAL_ERROR;  }  /* Process Locked */  __HAL_LOCK(hi2s);  if(hi2s->State == HAL_I2S_STATE_READY)  {      hi2s->pTxBuffPtr = pTxData;    hi2s->pRxBuffPtr = pRxData;    hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||/      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))    {      hi2s->TxXferSize  = (Size << 1U);      hi2s->TxXferCount = (Size << 1U);      hi2s->RxXferSize  = (Size << 1U);      hi2s->RxXferCount = (Size << 1U);    }    else    {      hi2s->TxXferSize  = Size;      hi2s->TxXferCount = Size;      hi2s->RxXferSize  = Size;      hi2s->RxXferCount = Size;    }    /* Set the I2S Rx DMA Half transfert complete callback */    hi2s->hdmarx->XferHalfCpltCallback = I2SEx_DMATxRxHalfCplt;    /* Set the I2S Rx DMA transfert complete callback */    hi2s->hdmarx->XferCpltCallback = I2SEx_DMATxRxCplt;    /* Set the DMA error callback */    hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;    /* Enable the Rx DMA Channel */    HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);    /* Check if the I2S Rx requests are already enabled */     if(HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))    {      /* Check if the SPI2S is disabled to edit CFG1 register */      if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)      {        /* Enable Rx DMA Request */        SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);      }      else      {        /* Disable SPI peripheral */        __HAL_I2S_DISABLE(hi2s);            /* Enable Rx DMA Request */        SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);        /* Enable SPI peripheral */        __HAL_I2S_ENABLE(hi2s);      }    }    /* Set the I2S Tx DMA transfer callbacks as NULL because the communication closing    is performed in DMA reception callbacks */    hi2s->hdmatx->XferHalfCpltCallback = NULL;    hi2s->hdmatx->XferCpltCallback     = NULL;    hi2s->hdmatx->XferErrorCallback    = NULL;    /* Enable the Tx DMA Channel */    HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize);    /* Check if the I2S Tx requests are already enabled */     if(HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))    {      /* Check if the SPI2S is disabled to edit CFG1 register */      if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)      {        /* Enable Tx DMA Request */        SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);//.........这里部分代码省略.........

/**  * @brief Receive an amount of data (Control Flow) with DMA  * @param hspdif SPDIFRX handle  * @param pData a 32-bit pointer to the Receive data buffer.  * @param Size number of data (Control Flow) sample to be received :  * @retval HAL status  */HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size){  __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);  if((pData == NULL) || (Size == 0))  {    return  HAL_ERROR;  }  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))  {    hspdif->pCsBuffPtr = pData;    hspdif->CsXferSize = Size;    hspdif->CsXferCount = Size;    /* Process Locked */    __HAL_LOCK(hspdif);    hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;    hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;    /* Set the SPDIFRX Rx DMA Half transfer complete callback */    hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;    /* Set the SPDIFRX Rx DMA transfer complete callback */    hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;    /* Set the DMA error callback */    hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;    /* Enable the DMA request */    HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);    /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/    hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)    {      /* Start synchronization */      __HAL_SPDIFRX_SYNC(hspdif);      /* Wait until SYNCD flag is set */      do      {        if (count-- == 0U)        {          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);          hspdif->State= HAL_SPDIFRX_STATE_READY;          /* Process Unlocked */          __HAL_UNLOCK(hspdif);          return HAL_TIMEOUT;        }      }      while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);      /* Start reception */      __HAL_SPDIFRX_RCV(hspdif);    }    /* Process Unlocked */    __HAL_UNLOCK(hspdif);    return HAL_OK;  }  else  {    return HAL_BUSY;  }}

int main(void){  /* USER CODE BEGIN 1 */  /* USER CODE END 1 */  /* MCU Configuration----------------------------------------------------------*/  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */  HAL_Init();  /* Configure the system clock */  SystemClock_Config();  /* Initialize all configured peripherals */  MX_GPIO_Init();  MX_DMA_Init();  MX_FMC_Init();  MX_DMA2D_Init();  MX_LTDC_Init();  MX_SPI5_Init();  /* USER CODE BEGIN 2 */  /* USER CODE END 2 */  /* Infinite loop */  /* USER CODE BEGIN WHILE */	HAL_GPIO_TogglePin(green_led_GPIO_Port,green_led_Pin);  while (1)  {  /* USER CODE END WHILE */  /* USER CODE BEGIN 3 */		HAL_GPIO_TogglePin(red_led_GPIO_Port,red_led_Pin);		HAL_GPIO_TogglePin(green_led_GPIO_Port,green_led_Pin);		HAL_Delay(1000);					p = (uint32_t*)sdram_start_address;		//r(i=0;i<8*1024*1024;i+=4){			//HAL_SDRAM_Write_32b(&hsdram1,(uint32_t*)(sdram_start_address+i),&pattern,1);						//(__IO uint32_t *)(p++) = pattern;//}				//L_DMA_XFER_CPLT_CB_ID		pattern = rand();				HAL_DMA_RegisterCallback(&hdma_memtomem_dma2_stream0,HAL_DMA_XFER_CPLT_CB_ID,myDMA_Callback);		for(i=0;i<2;i++){			HAL_DMA_Start_IT(&hdma_memtomem_dma2_stream0,			(uint32_t)&pattern,			(uint32_t)p,38400);			p+=38400;			while(!done);			done = 0;		}		HAL_Delay(1000);		start = HAL_GetTick();	//todo add mandelbrot here		{			 float sx,ex,sy,ey;			 float	zof = 0.00001;		   float zfi = 0.00001;			sx = -1.4481471; ex = -1.4472926; sy = -0.0012840417; ey = -0.00030747990;						while(zof<0.00163999794){								drawset2(sx, ex, sy, ey);								zof+=zfi;				sx -= zof;				ex += zof;				sy -= zof;				ey += zof;								HAL_Delay(16);			}								}		//HAL_Delay(1000);		//drawset2(-1.4494717,-1.4477627,-0.0017153568,0.00023776683);						stop = HAL_GetTick();		delta = stop- start;		#if 0		p = (uint32_t*)sdram_start_address;		for(i=0;i<128*65532;i+=4){			//HAL_SDRAM_Read_32b(&hsdram1,(uint32_t*)(sdram_start_address+i),&read_pattern,1);			read_pattern = *(__IO uint32_t *)(p++);			if(read_pattern!=0xaa55aa55)			{				while(1){					HAL_GPIO_TogglePin(red_led_GPIO_Port,red_led_Pin);					HAL_GPIO_TogglePin(green_led_GPIO_Port,green_led_Pin);					HAL_Delay(50);				}//.........这里部分代码省略.........

//.........这里部分代码省略.........  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));    /* Process locked */  __HAL_LOCK(hadc);    /* Check if ADC peripheral is disabled in order to enable it and wait during      Tstab time the ADC's stabilization */  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)  {      /* Enable the Peripheral */    __HAL_ADC_ENABLE(hadc);        /* Delay for temperature sensor stabilization time */    /* Compute number of CPU cycles to wait for */    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));    while(counter != 0U)    {      counter--;    }  }    /* Start conversion if ADC is effectively enabled */  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))  {    /* Set ADC state                                                          */    /* - Clear state bitfield related to regular group conversion results     */    /* - Set state bitfield related to regular group operation                */    ADC_STATE_CLR_SET(hadc->State,                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,                      HAL_ADC_STATE_REG_BUSY);        /* If conversions on group regular are also triggering group injected,    */    /* update ADC state.                                                      */    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)    {      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);      }        /* State machine update: Check if an injected conversion is ongoing */    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))    {      /* Reset ADC error code fields related to conversions on group regular */      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));             }    else    {      /* Reset ADC all error code fields */      ADC_CLEAR_ERRORCODE(hadc);    }        /* Process unlocked */    /* Unlock before starting ADC conversions: in case of potential           */    /* interruption, to let the process to ADC IRQ Handler.                   */    __HAL_UNLOCK(hadc);        /* Set the DMA transfer complete callback */    hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;        /* Set the DMA half transfer complete callback */    hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;        /* Set the DMA error callback */    hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;        /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */    /* start (in case of SW start):                                           */        /* Clear regular group conversion flag and overrun flag */    /* (To ensure of no unknown state from potential previous ADC operations) */    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);    /* Enable ADC overrun interrupt */    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);        if (hadc->Init.DMAContinuousRequests != DISABLE)    {      /* Enable the selected ADC DMA request after last transfer */      ADC->CCR |= ADC_CCR_DDS;    }    else    {      /* Disable the selected ADC EOC rising on each regular channel conversion */      ADC->CCR &= ~ADC_CCR_DDS;    }        /* Enable the DMA Stream */    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);        /* if no external trigger present enable software conversion of regular channels */    if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)     {      /* Enable the selected ADC software conversion for regular group */      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;    }  }    /* Return function status */  return HAL_OK;}

/**  * @brief Transmit an amount of data in non-blocking mode with DMA  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains  *         the configuration information for I2S module  * @param pData: a 16-bit pointer to the Transmit data buffer.  * @param Size: number of data sample to be sent:  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S  *       configuration phase, the Size parameter means the number of 16-bit data length   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected   *       the Size parameter means the number of 16-bit data length.   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization   *       between Master and Slave(example: audio streaming).  * @retval HAL status  */HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size){  if((pData == NULL) || (Size == 0))   {    return  HAL_ERROR;  }  /* Process Locked */  __HAL_LOCK(hi2s);  if(hi2s->State == HAL_I2S_STATE_READY)  {      hi2s->pTxBuffPtr = pData;    hi2s->State = HAL_I2S_STATE_BUSY_TX;    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||/      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))    {      hi2s->TxXferSize = (Size << 1);      hi2s->TxXferCount = (Size << 1);    }    else    {      hi2s->TxXferSize = Size;      hi2s->TxXferCount = Size;    }    /* Set the I2S Tx DMA Half transfert complete callback */    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;    /* Set the I2S Tx DMA transfert complete callback */    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;    /* Set the DMA error callback */    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;    /* Enable the Tx DMA Channel */    HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);    /* Check if the I2S is already enabled */     if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))    {      /* Enable I2S peripheral */      __HAL_I2S_ENABLE(hi2s);    }    /* Check if the I2S Tx request is already enabled */     if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))    {      /* Enable Tx DMA Request */        SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);    }    /* Process Unlocked */    __HAL_UNLOCK(hi2s);        return HAL_OK;  }  else  {    /* Process Unlocked */    __HAL_UNLOCK(hi2s);    return HAL_BUSY;  }}